diff options
Diffstat (limited to 'riscv64-asm.c')
-rw-r--r-- | riscv64-asm.c | 374 |
1 files changed, 187 insertions, 187 deletions
diff --git a/riscv64-asm.c b/riscv64-asm.c index fbb60ba..30662df 100644 --- a/riscv64-asm.c +++ b/riscv64-asm.c @@ -9,9 +9,9 @@ #define CONFIG_TCC_ASM #define NB_ASM_REGS 32 -ST_FUNC void g(TCCState* S, int c); -ST_FUNC void gen_le16(TCCState* S, int c); -ST_FUNC void gen_le32(TCCState* S, int c); +ST_FUNC void g(int c); +ST_FUNC void gen_le16(int c); +ST_FUNC void gen_le32(int c); /*************************************************************/ #else @@ -20,85 +20,85 @@ ST_FUNC void gen_le32(TCCState* S, int c); #include "tcc.h" /* XXX: make it faster ? */ -ST_FUNC void g(TCCState* S, int c) +ST_FUNC void g(int c) { int ind1; - if (S->tccgen_nocode_wanted) + if (nocode_wanted) return; - ind1 = S->tccgen_ind + 1; + ind1 = ind + 1; if (ind1 > cur_text_section->data_allocated) - section_realloc(S, cur_text_section, ind1); - cur_text_section->data[S->tccgen_ind] = c; - S->tccgen_ind = ind1; + section_realloc(cur_text_section, ind1); + cur_text_section->data[ind] = c; + ind = ind1; } -ST_FUNC void gen_le16 (TCCState* S, int i) +ST_FUNC void gen_le16 (int i) { - g(S, i); - g(S, i>>8); + g(i); + g(i>>8); } -ST_FUNC void gen_le32 (TCCState* S, int i) +ST_FUNC void gen_le32 (int i) { int ind1; - if (S->tccgen_nocode_wanted) + if (nocode_wanted) return; - ind1 = S->tccgen_ind + 4; + ind1 = ind + 4; if (ind1 > cur_text_section->data_allocated) - section_realloc(S, cur_text_section, ind1); - cur_text_section->data[S->tccgen_ind++] = i & 0xFF; - cur_text_section->data[S->tccgen_ind++] = (i >> 8) & 0xFF; - cur_text_section->data[S->tccgen_ind++] = (i >> 16) & 0xFF; - cur_text_section->data[S->tccgen_ind++] = (i >> 24) & 0xFF; + section_realloc(cur_text_section, ind1); + cur_text_section->data[ind++] = i & 0xFF; + cur_text_section->data[ind++] = (i >> 8) & 0xFF; + cur_text_section->data[ind++] = (i >> 16) & 0xFF; + cur_text_section->data[ind++] = (i >> 24) & 0xFF; } -ST_FUNC void gen_expr32(TCCState* S, ExprValue *pe) +ST_FUNC void gen_expr32(ExprValue *pe) { - gen_le32(S, pe->v); + gen_le32(pe->v); } -static void asm_emit_opcode(TCCState* S, uint32_t opcode) { - gen_le32(S, opcode); +static void asm_emit_opcode(uint32_t opcode) { + gen_le32(opcode); } -static void asm_nullary_opcode(TCCState *S, int token) +static void asm_nullary_opcode(TCCState *s1, int token) { switch (token) { // Sync instructions case TOK_ASM_fence: // I - asm_emit_opcode(S, (0x3 << 2) | 3 | (0 << 12)); + asm_emit_opcode((0x3 << 2) | 3 | (0 << 12)); return; case TOK_ASM_fence_i: // I - asm_emit_opcode(S, (0x3 << 2) | 3| (1 << 12)); + asm_emit_opcode((0x3 << 2) | 3| (1 << 12)); return; // System calls case TOK_ASM_scall: // I (pseudo) - asm_emit_opcode(S, (0x1C << 2) | 3 | (0 << 12)); + asm_emit_opcode((0x1C << 2) | 3 | (0 << 12)); return; case TOK_ASM_sbreak: // I (pseudo) - asm_emit_opcode(S, (0x1C << 2) | 3 | (0 << 12) | (1 << 20)); + asm_emit_opcode((0x1C << 2) | 3 | (0 << 12) | (1 << 20)); return; // Privileged Instructions case TOK_ASM_ecall: - asm_emit_opcode(S, (0x1C << 2) | 3 | (0 << 20)); + asm_emit_opcode((0x1C << 2) | 3 | (0 << 20)); return; case TOK_ASM_ebreak: - asm_emit_opcode(S, (0x1C << 2) | 3 | (1 << 20)); + asm_emit_opcode((0x1C << 2) | 3 | (1 << 20)); return; // Other case TOK_ASM_wfi: - asm_emit_opcode(S, (0x1C << 2) | 3 | (0x105 << 20)); + asm_emit_opcode((0x1C << 2) | 3 | (0x105 << 20)); return; default: - expect(S, "nullary instruction"); + expect("nullary instruction"); } } @@ -121,30 +121,30 @@ typedef struct Operand { } Operand; /* Parse a text containing operand and store the result in OP */ -static void parse_operand(TCCState *S, Operand *op) +static void parse_operand(TCCState *s1, Operand *op) { ExprValue e; int8_t reg; op->type = 0; - if ((reg = asm_parse_regvar(S, S->tccpp_tok)) != -1) { - next(S); // skip register name + if ((reg = asm_parse_regvar(tok)) != -1) { + next(); // skip register name op->type = OP_REG; op->reg = (uint8_t) reg; return; - } else if (S->tccpp_tok == '$') { + } else if (tok == '$') { /* constant value */ - next(S); // skip '#' or '$' + next(); // skip '#' or '$' } - asm_expr(S, &e); + asm_expr(s1, &e); op->type = OP_IM32; op->e = e; if (!op->e.sym) { if ((int) op->e.v >= -2048 && (int) op->e.v < 2048) op->type = OP_IM12S; } else - expect(S, "operand"); + expect("operand"); } #define ENCODE_RS1(register_index) ((register_index) << 15) @@ -152,96 +152,96 @@ static void parse_operand(TCCState *S, Operand *op) #define ENCODE_RD(register_index) ((register_index) << 7) // Note: Those all map to CSR--so they are pseudo-instructions. -static void asm_unary_opcode(TCCState *S, int token) +static void asm_unary_opcode(TCCState *s1, int token) { uint32_t opcode = (0x1C << 2) | 3 | (2 << 12); Operand op; - parse_operand(S, &op); + parse_operand(s1, &op); if (op.type != OP_REG) { - expect(S, "register"); + expect("register"); return; } opcode |= ENCODE_RD(op.reg); switch (token) { case TOK_ASM_rdcycle: - asm_emit_opcode(S, opcode | (0xC00 << 20)); + asm_emit_opcode(opcode | (0xC00 << 20)); return; case TOK_ASM_rdcycleh: - asm_emit_opcode(S, opcode | (0xC80 << 20)); + asm_emit_opcode(opcode | (0xC80 << 20)); return; case TOK_ASM_rdtime: - asm_emit_opcode(S, opcode | (0xC01 << 20) | ENCODE_RD(op.reg)); + asm_emit_opcode(opcode | (0xC01 << 20) | ENCODE_RD(op.reg)); return; case TOK_ASM_rdtimeh: - asm_emit_opcode(S, opcode | (0xC81 << 20) | ENCODE_RD(op.reg)); + asm_emit_opcode(opcode | (0xC81 << 20) | ENCODE_RD(op.reg)); return; case TOK_ASM_rdinstret: - asm_emit_opcode(S, opcode | (0xC02 << 20) | ENCODE_RD(op.reg)); + asm_emit_opcode(opcode | (0xC02 << 20) | ENCODE_RD(op.reg)); return; case TOK_ASM_rdinstreth: - asm_emit_opcode(S, opcode | (0xC82 << 20) | ENCODE_RD(op.reg)); + asm_emit_opcode(opcode | (0xC82 << 20) | ENCODE_RD(op.reg)); return; default: - expect(S, "unary instruction"); + expect("unary instruction"); } } -static void asm_emit_u(TCCState *S, int token, uint32_t opcode, const Operand* rd, const Operand* rs2) +static void asm_emit_u(int token, uint32_t opcode, const Operand* rd, const Operand* rs2) { if (rd->type != OP_REG) { - tcc_error(S, "'%s': Expected destination operand that is a register", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL)); return; } if (rs2->type != OP_IM12S && rs2->type != OP_IM32) { - tcc_error(S, "'%s': Expected second source operand that is an immediate value", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token, NULL)); return; } else if (rs2->e.v >= 0x100000) { - tcc_error(S, "'%s': Expected second source operand that is an immediate value between 0 and 0xfffff", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0xfffff", get_tok_str(token, NULL)); return; } /* U-type instruction: 31...12 imm[31:12] 11...7 rd 6...0 opcode */ - gen_le32(S, opcode | ENCODE_RD(rd->reg) | (rs2->e.v << 12)); + gen_le32(opcode | ENCODE_RD(rd->reg) | (rs2->e.v << 12)); } -static void asm_binary_opcode(TCCState* S, int token) +static void asm_binary_opcode(TCCState* s1, int token) { Operand ops[2]; - parse_operand(S, &ops[0]); - if (S->tccpp_tok == ',') - next(S); + parse_operand(s1, &ops[0]); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[1]); + expect("','"); + parse_operand(s1, &ops[1]); switch (token) { case TOK_ASM_lui: - asm_emit_u(S, token, (0xD << 2) | 3, &ops[0], &ops[1]); + asm_emit_u(token, (0xD << 2) | 3, &ops[0], &ops[1]); return; case TOK_ASM_auipc: - asm_emit_u(S, token, (0x05 << 2) | 3, &ops[0], &ops[1]); + asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[1]); return; default: - expect(S, "binary instruction"); + expect("binary instruction"); } } /* caller: Add funct3, funct7 into opcode */ -static void asm_emit_r(TCCState* S, int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2) +static void asm_emit_r(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2) { if (rd->type != OP_REG) { - tcc_error(S, "'%s': Expected destination operand that is a register", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL)); return; } if (rs1->type != OP_REG) { - tcc_error(S, "'%s': Expected first source operand that is a register", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL)); return; } if (rs2->type != OP_REG) { - tcc_error(S, "'%s': Expected second source operand that is a register or immediate", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected second source operand that is a register or immediate", get_tok_str(token, NULL)); return; } /* R-type instruction: @@ -251,22 +251,22 @@ static void asm_emit_r(TCCState* S, int token, uint32_t opcode, const Operand* r 14...12 funct3 11...7 rd 6...0 opcode */ - gen_le32(S, opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg)); + gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg)); } /* caller: Add funct3 into opcode */ -static void asm_emit_i(TCCState* S, int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2) +static void asm_emit_i(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2) { if (rd->type != OP_REG) { - tcc_error(S, "'%s': Expected destination operand that is a register", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL)); return; } if (rs1->type != OP_REG) { - tcc_error(S, "'%s': Expected first source operand that is a register", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL)); return; } if (rs2->type != OP_IM12S) { - tcc_error(S, "'%s': Expected second source operand that is an immediate value between 0 and 4095", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 4095", get_tok_str(token, NULL)); return; } /* I-type instruction: @@ -276,156 +276,156 @@ static void asm_emit_i(TCCState* S, int token, uint32_t opcode, const Operand* r 11...7 rd 6...0 opcode */ - gen_le32(S, opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | (rs2->e.v << 20)); + gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | (rs2->e.v << 20)); } -static void asm_shift_opcode(TCCState *S, int token) +static void asm_shift_opcode(TCCState *s1, int token) { Operand ops[3]; - parse_operand(S, &ops[0]); - if (S->tccpp_tok == ',') - next(S); + parse_operand(s1, &ops[0]); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[1]); - if (S->tccpp_tok == ',') - next(S); + expect("','"); + parse_operand(s1, &ops[1]); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[2]); + expect("','"); + parse_operand(s1, &ops[2]); switch (token) { case TOK_ASM_sll: - asm_emit_r(S, token, (0xC << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_slli: - asm_emit_i(S, token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_srl: - asm_emit_r(S, token, (0xC << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_srli: - asm_emit_i(S, token, (0x4 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x4 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sra: - asm_emit_r(S, token, (0xC << 2) | 3 | (5 << 12) | (32 << 25), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (5 << 12) | (32 << 25), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_srai: - asm_emit_i(S, token, (0x4 << 2) | 3 | (5 << 12) | (16 << 26), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x4 << 2) | 3 | (5 << 12) | (16 << 26), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sllw: - asm_emit_r(S, token, (0xE << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xE << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_slliw: - asm_emit_i(S, token, (6 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (6 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_srlw: - asm_emit_r(S, token, (0xE << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xE << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_srliw: - asm_emit_i(S, token, (0x6 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x6 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sraw: - asm_emit_r(S, token, (0xE << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xE << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sraiw: - asm_emit_i(S, token, (0x6 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x6 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); return; default: - expect(S, "shift instruction"); + expect("shift instruction"); } } -static void asm_data_processing_opcode(TCCState* S, int token) +static void asm_data_processing_opcode(TCCState* s1, int token) { Operand ops[3]; - parse_operand(S, &ops[0]); - if (S->tccpp_tok == ',') - next(S); + parse_operand(s1, &ops[0]); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[1]); - if (S->tccpp_tok == ',') - next(S); + expect("','"); + parse_operand(s1, &ops[1]); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[2]); + expect("','"); + parse_operand(s1, &ops[2]); switch (token) { // Arithmetic (RD,RS1,(RS2|IMM)); R-format, I-format or U-format case TOK_ASM_add: - asm_emit_r(S, token, (0xC << 2) | 3, &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3, &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_addi: - asm_emit_i(S, token, (4 << 2) | 3, &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (4 << 2) | 3, &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sub: - asm_emit_r(S, token, (0xC << 2) | 3 | (32 << 25), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (32 << 25), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_addw: - asm_emit_r(S, token, (0xE << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xE << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_addiw: // 64 bit - asm_emit_i(S, token, (0x6 << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x6 << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_subw: - asm_emit_r(S, token, (0xE << 2) | 3 | (0 << 12) | (32 << 25), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xE << 2) | 3 | (0 << 12) | (32 << 25), &ops[0], &ops[1], &ops[2]); return; // Logical (RD,RS1,(RS2|IMM)); R-format or I-format case TOK_ASM_xor: - asm_emit_r(S, token, (0xC << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_xori: - asm_emit_i(S, token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_or: - asm_emit_r(S, token, (0xC << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_ori: - asm_emit_i(S, token, (0x4 << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x4 << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_and: - asm_emit_r(S, token, (0xC << 2) | 3 | (7 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (7 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_andi: - asm_emit_i(S, token, (0x4 << 2) | 3 | (7 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x4 << 2) | 3 | (7 << 12), &ops[0], &ops[1], &ops[2]); return; // Compare (RD,RS1,(RS2|IMM)); R-format or I-format case TOK_ASM_slt: - asm_emit_r(S, token, (0xC << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_slti: - asm_emit_i(S, token, (0x4 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x4 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sltu: - asm_emit_r(S, token, (0xC << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_r(token, (0xC << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sltiu: - asm_emit_i(S, token, (0x4 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x4 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]); return; default: - expect(S, "known data processing instruction"); + expect("known data processing instruction"); } } /* caller: Add funct3 to opcode */ -static void asm_emit_s(TCCState* S, int token, uint32_t opcode, const Operand* rs1, const Operand* rs2, const Operand* imm) +static void asm_emit_s(int token, uint32_t opcode, const Operand* rs1, const Operand* rs2, const Operand* imm) { if (rs1->type != OP_REG) { - tcc_error(S, "'%s': Expected first source operand that is a register", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL)); return; } if (rs2->type != OP_REG) { - tcc_error(S, "'%s': Expected second source operand that is a register", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token, NULL)); return; } if (imm->type != OP_IM12S) { - tcc_error(S, "'%s': Expected third operand that is an immediate value between 0 and 0xfff", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected third operand that is an immediate value between 0 and 0xfff", get_tok_str(token, NULL)); return; } { @@ -438,112 +438,112 @@ static void asm_emit_s(TCCState* S, int token, uint32_t opcode, const Operand* r 11...7 imm[4:0] 6...0 opcode opcode always fixed pos. */ - gen_le32(S, opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | ((v & 0x1F) << 7) | ((v >> 5) << 25)); + gen_le32(opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | ((v & 0x1F) << 7) | ((v >> 5) << 25)); } } -static void asm_data_transfer_opcode(TCCState* S, int token) +static void asm_data_transfer_opcode(TCCState* s1, int token) { Operand ops[3]; - parse_operand(S, &ops[0]); + parse_operand(s1, &ops[0]); if (ops[0].type != OP_REG) { - expect(S, "register"); + expect("register"); return; } - if (S->tccpp_tok == ',') - next(S); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[1]); + expect("','"); + parse_operand(s1, &ops[1]); if (ops[1].type != OP_REG) { - expect(S, "register"); + expect("register"); return; } - if (S->tccpp_tok == ',') - next(S); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[2]); + expect("','"); + parse_operand(s1, &ops[2]); switch (token) { // Loads (RD,RS1,I); I-format case TOK_ASM_lb: - asm_emit_i(S, token, (0x0 << 2) | 3, &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x0 << 2) | 3, &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_lh: - asm_emit_i(S, token, (0x0 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x0 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_lw: - asm_emit_i(S, token, (0x0 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x0 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_lbu: - asm_emit_i(S, token, (0x0 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x0 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_lhu: - asm_emit_i(S, token, (0x0 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x0 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]); return; // 64 bit case TOK_ASM_ld: - asm_emit_i(S, token, (0x0 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x0 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_lwu: - asm_emit_i(S, token, (0x0 << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_i(token, (0x0 << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]); return; // Stores (RS1,RS2,I); S-format case TOK_ASM_sb: - asm_emit_s(S, token, (0x8 << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_s(token, (0x8 << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sh: - asm_emit_s(S, token, (0x8 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_s(token, (0x8 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sw: - asm_emit_s(S, token, (0x8 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_s(token, (0x8 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]); return; case TOK_ASM_sd: - asm_emit_s(S, token, (0x8 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]); + asm_emit_s(token, (0x8 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]); return; default: - expect(S, "known data transfer instruction"); + expect("known data transfer instruction"); } } -static void asm_branch_opcode(TCCState* S, int token) +static void asm_branch_opcode(TCCState* s1, int token) { // Branch (RS1,RS2,IMM); SB-format uint32_t opcode = (0x18 << 2) | 3; uint32_t offset = 0; Operand ops[3]; - parse_operand(S, &ops[0]); + parse_operand(s1, &ops[0]); if (ops[0].type != OP_REG) { - expect(S, "register"); + expect("register"); return; } - if (S->tccpp_tok == ',') - next(S); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[1]); + expect("','"); + parse_operand(s1, &ops[1]); if (ops[1].type != OP_REG) { - expect(S, "register"); + expect("register"); return; } - if (S->tccpp_tok == ',') - next(S); + if (tok == ',') + next(); else - expect(S, "','"); - parse_operand(S, &ops[2]); + expect("','"); + parse_operand(s1, &ops[2]); if (ops[2].type != OP_IM12S) { - tcc_error(S, "'%s': Expected third operand that is an immediate value between 0 and 0xfff", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected third operand that is an immediate value between 0 and 0xfff", get_tok_str(token, NULL)); return; } offset = ops[2].e.v; if (offset & 1) { - tcc_error(S, "'%s': Expected third operand that is an even immediate value", get_tok_str(S, token, NULL)); + tcc_error("'%s': Expected third operand that is an even immediate value", get_tok_str(token, NULL)); return; } @@ -567,12 +567,12 @@ static void asm_branch_opcode(TCCState* S, int token) opcode |= 7 << 12; break; default: - expect(S, "known branch instruction"); + expect("known branch instruction"); } - asm_emit_opcode(S, opcode | ENCODE_RS1(ops[0].reg) | ENCODE_RS2(ops[1].reg) | (((offset >> 1) & 0xF) << 8) | (((offset >> 5) & 0x1f) << 25) | (((offset >> 11) & 1) << 7) | (((offset >> 12) & 1) << 31)); + asm_emit_opcode(opcode | ENCODE_RS1(ops[0].reg) | ENCODE_RS2(ops[1].reg) | (((offset >> 1) & 0xF) << 8) | (((offset >> 5) & 0x1f) << 25) | (((offset >> 11) & 1) << 7) | (((offset >> 12) & 1) << 31)); } -ST_FUNC void asm_opcode(TCCState *S, int token) +ST_FUNC void asm_opcode(TCCState *s1, int token) { switch (token) { case TOK_ASM_fence: @@ -585,7 +585,7 @@ ST_FUNC void asm_opcode(TCCState *S, int token) case TOK_ASM_mrth: case TOK_ASM_hrts: case TOK_ASM_wfi: - asm_nullary_opcode(S, token); + asm_nullary_opcode(s1, token); return; case TOK_ASM_rdcycle: @@ -594,12 +594,12 @@ ST_FUNC void asm_opcode(TCCState *S, int token) case TOK_ASM_rdtimeh: case TOK_ASM_rdinstret: case TOK_ASM_rdinstreth: - asm_unary_opcode(S, token); + asm_unary_opcode(s1, token); return; case TOK_ASM_lui: case TOK_ASM_auipc: - asm_binary_opcode(S, token); + asm_binary_opcode(s1, token); return; case TOK_ASM_sll: @@ -620,7 +620,7 @@ ST_FUNC void asm_opcode(TCCState *S, int token) case TOK_ASM_srad: case TOK_ASM_sraiw: case TOK_ASM_sraid: - asm_shift_opcode(S, token); + asm_shift_opcode(s1, token); return; case TOK_ASM_add: @@ -642,7 +642,7 @@ ST_FUNC void asm_opcode(TCCState *S, int token) case TOK_ASM_slti: case TOK_ASM_sltu: case TOK_ASM_sltiu: - asm_data_processing_opcode(S, token); + asm_data_processing_opcode(s1, token); case TOK_ASM_lb: case TOK_ASM_lh: @@ -655,7 +655,7 @@ ST_FUNC void asm_opcode(TCCState *S, int token) case TOK_ASM_sh: case TOK_ASM_sw: case TOK_ASM_sd: - asm_data_transfer_opcode(S, token); + asm_data_transfer_opcode(s1, token); return; case TOK_ASM_beq: @@ -664,35 +664,35 @@ ST_FUNC void asm_opcode(TCCState *S, int token) case TOK_ASM_bge: case TOK_ASM_bltu: case TOK_ASM_bgeu: - asm_branch_opcode(S, token); + asm_branch_opcode(s1, token); return; default: - expect(S, "known instruction"); + expect("known instruction"); } } -ST_FUNC void subst_asm_operand(TCCState *S, CString *add_str, SValue *sv, int modifier) +ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier) { - tcc_error(S, "RISCV64 asm not implemented."); + tcc_error("RISCV64 asm not implemented."); } /* generate prolog and epilog code for asm statement */ -ST_FUNC void asm_gen_code(TCCState *S, ASMOperand *operands, int nb_operands, +ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands, int nb_outputs, int is_output, uint8_t *clobber_regs, int out_reg) { } -ST_FUNC void asm_compute_constraints(TCCState *S, ASMOperand *operands, +ST_FUNC void asm_compute_constraints(ASMOperand *operands, int nb_operands, int nb_outputs, const uint8_t *clobber_regs, int *pout_reg) { } -ST_FUNC void asm_clobber(TCCState *S, uint8_t *clobber_regs, const char *str) +ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str) { int reg; TokenSym *ts; @@ -701,15 +701,15 @@ ST_FUNC void asm_clobber(TCCState *S, uint8_t *clobber_regs, const char *str) !strcmp(str, "cc") || !strcmp(str, "flags")) return; - ts = tok_alloc(S, str, strlen(str)); - reg = asm_parse_regvar(S, ts->tok); + ts = tok_alloc(str, strlen(str)); + reg = asm_parse_regvar(ts->tok); if (reg == -1) { - tcc_error(S, "invalid clobber register '%s'", str); + tcc_error("invalid clobber register '%s'", str); } clobber_regs[reg] = 1; } -ST_FUNC int asm_parse_regvar (TCCState* S, int t) +ST_FUNC int asm_parse_regvar (int t) { if (t >= TOK_ASM_x0 && t <= TOK_ASM_pc) { /* register name */ switch (t) { |