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| author | noneofyourbusiness <noneofyourbusiness@danwin1210.de> | 2023-12-10 15:22:41 +0100 |
|---|---|---|
| committer | noneofyourbusiness <noneofyourbusiness@danwin1210.de> | 2023-12-10 15:22:41 +0100 |
| commit | 5dc241fee11691fc168477261a92e99b7c0b7873 (patch) | |
| tree | 2c5ac8cc25862e0d2da69bde37ff7051c6efa2bd | |
| parent | 3b3c9412acb25bbdd7cefd61e7f628e99a0f7ada (diff) | |
riscv64-tok.h: add Zicsr pseudoinstructions, registers
| -rw-r--r-- | riscv64-tok.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/riscv64-tok.h b/riscv64-tok.h index c8a6e8e..92369d9 100644 --- a/riscv64-tok.h +++ b/riscv64-tok.h @@ -340,6 +340,29 @@ DEF_ASM(csrrwi) DEF_ASM(csrrsi) DEF_ASM(csrrci) + /* registers */ + DEF_ASM(cycle) + DEF_ASM(fcsr) + DEF_ASM(fflags) + DEF_ASM(frm) + DEF_ASM(instret) + DEF_ASM(time) + /* RV32I-only */ + DEF_ASM(cycleh) + DEF_ASM(instreth) + DEF_ASM(timeh) + /* pseudo */ + DEF_ASM(csrc) + DEF_ASM(csrci) + DEF_ASM(csrr) + DEF_ASM(csrs) + DEF_ASM(csrsi) + DEF_ASM(csrw) + DEF_ASM(csrwi) + DEF_ASM(frcsr) + DEF_ASM(frrm) + DEF_ASM(fscsr) + DEF_ASM(fsrm) /* Privileged Instructions */ |