diff options
| author | russellcnv <russellc@nvidia.com> | 2024-01-31 14:02:06 -0800 |
|---|---|---|
| committer | russellcnv <russellc@nvidia.com> | 2024-01-31 14:02:06 -0800 |
| commit | e558660fc28cb7574cf1815e4bd3ec84e15c7226 (patch) | |
| tree | a9d5983ee7ed8ea09ee4624e03c353f641fb18b7 | |
| parent | 2a3b58b8c8966a0581d46cc5b48e5c44c46b5c4a (diff) | |
535.43.24535.43.24
267 files changed, 88989 insertions, 82768 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index 67b530df4..ff49b2cbd 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ ## Release 535 Entries -### [535.54.03] 2023-06-14 +### [535.43.24] 2024-01-31 ### [535.43.23] 2024-01-24 @@ -30,6 +30,7 @@ #### Fixed +- Fixed building main against current centos stream 8 fails, [#550](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/550) by @airlied - Fixed console restore with traditional VGA consoles. #### Added @@ -58,6 +59,14 @@ ## Release 525 Entries +### [525.147.05] 2023-10-31 + +#### Fixed + +- Fix nvidia_p2p_get_pages(): Fix double-free in register-callback error path, [#557](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/557) by @BrendanCunningham + +### [525.125.06] 2023-06-26 + ### [525.116.04] 2023-05-09 ### [525.116.03] 2023-04-25 @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 535.43.23. +version 535.43.24. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -535.43.23 driver release. This can be achieved by installing +535.43.24 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -180,7 +180,7 @@ software applications. ## Compatible GPUs The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 535.43.23 release, +(see the table below). However, in the 535.43.24 release, GeForce and Workstation support is still considered alpha-quality. To enable use of the open kernel modules on GeForce and Workstation GPUs, @@ -188,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module parameter to 1. For more details, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/535.43.23/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/535.43.24/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index f5fd300c0..5bace389a 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.43.23\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.43.24\" ifneq ($(SYSSRCHOST1X),) EXTRA_CFLAGS += -I$(SYSSRCHOST1X) @@ -123,6 +123,9 @@ ifneq ($(wildcard /proc/sgi_uv),) EXTRA_CFLAGS += -DNV_CONFIG_X86_UV endif +ifdef VGX_FORCE_VFIO_PCI_CORE + EXTRA_CFLAGS += -DNV_VGPU_FORCE_VFIO_PCI_CORE +endif # # The conftest.sh script tests various aspects of the target kernel. diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h index fd6f99d16..2349ceb91 100644 --- a/kernel-open/common/inc/nv-linux.h +++ b/kernel-open/common/inc/nv-linux.h @@ -2067,4 +2067,7 @@ typedef enum #include <linux/clk-provider.h> #endif +#define NV_EXPORT_SYMBOL(symbol) EXPORT_SYMBOL_GPL(symbol) +#define NV_CHECK_EXPORT_SYMBOL(symbol) NV_IS_EXPORT_SYMBOL_PRESENT_##symbol + #endif /* _NV_LINUX_H_ */ diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index 44a1515e3..fc7764165 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -924,6 +924,7 @@ NV_STATUS NV_API_CALL rm_ioctl (nvidia_stack_t *, nv_state_t * NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *); void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t); NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *); diff --git a/kernel-open/common/inc/os-interface.h b/kernel-open/common/inc/os-interface.h index 52699ac19..5249e124e 100644 --- a/kernel-open/common/inc/os-interface.h +++ b/kernel-open/common/inc/os-interface.h @@ -207,9 +207,13 @@ enum os_pci_req_atomics_type { OS_INTF_PCIE_REQ_ATOMICS_128BIT }; NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); +NV_STATUS NV_API_CALL os_get_numa_node_memory_usage (NvS32, NvU64 *, NvU64 *); NV_STATUS NV_API_CALL os_numa_add_gpu_memory (void *, NvU64, NvU64, NvU32 *); NV_STATUS NV_API_CALL os_numa_remove_gpu_memory (void *, NvU64, NvU64, NvU32); NV_STATUS NV_API_CALL os_offline_page_at_address(NvU64 address); +void* NV_API_CALL os_get_pid_info(void); +void NV_API_CALL os_put_pid_info(void *pid_info); +NV_STATUS NV_API_CALL os_find_ns_pid(void *pid_info, NvU32 *ns_pid); extern NvU32 os_page_size; extern NvU64 os_page_mask; diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index 4e3e7593a..a642269c4 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -316,7 +316,7 @@ export_symbol_present_conftest() { SYMBOL="$1" TAB=' ' - if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL.*\$" \ + if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL\(_GPL\)\?\s*\$" \ "$OUTPUT/Module.symvers" >/dev/null 2>&1; then echo "#define NV_IS_EXPORT_SYMBOL_PRESENT_$SYMBOL 1" | append_conftest "symbols" @@ -337,7 +337,7 @@ export_symbol_gpl_conftest() { SYMBOL="$1" TAB=' ' - if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_\(UNUSED_\)*SYMBOL_GPL\$" \ + if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_\(UNUSED_\)*SYMBOL_GPL\s*\$" \ "$OUTPUT/Module.symvers" >/dev/null 2>&1; then echo "#define NV_IS_EXPORT_SYMBOL_GPL_$SYMBOL 1" | append_conftest "symbols" @@ -4468,6 +4468,24 @@ compile_test() { compile_check_conftest "$CODE" "NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE" "" "types" ;; + mmu_notifier_ops_arch_invalidate_secondary_tlbs) + # + # Determine if the mmu_notifier_ops struct has the + # 'arch_invalidate_secondary_tlbs' member. + # + # struct mmu_notifier_ops.invalidate_range was renamed to + # arch_invalidate_secondary_tlbs by commit 1af5a8109904 + # ("mmu_notifiers: rename invalidate_range notifier") due to be + # added in v6.6 + CODE=" + #include <linux/mmu_notifier.h> + int conftest_mmu_notifier_ops_arch_invalidate_secondary_tlbs(void) { + return offsetof(struct mmu_notifier_ops, arch_invalidate_secondary_tlbs); + }" + + compile_check_conftest "$CODE" "NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS" "" "types" + ;; + drm_format_num_planes) # # Determine if drm_format_num_planes() function is present. @@ -5636,23 +5654,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_GPIO_TO_IRQ_PRESENT" "" "functions" ;; - migrate_vma_setup) - # - # Determine if migrate_vma_setup() function is present - # - # migrate_vma_setup() function was added by commit - # a7d1f22bb74f32cf3cd93f52776007e161f1a738 ("mm: turn migrate_vma - # upside down) in v5.4. - # (2019-08-20). - CODE=" - #include <linux/migrate.h> - int conftest_migrate_vma_setup(void) { - migrate_vma_setup(); - }" - - compile_check_conftest "$CODE" "NV_MIGRATE_VMA_SETUP_PRESENT" "" "functions" - ;; - migrate_vma_added_flags) # # Determine if migrate_vma structure has flags @@ -5743,23 +5744,25 @@ compile_test() { compile_check_conftest "$CODE" "NV_IOASID_GET_PRESENT" "" "functions" ;; - mm_pasid_set) + mm_pasid_drop) + # + # Determine if mm_pasid_drop() function is present # - # Determine if mm_pasid_set() function is present + # Added by commit 701fac40384f ("iommu/sva: Assign a PASID to mm + # on PASID allocation and free it on mm exit") in v5.18. + # Moved to linux/iommu.h in commit cd3891158a77 ("iommu/sva: Move + # PASID helpers to sva code") in v6.4. # - # mm_pasid_set() function was added by commit - # 701fac40384f07197b106136012804c3cae0b3de (iommu/sva: Assign a - # PASID to mm on PASID allocation and free it on mm exit) in v5.18. - # (2022-02-15). CODE=" #if defined(NV_LINUX_SCHED_MM_H_PRESENT) #include <linux/sched/mm.h> #endif - void conftest_mm_pasid_set(void) { - mm_pasid_set(); + #include <linux/iommu.h> + void conftest_mm_pasid_drop(void) { + mm_pasid_drop(); }" - compile_check_conftest "$CODE" "NV_MM_PASID_SET_PRESENT" "" "functions" + compile_check_conftest "$CODE" "NV_MM_PASID_DROP_PRESENT" "" "functions" ;; drm_crtc_state_has_no_vblank) @@ -6279,6 +6282,21 @@ compile_test() { compile_check_conftest "$CODE" "NV_MEMORY_FAILURE_MF_SW_SIMULATED_DEFINED" "" "types" ;; + crypto_tfm_ctx_aligned) + # Determine if 'crypto_tfm_ctx_aligned' is defined. + # + # Removed by commit 25c74a39e0f6 ("crypto: hmac - remove unnecessary + # alignment logic") in v6.7. + # + CODE=" + #include <crypto/algapi.h> + void conftest_crypto_tfm_ctx_aligned(void) { + (void)crypto_tfm_ctx_aligned(); + }" + + compile_check_conftest "$CODE" "NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT" "" "functions" + ;; + crypto) # # Determine if we support various crypto functions. @@ -6341,6 +6359,22 @@ compile_test() { compile_check_conftest "$CODE" "NV_MEMPOLICY_HAS_HOME_NODE" "" "types" ;; + mpol_preferred_many_present) + # + # Determine if MPOL_PREFERRED_MANY enum is present or not + # + # Added by commit b27abaccf8e8b ("mm/mempolicy: add + # MPOL_PREFERRED_MANY for multiple preferred nodes") in + # v5.15 + # + CODE=" + #include <linux/mempolicy.h> + int mpol_preferred_many = MPOL_PREFERRED_MANY; + " + + compile_check_conftest "$CODE" "NV_MPOL_PREFERRED_MANY_PRESENT" "" "types" + ;; + mmu_interval_notifier) # # Determine if mmu_interval_notifier struct is present or not @@ -6356,6 +6390,21 @@ compile_test() { compile_check_conftest "$CODE" "NV_MMU_INTERVAL_NOTIFIER" "" "types" ;; + drm_unlocked_ioctl_flag_present) + # Determine if DRM_UNLOCKED IOCTL flag is present. + # + # DRM_UNLOCKED was removed by commit 2798ffcc1d6a ("drm: Remove + # locking for legacy ioctls and DRM_UNLOCKED") in Linux + # next-20231208. + CODE=" + #if defined(NV_DRM_DRM_IOCTL_H_PRESENT) + #include <drm/drm_ioctl.h> + #endif + int flags = DRM_UNLOCKED;" + + compile_check_conftest "$CODE" "NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. # @@ -6680,18 +6729,9 @@ case "$5" in VFIO_PCI_CORE_PRESENT=1 fi - # When this sanity check is run via nvidia-installer, it sets ARCH as aarch64. - # But, when it is run via Kbuild, ARCH is set as arm64 - if [ "$ARCH" = "aarch64" ]; then - ARCH="arm64" - fi - if [ "$VFIO_IOMMU_PRESENT" != "0" ] && [ "$KVM_PRESENT" != "0" ] ; then - - # On x86_64, vGPU requires MDEV framework to be present. - # On aarch64, vGPU requires MDEV or vfio-pci-core framework to be present. - if ([ "$ARCH" = "arm64" ] && ([ "$VFIO_MDEV_PRESENT" != "0" ] || [ "$VFIO_PCI_CORE_PRESENT" != "0" ])) || - ([ "$ARCH" = "x86_64" ] && [ "$VFIO_MDEV_PRESENT" != "0" ];) then + # vGPU requires either MDEV or vfio-pci-core framework to be present. + if [ "$VFIO_MDEV_PRESENT" != "0" ] || [ "$VFIO_PCI_CORE_PRESENT" != "0" ]; then exit 0 fi fi @@ -6702,14 +6742,10 @@ case "$5" in echo "CONFIG_VFIO_IOMMU_TYPE1"; fi - if [ "$ARCH" = "arm64" ] && [ "$VFIO_MDEV_PRESENT" = "0" ] && [ "$VFIO_PCI_CORE_PRESENT" = "0" ]; then + if [ "$VFIO_MDEV_PRESENT" = "0" ] && [ "$VFIO_PCI_CORE_PRESENT" = "0" ]; then echo "either CONFIG_VFIO_MDEV or CONFIG_VFIO_PCI_CORE"; fi - if [ "$ARCH" = "x86_64" ] && [ "$VFIO_MDEV_PRESENT" = "0" ]; then - echo "CONFIG_VFIO_MDEV"; - fi - if [ "$KVM_PRESENT" = "0" ]; then echo "CONFIG_KVM"; fi diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index 6c68d8242..62d557e7a 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -1312,9 +1312,21 @@ static const struct drm_ioctl_desc nv_drm_ioctls[] = { DRM_RENDER_ALLOW|DRM_UNLOCKED), #endif + /* + * DRM_UNLOCKED is implicit for all non-legacy DRM driver IOCTLs since Linux + * v4.10 commit fa5386459f06 "drm: Used DRM_LEGACY for all legacy functions" + * (Linux v4.4 commit ea487835e887 "drm: Enforce unlocked ioctl operation + * for kms driver ioctls" previously did it only for drivers that set the + * DRM_MODESET flag), so this will race with SET_CLIENT_CAP. Linux v4.11 + * commit dcf727ab5d17 "drm: setclientcap doesn't need the drm BKL" also + * removed locking from SET_CLIENT_CAP so there is no use attempting to lock + * manually. The latter commit acknowledges that this can expose userspace + * to inconsistent behavior when racing with itself, but accepts that risk. + */ DRM_IOCTL_DEF_DRV(NVIDIA_GET_CLIENT_CAPABILITY, nv_drm_get_client_capability_ioctl, 0), + #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) DRM_IOCTL_DEF_DRV(NVIDIA_GET_CRTC_CRC32, nv_drm_get_crtc_crc32_ioctl, diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c index 5d04713ce..c76045c4b 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c @@ -243,6 +243,15 @@ static int __nv_drm_nvkms_gem_obj_init( NvU64 *pages = NULL; NvU32 numPages = 0; + if ((size % PAGE_SIZE) != 0) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "NvKmsKapiMemory 0x%p size should be in a multiple of page size to " + "create a gem object", + pMemory); + return -EINVAL; + } + nv_nvkms_memory->pPhysicalAddress = NULL; nv_nvkms_memory->pWriteCombinedIORemapAddress = NULL; nv_nvkms_memory->physically_mapped = false; diff --git a/kernel-open/nvidia-drm/nvidia-drm-helper.h b/kernel-open/nvidia-drm/nvidia-drm-helper.h index 85a5d2e9c..c74ebbb10 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-helper.h +++ b/kernel-open/nvidia-drm/nvidia-drm-helper.h @@ -583,6 +583,19 @@ static inline int nv_drm_format_num_planes(uint32_t format) #endif /* defined(NV_DRM_FORMAT_MODIFIERS_PRESENT) */ /* + * DRM_UNLOCKED was removed with linux-next commit 2798ffcc1d6a ("drm: Remove + * locking for legacy ioctls and DRM_UNLOCKED"), but it was previously made + * implicit for all non-legacy DRM driver IOCTLs since Linux v4.10 commit + * fa5386459f06 "drm: Used DRM_LEGACY for all legacy functions" (Linux v4.4 + * commit ea487835e887 "drm: Enforce unlocked ioctl operation for kms driver + * ioctls" previously did it only for drivers that set the DRM_MODESET flag), so + * it was effectively a no-op anyway. + */ +#if !defined(NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT) +#define DRM_UNLOCKED 0 +#endif + +/* * drm_vma_offset_exact_lookup_locked() were added * by kernel commit 2225cfe46bcc which was Signed-off-by: * Daniel Vetter <daniel.vetter@intel.com> diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index a4ea2d479..9b30f1260 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -133,3 +133,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index d4d1d2683..11c235994 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -68,6 +68,9 @@ module_param_named(output_rounding_fix, output_rounding_fix, bool, 0400); static bool disable_vrr_memclk_switch = false; module_param_named(disable_vrr_memclk_switch, disable_vrr_memclk_switch, bool, 0400); +static bool opportunistic_display_sync = true; +module_param_named(opportunistic_display_sync, opportunistic_display_sync, bool, 0400); + /* These parameters are used for fault injection tests. Normally the defaults * should be used. */ MODULE_PARM_DESC(fail_malloc, "Fail the Nth call to nvkms_alloc"); @@ -99,6 +102,11 @@ NvBool nvkms_disable_vrr_memclk_switch(void) return disable_vrr_memclk_switch; } +NvBool nvkms_opportunistic_display_sync(void) +{ + return opportunistic_display_sync; +} + #define NVKMS_SYNCPT_STUBS_NEEDED /************************************************************************* @@ -200,9 +208,23 @@ static inline int nvkms_read_trylock_pm_lock(void) static inline void nvkms_read_lock_pm_lock(void) { - while (!down_read_trylock(&nvkms_pm_lock)) { - try_to_freeze(); - cond_resched(); + if ((current->flags & PF_NOFREEZE)) { + /* + * Non-freezable tasks (i.e. kthreads in this case) don't have to worry + * about being frozen during system suspend, but do need to block so + * that the CPU can go idle during s2idle. Do a normal uninterruptible + * blocking wait for the PM lock. + */ + down_read(&nvkms_pm_lock); + } else { + /* + * For freezable tasks, make sure we give the kernel an opportunity to + * freeze if taking the PM lock fails. + */ + while (!down_read_trylock(&nvkms_pm_lock)) { + try_to_freeze(); + cond_resched(); + } } } diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h index 16b89c1ca..44ff02d80 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h +++ b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h @@ -99,6 +99,7 @@ typedef struct { NvBool nvkms_output_rounding_fix(void); NvBool nvkms_disable_vrr_memclk_switch(void); +NvBool nvkms_opportunistic_display_sync(void); void nvkms_call_rm (void *ops); void* nvkms_alloc (size_t size, diff --git a/kernel-open/nvidia-peermem/nvidia-peermem.c b/kernel-open/nvidia-peermem/nvidia-peermem.c index a20f7d1dd..9636f4dba 100644 --- a/kernel-open/nvidia-peermem/nvidia-peermem.c +++ b/kernel-open/nvidia-peermem/nvidia-peermem.c @@ -1,20 +1,25 @@ -/* SPDX-License-Identifier: Linux-OpenIB */ /* * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF @@ -43,7 +48,9 @@ MODULE_AUTHOR("Yishai Hadas"); MODULE_DESCRIPTION("NVIDIA GPU memory plug-in"); -MODULE_LICENSE("Linux-OpenIB"); + +MODULE_LICENSE("Dual BSD/GPL"); + MODULE_VERSION(DRV_VERSION); enum { NV_MEM_PEERDIRECT_SUPPORT_DEFAULT = 0, @@ -53,7 +60,13 @@ static int peerdirect_support = NV_MEM_PEERDIRECT_SUPPORT_DEFAULT; module_param(peerdirect_support, int, S_IRUGO); MODULE_PARM_DESC(peerdirect_support, "Set level of support for Peer-direct, 0 [default] or 1 [legacy, for example MLNX_OFED 4.9 LTS]"); -#define peer_err(FMT, ARGS...) printk(KERN_ERR "nvidia-peermem" " %s:%d " FMT, __FUNCTION__, __LINE__, ## ARGS) + +#define peer_err(FMT, ARGS...) printk(KERN_ERR "nvidia-peermem" " %s:%d ERROR " FMT, __FUNCTION__, __LINE__, ## ARGS) +#ifdef NV_MEM_DEBUG +#define peer_trace(FMT, ARGS...) printk(KERN_DEBUG "nvidia-peermem" " %s:%d TRACE " FMT, __FUNCTION__, __LINE__, ## ARGS) +#else +#define peer_trace(FMT, ARGS...) do {} while (0) +#endif #if defined(NV_MLNX_IB_PEER_MEM_SYMBOLS_PRESENT) @@ -74,7 +87,10 @@ invalidate_peer_memory mem_invalidate_callback; static void *reg_handle = NULL; static void *reg_handle_nc = NULL; +#define NV_MEM_CONTEXT_MAGIC ((u64)0xF1F4F1D0FEF0DAD0ULL) + struct nv_mem_context { + u64 pad1; struct nvidia_p2p_page_table *page_table; struct nvidia_p2p_dma_mapping *dma_mapping; u64 core_context; @@ -86,8 +102,22 @@ struct nv_mem_context { struct task_struct *callback_task; int sg_allocated; struct sg_table sg_head; + u64 pad2; }; +#define NV_MEM_CONTEXT_CHECK_OK(MC) ({ \ + struct nv_mem_context *mc = (MC); \ + int rc = ((0 != mc) && \ + (READ_ONCE(mc->pad1) == NV_MEM_CONTEXT_MAGIC) && \ + (READ_ONCE(mc->pad2) == NV_MEM_CONTEXT_MAGIC)); \ + if (!rc) { \ + peer_trace("invalid nv_mem_context=%px pad1=%016llx pad2=%016llx\n", \ + mc, \ + mc?mc->pad1:0, \ + mc?mc->pad2:0); \ + } \ + rc; \ +}) static void nv_get_p2p_free_callback(void *data) { @@ -97,8 +127,9 @@ static void nv_get_p2p_free_callback(void *data) struct nvidia_p2p_dma_mapping *dma_mapping = NULL; __module_get(THIS_MODULE); - if (!nv_mem_context) { - peer_err("nv_get_p2p_free_callback -- invalid nv_mem_context\n"); + + if (!NV_MEM_CONTEXT_CHECK_OK(nv_mem_context)) { + peer_err("detected invalid context, skipping further processing\n"); goto out; } @@ -169,9 +200,11 @@ static int nv_mem_acquire(unsigned long addr, size_t size, void *peer_mem_privat /* Error case handled as not mine */ return 0; + nv_mem_context->pad1 = NV_MEM_CONTEXT_MAGIC; nv_mem_context->page_virt_start = addr & GPU_PAGE_MASK; nv_mem_context->page_virt_end = (addr + size + GPU_PAGE_SIZE - 1) & GPU_PAGE_MASK; nv_mem_context->mapped_size = nv_mem_context->page_virt_end - nv_mem_context->page_virt_start; + nv_mem_context->pad2 = NV_MEM_CONTEXT_MAGIC; ret = nvidia_p2p_get_pages(0, 0, nv_mem_context->page_virt_start, nv_mem_context->mapped_size, &nv_mem_context->page_table, nv_mem_dummy_callback, nv_mem_context); @@ -195,6 +228,7 @@ static int nv_mem_acquire(unsigned long addr, size_t size, void *peer_mem_privat return 1; err: + memset(nv_mem_context, 0, sizeof(*nv_mem_context)); kfree(nv_mem_context); /* Error case handled as not mine */ @@ -342,6 +376,7 @@ static void nv_mem_release(void *context) sg_free_table(&nv_mem_context->sg_head); nv_mem_context->sg_allocated = 0; } + memset(nv_mem_context, 0, sizeof(*nv_mem_context)); kfree(nv_mem_context); module_put(THIS_MODULE); return; diff --git a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild index 73083929a..a38de2166 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild @@ -81,8 +81,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_memory_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get -NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_set -NV_CONFTEST_FUNCTION_COMPILE_TESTS += migrate_vma_setup +NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_drop NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmgrab NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_sva_bind_device_has_drvdata_arg @@ -100,6 +99,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += kmem_cache_has_kobj_remove_work NV_CONFTEST_TYPE_COMPILE_TESTS += sysfs_slab_unlink NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_invalidate_range +NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_arch_invalidate_secondary_tlbs NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops NV_CONFTEST_TYPE_COMPILE_TESTS += timespec64 NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock @@ -110,6 +110,8 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += handle_mm_fault_has_mm_arg NV_CONFTEST_TYPE_COMPILE_TESTS += handle_mm_fault_has_pt_regs_arg NV_CONFTEST_TYPE_COMPILE_TESTS += mempolicy_has_unified_nodes NV_CONFTEST_TYPE_COMPILE_TESTS += mempolicy_has_home_node +NV_CONFTEST_TYPE_COMPILE_TESTS += mpol_preferred_many_present NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_interval_notifier NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup diff --git a/kernel-open/nvidia-uvm/uvm.c b/kernel-open/nvidia-uvm/uvm.c index a74ad154b..6f95f17cb 100644 --- a/kernel-open/nvidia-uvm/uvm.c +++ b/kernel-open/nvidia-uvm/uvm.c @@ -571,7 +571,6 @@ static void uvm_vm_open_managed_entry(struct vm_area_struct *vma) static void uvm_vm_close_managed(struct vm_area_struct *vma) { uvm_va_space_t *va_space = uvm_va_space_get(vma->vm_file); - uvm_processor_id_t gpu_id; bool make_zombie = false; if (current->mm != NULL) @@ -606,12 +605,6 @@ static void uvm_vm_close_managed(struct vm_area_struct *vma) uvm_destroy_vma_managed(vma, make_zombie); - // Notify GPU address spaces that the fault buffer needs to be flushed to - // avoid finding stale entries that can be attributed to new VA ranges - // reallocated at the same address. - for_each_gpu_id_in_mask(gpu_id, &va_space->registered_gpu_va_spaces) { - uvm_processor_mask_set_atomic(&va_space->needs_fault_buffer_flush, gpu_id); - } uvm_va_space_up_write(va_space); if (current->mm != NULL) diff --git a/kernel-open/nvidia-uvm/uvm_ada.c b/kernel-open/nvidia-uvm/uvm_ada.c index 8852c44ab..2de1eee0e 100644 --- a/kernel-open/nvidia-uvm/uvm_ada.c +++ b/kernel-open/nvidia-uvm/uvm_ada.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -94,4 +94,6 @@ void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_ampere.c b/kernel-open/nvidia-uvm/uvm_ampere.c index d4af699e4..0f95c8fb2 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere.c +++ b/kernel-open/nvidia-uvm/uvm_ampere.c @@ -101,4 +101,6 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_ats_faults.c b/kernel-open/nvidia-uvm/uvm_ats_faults.c index dc8a439b3..2da387e7a 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_faults.c +++ b/kernel-open/nvidia-uvm/uvm_ats_faults.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018 NVIDIA Corporation + Copyright (c) 2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -107,10 +107,10 @@ static NV_STATUS service_ats_faults(uvm_gpu_va_space_t *gpu_va_space, return status; } -static void flush_tlb_write_faults(uvm_gpu_va_space_t *gpu_va_space, - NvU64 addr, - size_t size, - uvm_fault_client_type_t client_type) +static void flush_tlb_va_region(uvm_gpu_va_space_t *gpu_va_space, + NvU64 addr, + size_t size, + uvm_fault_client_type_t client_type) { uvm_ats_fault_invalidate_t *ats_invalidate; @@ -119,12 +119,12 @@ static void flush_tlb_write_faults(uvm_gpu_va_space_t *gpu_va_space, else ats_invalidate = &gpu_va_space->gpu->parent->fault_buffer_info.non_replayable.ats_invalidate; - if (!ats_invalidate->write_faults_in_batch) { - uvm_tlb_batch_begin(&gpu_va_space->page_tables, &ats_invalidate->write_faults_tlb_batch); - ats_invalidate->write_faults_in_batch = true; + if (!ats_invalidate->tlb_batch_pending) { + uvm_tlb_batch_begin(&gpu_va_space->page_tables, &ats_invalidate->tlb_batch); + ats_invalidate->tlb_batch_pending = true; } - uvm_tlb_batch_invalidate(&ats_invalidate->write_faults_tlb_batch, addr, size, PAGE_SIZE, UVM_MEMBAR_NONE); + uvm_tlb_batch_invalidate(&ats_invalidate->tlb_batch, addr, size, PAGE_SIZE, UVM_MEMBAR_NONE); } static void ats_batch_select_residency(uvm_gpu_va_space_t *gpu_va_space, @@ -149,7 +149,11 @@ static void ats_batch_select_residency(uvm_gpu_va_space_t *gpu_va_space, mode = vma_policy->mode; - if ((mode == MPOL_BIND) || (mode == MPOL_PREFERRED_MANY) || (mode == MPOL_PREFERRED)) { + if ((mode == MPOL_BIND) +#if defined(NV_MPOL_PREFERRED_MANY_PRESENT) + || (mode == MPOL_PREFERRED_MANY) +#endif + || (mode == MPOL_PREFERRED)) { int home_node = NUMA_NO_NODE; #if defined(NV_MEMPOLICY_HAS_HOME_NODE) @@ -467,6 +471,10 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, uvm_page_mask_and(write_fault_mask, write_fault_mask, read_fault_mask); else uvm_page_mask_zero(write_fault_mask); + + // There are no pending faults beyond write faults to RO region. + if (uvm_page_mask_empty(read_fault_mask)) + return status; } ats_batch_select_residency(gpu_va_space, vma, ats_context); @@ -489,6 +497,7 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, if (vma->vm_flags & VM_WRITE) { uvm_page_mask_region_fill(faults_serviced_mask, subregion); + uvm_ats_smmu_invalidate_tlbs(gpu_va_space, start, length); // The Linux kernel never invalidates TLB entries on mapping // permission upgrade. This is a problem if the GPU has cached @@ -499,7 +508,7 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, // infinite loop because we just forward the fault to the Linux // kernel and it will see that the permissions in the page table are // correct. Therefore, we flush TLB entries on ATS write faults. - flush_tlb_write_faults(gpu_va_space, start, length, client_type); + flush_tlb_va_region(gpu_va_space, start, length, client_type); } else { uvm_page_mask_region_fill(reads_serviced_mask, subregion); @@ -522,6 +531,15 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, return status; uvm_page_mask_region_fill(faults_serviced_mask, subregion); + + // Similarly to permission upgrade scenario, discussed above, GPU + // will not re-fetch the entry if the PTE is invalid and page size + // is 4K. To avoid infinite faulting loop, invalidate TLB for every + // new translation written explicitly like in the case of permission + // upgrade. + if (PAGE_SIZE == UVM_PAGE_SIZE_4K) + flush_tlb_va_region(gpu_va_space, start, length, client_type); + } return status; @@ -556,7 +574,7 @@ NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NV_STATUS status; uvm_push_t push; - if (!ats_invalidate->write_faults_in_batch) + if (!ats_invalidate->tlb_batch_pending) return NV_OK; UVM_ASSERT(gpu_va_space); @@ -568,7 +586,7 @@ NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, "Invalidate ATS entries"); if (status == NV_OK) { - uvm_tlb_batch_end(&ats_invalidate->write_faults_tlb_batch, &push, UVM_MEMBAR_NONE); + uvm_tlb_batch_end(&ats_invalidate->tlb_batch, &push, UVM_MEMBAR_NONE); uvm_push_end(&push); // Add this push to the GPU's tracker so that fault replays/clears can @@ -576,8 +594,7 @@ NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, status = uvm_tracker_add_push_safe(out_tracker, &push); } - ats_invalidate->write_faults_in_batch = false; + ats_invalidate->tlb_batch_pending = false; return status; } - diff --git a/kernel-open/nvidia-uvm/uvm_ats_faults.h b/kernel-open/nvidia-uvm/uvm_ats_faults.h index ca67387e7..f58e7a601 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_faults.h +++ b/kernel-open/nvidia-uvm/uvm_ats_faults.h @@ -52,7 +52,7 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, bool uvm_ats_check_in_gmmu_region(uvm_va_space_t *va_space, NvU64 address, uvm_va_range_t *next); // This function performs pending TLB invalidations for ATS and clears the -// ats_invalidate->write_faults_in_batch flag +// ats_invalidate->tlb_batch_pending flag NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, uvm_ats_fault_invalidate_t *ats_invalidate, uvm_tracker_t *out_tracker); diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.c b/kernel-open/nvidia-uvm/uvm_ats_sva.c index f9753d2c1..d4b9e2c4e 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_sva.c +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.c @@ -29,8 +29,13 @@ #include "uvm_va_space.h" #include "uvm_va_space_mm.h" +#include <asm/io.h> +#include <linux/log2.h> #include <linux/iommu.h> #include <linux/mm_types.h> +#include <linux/acpi.h> +#include <linux/device.h> +#include <linux/mmu_context.h> // linux/sched/mm.h is needed for mmget_not_zero and mmput to get the mm // reference required for the iommu_sva_bind_device() call. This header is not @@ -46,17 +51,276 @@ #define UVM_IOMMU_SVA_BIND_DEVICE(dev, mm) iommu_sva_bind_device(dev, mm) #endif +// Type to represent a 128-bit SMMU command queue command. +struct smmu_cmd { + NvU64 low; + NvU64 high; +}; + +// Base address of SMMU CMDQ-V for GSMMU0. +#define SMMU_CMDQV_BASE_ADDR(smmu_base) (smmu_base + 0x200000) +#define SMMU_CMDQV_BASE_LEN 0x00830000 + +// CMDQV configuration is done by firmware but we check status here. +#define SMMU_CMDQV_CONFIG 0x0 +#define SMMU_CMDQV_CONFIG_CMDQV_EN BIT(0) + +// Used to map a particular VCMDQ to a VINTF. +#define SMMU_CMDQV_CMDQ_ALLOC_MAP(vcmdq_id) (0x200 + 0x4 * (vcmdq_id)) +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC BIT(0) + +// Shift for the field containing the index of the virtual interface +// owning the VCMDQ. +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_VIRT_INTF_INDX_SHIFT 15 + +// Base address for the VINTF registers. +#define SMMU_VINTF_BASE_ADDR(cmdqv_base_addr, vintf_id) (cmdqv_base_addr + 0x1000 + 0x100 * (vintf_id)) + +// Virtual interface (VINTF) configuration registers. The WAR only +// works on baremetal so we need to configure ourselves as the +// hypervisor owner. +#define SMMU_VINTF_CONFIG 0x0 +#define SMMU_VINTF_CONFIG_ENABLE BIT(0) +#define SMMU_VINTF_CONFIG_HYP_OWN BIT(17) + +#define SMMU_VINTF_STATUS 0x0 +#define SMMU_VINTF_STATUS_ENABLED BIT(0) + +// Caclulates the base address for a particular VCMDQ instance. +#define SMMU_VCMDQ_BASE_ADDR(cmdqv_base_addr, vcmdq_id) (cmdqv_base_addr + 0x10000 + 0x80 * (vcmdq_id)) + +// SMMU command queue consumer index register. Updated by SMMU +// when commands are consumed. +#define SMMU_VCMDQ_CONS 0x0 + +// SMMU command queue producer index register. Updated by UVM when +// commands are added to the queue. +#define SMMU_VCMDQ_PROD 0x4 + +// Configuration register used to enable a VCMDQ. +#define SMMU_VCMDQ_CONFIG 0x8 +#define SMMU_VCMDQ_CONFIG_ENABLE BIT(0) + +// Status register used to check the VCMDQ is enabled. +#define SMMU_VCMDQ_STATUS 0xc +#define SMMU_VCMDQ_STATUS_ENABLED BIT(0) + +// Base address offset for the VCMDQ registers. +#define SMMU_VCMDQ_CMDQ_BASE 0x10000 + +// Size of the command queue. Each command is 16 bytes and we can't +// have a command queue greater than one page in size. +#define SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE (PAGE_SHIFT - ilog2(sizeof(struct smmu_cmd))) +#define SMMU_VCMDQ_CMDQ_ENTRIES (1UL << SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE) + +// We always use VINTF63 for the WAR +#define VINTF 63 +static void smmu_vintf_write32(void __iomem *smmu_cmdqv_base, int reg, NvU32 val) +{ + iowrite32(val, SMMU_VINTF_BASE_ADDR(smmu_cmdqv_base, VINTF) + reg); +} + +static NvU32 smmu_vintf_read32(void __iomem *smmu_cmdqv_base, int reg) +{ + return ioread32(SMMU_VINTF_BASE_ADDR(smmu_cmdqv_base, VINTF) + reg); +} + +// We always use VCMDQ127 for the WAR +#define VCMDQ 127 +void smmu_vcmdq_write32(void __iomem *smmu_cmdqv_base, int reg, NvU32 val) +{ + iowrite32(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +NvU32 smmu_vcmdq_read32(void __iomem *smmu_cmdqv_base, int reg) +{ + return ioread32(SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +static void smmu_vcmdq_write64(void __iomem *smmu_cmdqv_base, int reg, NvU64 val) +{ + iowrite64(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +// Fix for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU +// TLB invalidates on read-only to read-write upgrades +static NV_STATUS uvm_ats_smmu_war_init(uvm_parent_gpu_t *parent_gpu) +{ + uvm_spin_loop_t spin; + NV_STATUS status; + unsigned long cmdqv_config; + void __iomem *smmu_cmdqv_base; + struct acpi_iort_node *node; + struct acpi_iort_smmu_v3 *iort_smmu; + + node = *(struct acpi_iort_node **) dev_get_platdata(parent_gpu->pci_dev->dev.iommu->iommu_dev->dev->parent); + iort_smmu = (struct acpi_iort_smmu_v3 *) node->node_data; + + smmu_cmdqv_base = ioremap(SMMU_CMDQV_BASE_ADDR(iort_smmu->base_address), SMMU_CMDQV_BASE_LEN); + if (!smmu_cmdqv_base) + return NV_ERR_NO_MEMORY; + + parent_gpu->smmu_war.smmu_cmdqv_base = smmu_cmdqv_base; + cmdqv_config = ioread32(smmu_cmdqv_base + SMMU_CMDQV_CONFIG); + if (!(cmdqv_config & SMMU_CMDQV_CONFIG_CMDQV_EN)) { + status = NV_ERR_OBJECT_NOT_FOUND; + goto out; + } + + // Allocate SMMU CMDQ pages for WAR + parent_gpu->smmu_war.smmu_cmdq = alloc_page(NV_UVM_GFP_FLAGS | __GFP_ZERO); + if (!parent_gpu->smmu_war.smmu_cmdq) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + // Initialise VINTF for the WAR + smmu_vintf_write32(smmu_cmdqv_base, SMMU_VINTF_CONFIG, SMMU_VINTF_CONFIG_ENABLE | SMMU_VINTF_CONFIG_HYP_OWN); + UVM_SPIN_WHILE(!(smmu_vintf_read32(smmu_cmdqv_base, SMMU_VINTF_STATUS) & SMMU_VINTF_STATUS_ENABLED), &spin); + + // Allocate VCMDQ to VINTF + iowrite32((VINTF << SMMU_CMDQV_CMDQ_ALLOC_MAP_VIRT_INTF_INDX_SHIFT) | SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC, + smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + + smmu_vcmdq_write64(smmu_cmdqv_base, SMMU_VCMDQ_CMDQ_BASE, + page_to_phys(parent_gpu->smmu_war.smmu_cmdq) | SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONS, 0); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_PROD, 0); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONFIG, SMMU_VCMDQ_CONFIG_ENABLE); + UVM_SPIN_WHILE(!(smmu_vcmdq_read32(smmu_cmdqv_base, SMMU_VCMDQ_STATUS) & SMMU_VCMDQ_STATUS_ENABLED), &spin); + + uvm_mutex_init(&parent_gpu->smmu_war.smmu_lock, UVM_LOCK_ORDER_LEAF); + parent_gpu->smmu_war.smmu_prod = 0; + parent_gpu->smmu_war.smmu_cons = 0; + + return NV_OK; + +out: + iounmap(parent_gpu->smmu_war.smmu_cmdqv_base); + parent_gpu->smmu_war.smmu_cmdqv_base = NULL; + + return status; +} + +static void uvm_ats_smmu_war_deinit(uvm_parent_gpu_t *parent_gpu) +{ + void __iomem *smmu_cmdqv_base = parent_gpu->smmu_war.smmu_cmdqv_base; + NvU32 cmdq_alloc_map; + + if (parent_gpu->smmu_war.smmu_cmdqv_base) { + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONFIG, 0); + cmdq_alloc_map = ioread32(smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + iowrite32(cmdq_alloc_map & SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC, smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + smmu_vintf_write32(smmu_cmdqv_base, SMMU_VINTF_CONFIG, 0); + } + + if (parent_gpu->smmu_war.smmu_cmdq) + __free_page(parent_gpu->smmu_war.smmu_cmdq); + + if (parent_gpu->smmu_war.smmu_cmdqv_base) + iounmap(parent_gpu->smmu_war.smmu_cmdqv_base); +} + +// The SMMU on ARM64 can run under different translation regimes depending on +// what features the OS and CPU variant support. The CPU for GH180 supports +// virtualisation extensions and starts the kernel at EL2 meaning SMMU operates +// under the NS-EL2-E2H translation regime. Therefore we need to use the +// TLBI_EL2_* commands which invalidate TLB entries created under this +// translation regime. +#define CMDQ_OP_TLBI_EL2_ASID 0x21; +#define CMDQ_OP_TLBI_EL2_VA 0x22; +#define CMDQ_OP_CMD_SYNC 0x46 + +// Use the same maximum as used for MAX_TLBI_OPS in the upstream +// kernel. +#define UVM_MAX_TLBI_OPS (1UL << (PAGE_SHIFT - 3)) + +#if UVM_ATS_SMMU_WAR_REQUIRED() +void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) +{ + struct mm_struct *mm = gpu_va_space->va_space->va_space_mm.mm; + uvm_parent_gpu_t *parent_gpu = gpu_va_space->gpu->parent; + struct { + NvU64 low; + NvU64 high; + } *vcmdq; + unsigned long vcmdq_prod; + NvU64 end; + uvm_spin_loop_t spin; + NvU16 asid; + + if (!parent_gpu->smmu_war.smmu_cmdqv_base) + return; + + asid = arm64_mm_context_get(mm); + vcmdq = kmap(parent_gpu->smmu_war.smmu_cmdq); + uvm_mutex_lock(&parent_gpu->smmu_war.smmu_lock); + vcmdq_prod = parent_gpu->smmu_war.smmu_prod; + + // Our queue management is very simple. The mutex prevents multiple + // producers writing to the queue and all our commands require waiting for + // the queue to drain so we know it's empty. If we can't fit enough commands + // in the queue we just invalidate the whole ASID. + // + // The command queue is a cirular buffer with the MSB representing a wrap + // bit that must toggle on each wrap. See the SMMU architecture + // specification for more details. + // + // SMMU_VCMDQ_CMDQ_ENTRIES - 1 because we need to leave space for the + // CMD_SYNC. + if ((size >> PAGE_SHIFT) > min(UVM_MAX_TLBI_OPS, SMMU_VCMDQ_CMDQ_ENTRIES - 1)) { + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_TLBI_EL2_ASID; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low |= (NvU64) asid << 48; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = 0; + vcmdq_prod++; + } + else { + for (end = addr + size; addr < end; addr += PAGE_SIZE) { + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_TLBI_EL2_VA; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low |= (NvU64) asid << 48; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = addr & ~((1UL << 12) - 1); + vcmdq_prod++; + } + } + + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_CMD_SYNC; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = 0x0; + vcmdq_prod++; + + // MSB is the wrap bit + vcmdq_prod &= (1UL << (SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE + 1)) - 1; + parent_gpu->smmu_war.smmu_prod = vcmdq_prod; + smmu_vcmdq_write32(parent_gpu->smmu_war.smmu_cmdqv_base, SMMU_VCMDQ_PROD, parent_gpu->smmu_war.smmu_prod); + + UVM_SPIN_WHILE( + (smmu_vcmdq_read32(parent_gpu->smmu_war.smmu_cmdqv_base, SMMU_VCMDQ_CONS) & GENMASK(19, 0)) != vcmdq_prod, + &spin); + + uvm_mutex_unlock(&parent_gpu->smmu_war.smmu_lock); + kunmap(parent_gpu->smmu_war.smmu_cmdq); + arm64_mm_context_put(mm); +} +#endif + NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) { int ret; ret = iommu_dev_enable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); + if (ret) + return errno_to_nv_status(ret); - return errno_to_nv_status(ret); + if (UVM_ATS_SMMU_WAR_REQUIRED()) + return uvm_ats_smmu_war_init(parent_gpu); + else + return NV_OK; } void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu) { + if (UVM_ATS_SMMU_WAR_REQUIRED()) + uvm_ats_smmu_war_deinit(parent_gpu); + iommu_dev_disable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); } diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.h b/kernel-open/nvidia-uvm/uvm_ats_sva.h index 120ecfbf5..1466c6e47 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_sva.h +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.h @@ -32,23 +32,38 @@ // For ATS support on aarch64, arm_smmu_sva_bind() is needed for // iommu_sva_bind_device() calls. Unfortunately, arm_smmu_sva_bind() is not // conftest-able. We instead look for the presence of ioasid_get() or -// mm_pasid_set(). ioasid_get() was added in the same patch series as -// arm_smmu_sva_bind() and removed in v6.0. mm_pasid_set() was added in the +// mm_pasid_drop(). ioasid_get() was added in the same patch series as +// arm_smmu_sva_bind() and removed in v6.0. mm_pasid_drop() was added in the // same patch as the removal of ioasid_get(). We assume the presence of -// arm_smmu_sva_bind() if ioasid_get(v5.11 - v5.17) or mm_pasid_set(v5.18+) is +// arm_smmu_sva_bind() if ioasid_get(v5.11 - v5.17) or mm_pasid_drop(v5.18+) is // present. // // arm_smmu_sva_bind() was added with commit // 32784a9562fb0518b12e9797ee2aec52214adf6f and ioasid_get() was added with // commit cb4789b0d19ff231ce9f73376a023341300aed96 (11/23/2020). Commit // 701fac40384f07197b106136012804c3cae0b3de (02/15/2022) removed ioasid_get() -// and added mm_pasid_set(). - #if UVM_CAN_USE_MMU_NOTIFIERS() && (defined(NV_IOASID_GET_PRESENT) || defined(NV_MM_PASID_SET_PRESENT)) - #define UVM_ATS_SVA_SUPPORTED() 1 +// and added mm_pasid_drop(). + #if UVM_CAN_USE_MMU_NOTIFIERS() && (defined(NV_IOASID_GET_PRESENT) || defined(NV_MM_PASID_DROP_PRESENT)) + #if defined(CONFIG_IOMMU_SVA) + #define UVM_ATS_SVA_SUPPORTED() 1 + #else + #define UVM_ATS_SVA_SUPPORTED() 0 + #endif #else #define UVM_ATS_SVA_SUPPORTED() 0 #endif +// If NV_ARCH_INVALIDATE_SECONDARY_TLBS is defined it means the upstream fix is +// in place so no need for the WAR from Bug 4130089: [GH180][r535] WAR for +// kernel not issuing SMMU TLB invalidates on read-only +#if defined(NV_ARCH_INVALIDATE_SECONDARY_TLBS) + #define UVM_ATS_SMMU_WAR_REQUIRED() 0 +#elif NVCPU_IS_AARCH64 + #define UVM_ATS_SMMU_WAR_REQUIRED() 1 +#else + #define UVM_ATS_SMMU_WAR_REQUIRED() 0 +#endif + typedef struct { int placeholder; @@ -77,6 +92,17 @@ typedef struct // LOCKING: None void uvm_ats_sva_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space); + + // Fix for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU + // TLB invalidates on read-only to read-write upgrades + #if UVM_ATS_SMMU_WAR_REQUIRED() + void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size); + #else + static void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) + { + + } + #endif #else static NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) { @@ -107,6 +133,11 @@ typedef struct { } + + static void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) + { + + } #endif // UVM_ATS_SVA_SUPPORTED #endif // __UVM_ATS_SVA_H__ diff --git a/kernel-open/nvidia-uvm/uvm_ce_test.c b/kernel-open/nvidia-uvm/uvm_ce_test.c index c33ffc53c..90e7c2dbc 100644 --- a/kernel-open/nvidia-uvm/uvm_ce_test.c +++ b/kernel-open/nvidia-uvm/uvm_ce_test.c @@ -191,7 +191,7 @@ static NV_STATUS test_membar(uvm_gpu_t *gpu) for (i = 0; i < REDUCTIONS; ++i) { uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - gpu->parent->ce_hal->semaphore_reduction_inc(&push, host_mem_gpu_va, REDUCTIONS + 1); + gpu->parent->ce_hal->semaphore_reduction_inc(&push, host_mem_gpu_va, REDUCTIONS); } // Without a sys membar the channel tracking semaphore can and does complete @@ -577,7 +577,7 @@ static NV_STATUS test_semaphore_reduction_inc(uvm_gpu_t *gpu) for (i = 0; i < REDUCTIONS; i++) { uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - gpu->parent->ce_hal->semaphore_reduction_inc(&push, gpu_va, i+1); + gpu->parent->ce_hal->semaphore_reduction_inc(&push, gpu_va, REDUCTIONS); } status = uvm_push_end_and_wait(&push); diff --git a/kernel-open/nvidia-uvm/uvm_common.h b/kernel-open/nvidia-uvm/uvm_common.h index 7631c2610..f6620ce63 100644 --- a/kernel-open/nvidia-uvm/uvm_common.h +++ b/kernel-open/nvidia-uvm/uvm_common.h @@ -21,8 +21,8 @@ *******************************************************************************/ -#ifndef _UVM_COMMON_H -#define _UVM_COMMON_H +#ifndef __UVM_COMMON_H__ +#define __UVM_COMMON_H__ #ifdef DEBUG #define UVM_IS_DEBUG() 1 @@ -413,4 +413,40 @@ static inline void uvm_touch_page(struct page *page) // Return true if the VMA is one used by UVM managed allocations. bool uvm_vma_is_managed(struct vm_area_struct *vma); -#endif /* _UVM_COMMON_H */ +static bool uvm_platform_uses_canonical_form_address(void) +{ + if (NVCPU_IS_PPC64LE) + return false; + + return true; +} + +// Similar to the GPU MMU HAL num_va_bits(), it returns the CPU's num_va_bits(). +static NvU32 uvm_cpu_num_va_bits(void) +{ + return fls64(TASK_SIZE - 1) + 1; +} + +// Return the unaddressable range in a num_va_bits-wide VA space, [first, outer) +static void uvm_get_unaddressable_range(NvU32 num_va_bits, NvU64 *first, NvU64 *outer) +{ + UVM_ASSERT(num_va_bits < 64); + UVM_ASSERT(first); + UVM_ASSERT(outer); + + if (uvm_platform_uses_canonical_form_address()) { + *first = 1ULL << (num_va_bits - 1); + *outer = (NvU64)((NvS64)(1ULL << 63) >> (64 - num_va_bits)); + } + else { + *first = 1ULL << num_va_bits; + *outer = ~0Ull; + } +} + +static void uvm_cpu_get_unaddressable_range(NvU64 *first, NvU64 *outer) +{ + return uvm_get_unaddressable_range(uvm_cpu_num_va_bits(), first, outer); +} + +#endif /* __UVM_COMMON_H__ */ diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c index 6e4551b18..9070f4445 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_gpu.c @@ -218,19 +218,12 @@ static bool gpu_supports_uvm(uvm_parent_gpu_t *parent_gpu) return parent_gpu->rm_info.subdeviceCount == 1; } -static bool platform_uses_canonical_form_address(void) -{ - if (NVCPU_IS_PPC64LE) - return false; - - return true; -} - bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) { // Lower and upper address spaces are typically found in platforms that use // the canonical address form. NvU64 max_va_lower; + NvU64 min_va_upper; NvU64 addr_end = addr + size - 1; NvU8 gpu_addr_shift; NvU8 cpu_addr_shift; @@ -243,7 +236,7 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) UVM_ASSERT(size > 0); gpu_addr_shift = gpu->address_space_tree.hal->num_va_bits(); - cpu_addr_shift = fls64(TASK_SIZE - 1) + 1; + cpu_addr_shift = uvm_cpu_num_va_bits(); addr_shift = gpu_addr_shift; // Pascal+ GPUs are capable of accessing kernel pointers in various modes @@ -279,9 +272,7 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) // 0 +----------------+ 0 +----------------+ // On canonical form address platforms and Pascal+ GPUs. - if (platform_uses_canonical_form_address() && gpu_addr_shift > 40) { - NvU64 min_va_upper; - + if (uvm_platform_uses_canonical_form_address() && gpu_addr_shift > 40) { // On x86, when cpu_addr_shift > gpu_addr_shift, it means the CPU uses // 5-level paging and the GPU is pre-Hopper. On Pascal-Ada GPUs (49b // wide VA) we set addr_shift to match a 4-level paging x86 (48b wide). @@ -292,15 +283,11 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) addr_shift = gpu_addr_shift; else addr_shift = cpu_addr_shift; - - min_va_upper = (NvU64)((NvS64)(1ULL << 63) >> (64 - addr_shift)); - max_va_lower = 1ULL << (addr_shift - 1); - return (addr_end < max_va_lower) || (addr >= min_va_upper); - } - else { - max_va_lower = 1ULL << addr_shift; - return addr_end < max_va_lower; } + + uvm_get_unaddressable_range(addr_shift, &max_va_lower, &min_va_upper); + + return (addr_end < max_va_lower) || (addr >= min_va_upper); } // The internal UVM VAS does not use canonical form addresses. @@ -326,14 +313,14 @@ NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr) NvU8 addr_shift; NvU64 input_addr = addr; - if (platform_uses_canonical_form_address()) { + if (uvm_platform_uses_canonical_form_address()) { // When the CPU VA width is larger than GPU's, it means that: // On ARM: the CPU is on LVA mode and the GPU is pre-Hopper. // On x86: the CPU uses 5-level paging and the GPU is pre-Hopper. // We sign-extend on the 48b on ARM and on the 47b on x86 to mirror the // behavior of CPUs with smaller (than GPU) VA widths. gpu_addr_shift = parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits(); - cpu_addr_shift = fls64(TASK_SIZE - 1) + 1; + cpu_addr_shift = uvm_cpu_num_va_bits(); if (cpu_addr_shift > gpu_addr_shift) addr_shift = NVCPU_IS_X86_64 ? 48 : 49; diff --git a/kernel-open/nvidia-uvm/uvm_gpu.h b/kernel-open/nvidia-uvm/uvm_gpu.h index 8e13f6fe4..42bb83e3e 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_gpu.h @@ -57,14 +57,16 @@ typedef struct { - // Number of faults from this uTLB that have been fetched but have not been serviced yet + // Number of faults from this uTLB that have been fetched but have not been + // serviced yet. NvU32 num_pending_faults; // Whether the uTLB contains fatal faults bool has_fatal_faults; - // We have issued a replay of type START_ACK_ALL while containing fatal faults. This puts - // the uTLB in lockdown mode and no new translations are accepted + // We have issued a replay of type START_ACK_ALL while containing fatal + // faults. This puts the uTLB in lockdown mode and no new translations are + // accepted. bool in_lockdown; // We have issued a cancel on this uTLB @@ -126,8 +128,8 @@ struct uvm_service_block_context_struct struct list_head service_context_list; // A mask of GPUs that need to be checked for ECC errors before the CPU - // fault handler returns, but after the VA space lock has been unlocked to - // avoid the RM/UVM VA space lock deadlocks. + // fault handler returns, but after the VA space lock has been unlocked + // to avoid the RM/UVM VA space lock deadlocks. uvm_processor_mask_t gpus_to_check_for_ecc; // This is set to throttle page fault thrashing. @@ -160,9 +162,9 @@ struct uvm_service_block_context_struct struct { - // Per-processor mask with the pages that will be resident after servicing. - // We need one mask per processor because we may coalesce faults that - // trigger migrations to different processors. + // Per-processor mask with the pages that will be resident after + // servicing. We need one mask per processor because we may coalesce + // faults that trigger migrations to different processors. uvm_page_mask_t new_residency; } per_processor_masks[UVM_ID_MAX_PROCESSORS]; @@ -263,7 +265,10 @@ struct uvm_fault_service_batch_context_struct NvU32 num_coalesced_faults; - bool has_fatal_faults; + // One of the VA spaces in this batch which had fatal faults. If NULL, no + // faults were fatal. More than one VA space could have fatal faults, but we + // pick one to be the target of the cancel sequence. + uvm_va_space_t *fatal_va_space; bool has_throttled_faults; @@ -291,11 +296,8 @@ struct uvm_fault_service_batch_context_struct struct uvm_ats_fault_invalidate_struct { - // Whether the TLB batch contains any information - bool write_faults_in_batch; - - // Batch of TLB entries to be invalidated - uvm_tlb_batch_t write_faults_tlb_batch; + bool tlb_batch_pending; + uvm_tlb_batch_t tlb_batch; }; typedef struct @@ -440,20 +442,9 @@ struct uvm_access_counter_service_batch_context_struct NvU32 num_notifications; // Boolean used to avoid sorting the fault batch by instance_ptr if we - // determine at fetch time that all the access counter notifications in the - // batch report the same instance_ptr + // determine at fetch time that all the access counter notifications in + // the batch report the same instance_ptr bool is_single_instance_ptr; - - // Scratch space, used to generate artificial physically addressed notifications. - // Virtual address notifications are always aligned to 64k. This means up to 16 - // different physical locations could have been accessed to trigger one notification. - // The sub-granularity mask can correspond to any of them. - struct - { - uvm_processor_id_t resident_processors[16]; - uvm_gpu_phys_address_t phys_addresses[16]; - uvm_access_counter_buffer_entry_t phys_entry; - } scratch; } virt; struct @@ -464,8 +455,8 @@ struct uvm_access_counter_service_batch_context_struct NvU32 num_notifications; // Boolean used to avoid sorting the fault batch by aperture if we - // determine at fetch time that all the access counter notifications in the - // batch report the same aperture + // determine at fetch time that all the access counter notifications in + // the batch report the same aperture bool is_single_aperture; } phys; @@ -661,8 +652,8 @@ struct uvm_gpu_struct struct { // Big page size used by the internal UVM VA space - // Notably it may be different than the big page size used by a user's VA - // space in general. + // Notably it may be different than the big page size used by a user's + // VA space in general. NvU32 internal_size; } big_page; @@ -688,8 +679,8 @@ struct uvm_gpu_struct // lazily-populated array of peer GPUs, indexed by the peer's GPU index uvm_gpu_t *peer_gpus[UVM_ID_MAX_GPUS]; - // Leaf spinlock used to synchronize access to the peer_gpus table so that - // it can be safely accessed from the access counters bottom half + // Leaf spinlock used to synchronize access to the peer_gpus table so + // that it can be safely accessed from the access counters bottom half uvm_spinlock_t peer_gpus_lock; } peer_info; @@ -980,6 +971,10 @@ struct uvm_parent_gpu_struct bool plc_supported; + // If true, page_tree initialization pre-populates no_ats_ranges. It only + // affects ATS systems. + bool no_ats_range_required; + // Parameters used by the TLB batching API struct { @@ -1051,14 +1046,16 @@ struct uvm_parent_gpu_struct // Interrupt handling state and locks uvm_isr_info_t isr; - // Fault buffer info. This is only valid if supports_replayable_faults is set to true + // Fault buffer info. This is only valid if supports_replayable_faults is + // set to true. uvm_fault_buffer_info_t fault_buffer_info; // PMM lazy free processing queue. // TODO: Bug 3881835: revisit whether to use nv_kthread_q_t or workqueue. nv_kthread_q_t lazy_free_q; - // Access counter buffer info. This is only valid if supports_access_counters is set to true + // Access counter buffer info. This is only valid if + // supports_access_counters is set to true. uvm_access_counter_buffer_info_t access_counter_buffer_info; // Number of uTLBs per GPC. This information is only valid on Pascal+ GPUs. @@ -1108,7 +1105,7 @@ struct uvm_parent_gpu_struct uvm_rb_tree_t instance_ptr_table; uvm_spinlock_t instance_ptr_table_lock; - // This is set to true if the GPU belongs to an SLI group. Else, set to false. + // This is set to true if the GPU belongs to an SLI group. bool sli_enabled; struct @@ -1135,8 +1132,8 @@ struct uvm_parent_gpu_struct // environment, rather than using the peer-id field of the PTE (which can // only address 8 gpus), all gpus are assigned a 47-bit physical address // space by the fabric manager. Any physical address access to these - // physical address spaces are routed through the switch to the corresponding - // peer. + // physical address spaces are routed through the switch to the + // corresponding peer. struct { bool is_nvswitch_connected; @@ -1162,6 +1159,16 @@ struct uvm_parent_gpu_struct NvU64 memory_window_start; NvU64 memory_window_end; } system_bus; + + // WAR to issue ATS TLB invalidation commands ourselves. + struct + { + uvm_mutex_t smmu_lock; + struct page *smmu_cmdq; + void __iomem *smmu_cmdqv_base; + unsigned long smmu_prod; + unsigned long smmu_cons; + } smmu_war; }; static const char *uvm_gpu_name(uvm_gpu_t *gpu) @@ -1351,7 +1358,8 @@ void uvm_gpu_release_pcie_peer_access(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1); // They must not be the same gpu. uvm_aperture_t uvm_gpu_peer_aperture(uvm_gpu_t *local_gpu, uvm_gpu_t *remote_gpu); -// Get the processor id accessible by the given GPU for the given physical address +// Get the processor id accessible by the given GPU for the given physical +// address. uvm_processor_id_t uvm_gpu_get_processor_id_by_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t addr); // Get the P2P capabilities between the gpus with the given indexes @@ -1448,9 +1456,9 @@ NV_STATUS uvm_gpu_check_ecc_error(uvm_gpu_t *gpu); // Check for ECC errors without calling into RM // -// Calling into RM is problematic in many places, this check is always safe to do. -// Returns NV_WARN_MORE_PROCESSING_REQUIRED if there might be an ECC error and -// it's required to call uvm_gpu_check_ecc_error() to be sure. +// Calling into RM is problematic in many places, this check is always safe to +// do. Returns NV_WARN_MORE_PROCESSING_REQUIRED if there might be an ECC error +// and it's required to call uvm_gpu_check_ecc_error() to be sure. NV_STATUS uvm_gpu_check_ecc_error_no_rm(uvm_gpu_t *gpu); // Map size bytes of contiguous sysmem on the GPU for physical access @@ -1507,6 +1515,8 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); // The GPU must be initialized before calling this function. bool uvm_gpu_can_address_kernel(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); +bool uvm_platform_uses_canonical_form_address(void); + // Returns addr's canonical form for host systems that use canonical form // addresses. NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr); @@ -1553,8 +1563,9 @@ uvm_aperture_t uvm_gpu_page_tree_init_location(const uvm_gpu_t *gpu); // Debug print of GPU properties void uvm_gpu_print(uvm_gpu_t *gpu); -// Add the given instance pointer -> user_channel mapping to this GPU. The bottom -// half GPU page fault handler uses this to look up the VA space for GPU faults. +// Add the given instance pointer -> user_channel mapping to this GPU. The +// bottom half GPU page fault handler uses this to look up the VA space for GPU +// faults. NV_STATUS uvm_gpu_add_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel); void uvm_gpu_remove_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c index b3d3a3d3e..77512d6db 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c @@ -33,17 +33,17 @@ #include "uvm_va_space_mm.h" #include "uvm_pmm_sysmem.h" #include "uvm_perf_module.h" +#include "uvm_ats_ibm.h" #define UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_MIN 1 #define UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_DEFAULT 256 -#define UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT "2m" +#define UVM_PERF_ACCESS_COUNTER_GRANULARITY UVM_ACCESS_COUNTER_GRANULARITY_2M #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_MIN 1 #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_MAX ((1 << 16) - 1) #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_DEFAULT 256 -#define UVM_ACCESS_COUNTER_ACTION_NOTIFY 0x1 -#define UVM_ACCESS_COUNTER_ACTION_CLEAR 0x2 -#define UVM_ACCESS_COUNTER_ON_MANAGED 0x4 +#define UVM_ACCESS_COUNTER_ACTION_CLEAR 0x1 +#define UVM_ACCESS_COUNTER_PHYS_ON_MANAGED 0x2 // Each page in a tracked physical range may belong to a different VA Block. We // preallocate an array of reverse map translations. However, access counter @@ -54,12 +54,6 @@ #define UVM_MAX_TRANSLATION_SIZE (2 * 1024 * 1024ULL) #define UVM_SUB_GRANULARITY_REGIONS 32 -// The GPU offers the following tracking granularities: 64K, 2M, 16M, 16G -// -// Use the largest granularity to minimize the number of access counter -// notifications. This is fine because we simply drop the notifications during -// normal operation, and tests override these values. -static UVM_ACCESS_COUNTER_GRANULARITY g_uvm_access_counter_granularity; static unsigned g_uvm_access_counter_threshold; // Per-VA space access counters information @@ -87,7 +81,6 @@ static int uvm_perf_access_counter_momc_migration_enable = -1; static unsigned uvm_perf_access_counter_batch_count = UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_DEFAULT; // See module param documentation below -static char *uvm_perf_access_counter_granularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT; static unsigned uvm_perf_access_counter_threshold = UVM_PERF_ACCESS_COUNTER_THRESHOLD_DEFAULT; // Module parameters for the tunables @@ -100,10 +93,6 @@ MODULE_PARM_DESC(uvm_perf_access_counter_momc_migration_enable, "Whether MOMC access counters will trigger migrations." "Valid values: <= -1 (default policy), 0 (off), >= 1 (on)"); module_param(uvm_perf_access_counter_batch_count, uint, S_IRUGO); -module_param(uvm_perf_access_counter_granularity, charp, S_IRUGO); -MODULE_PARM_DESC(uvm_perf_access_counter_granularity, - "Size of the physical memory region tracked by each counter. Valid values as" - "of Volta: 64k, 2m, 16m, 16g"); module_param(uvm_perf_access_counter_threshold, uint, S_IRUGO); MODULE_PARM_DESC(uvm_perf_access_counter_threshold, "Number of remote accesses on a region required to trigger a notification." @@ -136,7 +125,7 @@ static va_space_access_counters_info_t *va_space_access_counters_info_get(uvm_va // Whether access counter migrations are enabled or not. The policy is as // follows: -// - MIMC migrations are enabled by default on P9 systems with ATS support +// - MIMC migrations are disabled by default on all systems except P9. // - MOMC migrations are disabled by default on all systems // - Users can override this policy by specifying on/off static bool is_migration_enabled(uvm_access_counter_type_t type) @@ -159,7 +148,10 @@ static bool is_migration_enabled(uvm_access_counter_type_t type) if (type == UVM_ACCESS_COUNTER_TYPE_MOMC) return false; - return g_uvm_global.ats.supported; + if (UVM_ATS_IBM_SUPPORTED()) + return g_uvm_global.ats.supported; + + return false; } // Create the access counters tracking struct for the given VA space @@ -225,30 +217,18 @@ static NV_STATUS config_granularity_to_bytes(UVM_ACCESS_COUNTER_GRANULARITY gran return NV_OK; } -// Clear the given access counter and add it to the per-GPU clear tracker -static NV_STATUS access_counter_clear_targeted(uvm_gpu_t *gpu, - const uvm_access_counter_buffer_entry_t *entry) +// Clear the access counter notifications and add it to the per-GPU clear +// tracker. +static NV_STATUS access_counter_clear_notifications(uvm_gpu_t *gpu, + uvm_access_counter_buffer_entry_t **notification_start, + NvU32 num_notifications) { + NvU32 i; NV_STATUS status; uvm_push_t push; uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; - if (entry->address.is_virtual) { - status = uvm_push_begin(gpu->channel_manager, - UVM_CHANNEL_TYPE_MEMOPS, - &push, - "Clear access counter with virtual address: 0x%llx", - entry->address.address); - } - else { - status = uvm_push_begin(gpu->channel_manager, - UVM_CHANNEL_TYPE_MEMOPS, - &push, - "Clear access counter with physical address: 0x%llx:%s", - entry->address.address, - uvm_aperture_string(entry->address.aperture)); - } - + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, &push, "Clear access counter batch"); if (status != NV_OK) { UVM_ERR_PRINT("Error creating push to clear access counters: %s, GPU %s\n", nvstatusToString(status), @@ -256,7 +236,8 @@ static NV_STATUS access_counter_clear_targeted(uvm_gpu_t *gpu, return status; } - gpu->parent->host_hal->access_counter_clear_targeted(&push, entry); + for (i = 0; i < num_notifications; i++) + gpu->parent->host_hal->access_counter_clear_targeted(&push, notification_start[i]); uvm_push_end(&push); @@ -381,25 +362,6 @@ NV_STATUS uvm_gpu_init_access_counters(uvm_parent_gpu_t *parent_gpu) g_uvm_access_counter_threshold = uvm_perf_access_counter_threshold; } - if (strcmp(uvm_perf_access_counter_granularity, "64k") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_64K; - } - else if (strcmp(uvm_perf_access_counter_granularity, "2m") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_2M; - } - else if (strcmp(uvm_perf_access_counter_granularity, "16m") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_16M; - } - else if (strcmp(uvm_perf_access_counter_granularity, "16g") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_16G; - } - else { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_2M; - pr_info("Invalid value '%s' for uvm_perf_access_counter_granularity, using '%s' instead", - uvm_perf_access_counter_granularity, - UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT); - } - uvm_assert_mutex_locked(&g_uvm_global.global_lock); UVM_ASSERT(parent_gpu->access_counter_buffer_hal != NULL); @@ -422,7 +384,7 @@ NV_STATUS uvm_gpu_init_access_counters(uvm_parent_gpu_t *parent_gpu) UVM_ASSERT(access_counters->rm_info.bufferSize % parent_gpu->access_counter_buffer_hal->entry_size(parent_gpu) == 0); - status = config_granularity_to_bytes(g_uvm_access_counter_granularity, &granularity_bytes); + status = config_granularity_to_bytes(UVM_PERF_ACCESS_COUNTER_GRANULARITY, &granularity_bytes); UVM_ASSERT(status == NV_OK); if (granularity_bytes > UVM_MAX_TRANSLATION_SIZE) UVM_ASSERT(granularity_bytes % UVM_MAX_TRANSLATION_SIZE == 0); @@ -641,8 +603,8 @@ NV_STATUS uvm_gpu_access_counters_enable(uvm_gpu_t *gpu, uvm_va_space_t *va_spac else { UvmGpuAccessCntrConfig default_config = { - .mimcGranularity = g_uvm_access_counter_granularity, - .momcGranularity = g_uvm_access_counter_granularity, + .mimcGranularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY, + .momcGranularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY, .mimcUseLimit = UVM_ACCESS_COUNTER_USE_LIMIT_FULL, .momcUseLimit = UVM_ACCESS_COUNTER_USE_LIMIT_FULL, .threshold = g_uvm_access_counter_threshold, @@ -767,6 +729,22 @@ static int cmp_sort_virt_notifications_by_instance_ptr(const void *_a, const voi return cmp_access_counter_instance_ptr(a, b); } +// Sort comparator for pointers to GVA access counter notification buffer +// entries that sorts by va_space, and fault address. +static int cmp_sort_virt_notifications_by_va_space_address(const void *_a, const void *_b) +{ + const uvm_access_counter_buffer_entry_t **a = (const uvm_access_counter_buffer_entry_t **)_a; + const uvm_access_counter_buffer_entry_t **b = (const uvm_access_counter_buffer_entry_t **)_b; + + int result; + + result = UVM_CMP_DEFAULT((*a)->virtual_info.va_space, (*b)->virtual_info.va_space); + if (result != 0) + return result; + + return UVM_CMP_DEFAULT((*a)->address.address, (*b)->address.address); +} + // Sort comparator for pointers to GPA access counter notification buffer // entries that sorts by physical address' aperture static int cmp_sort_phys_notifications_by_processor_id(const void *_a, const void *_b) @@ -924,12 +902,11 @@ static void translate_virt_notifications_instance_ptrs(uvm_gpu_t *gpu, // GVA notifications provide an instance_ptr and ve_id that can be directly // translated to a VA space. In order to minimize translations, we sort the -// entries by instance_ptr. +// entries by instance_ptr, va_space and notification address in that order. static void preprocess_virt_notifications(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context) { if (!batch_context->virt.is_single_instance_ptr) { - // Sort by instance_ptr sort(batch_context->virt.notifications, batch_context->virt.num_notifications, sizeof(*batch_context->virt.notifications), @@ -938,6 +915,12 @@ static void preprocess_virt_notifications(uvm_gpu_t *gpu, } translate_virt_notifications_instance_ptrs(gpu, batch_context); + + sort(batch_context->virt.notifications, + batch_context->virt.num_notifications, + sizeof(*batch_context->virt.notifications), + cmp_sort_virt_notifications_by_va_space_address, + NULL); } // GPA notifications provide a physical address and an aperture. Sort @@ -946,7 +929,6 @@ static void preprocess_virt_notifications(uvm_gpu_t *gpu, static void preprocess_phys_notifications(uvm_access_counter_service_batch_context_t *batch_context) { if (!batch_context->phys.is_single_aperture) { - // Sort by instance_ptr sort(batch_context->phys.notifications, batch_context->phys.num_notifications, sizeof(*batch_context->phys.notifications), @@ -955,6 +937,28 @@ static void preprocess_phys_notifications(uvm_access_counter_service_batch_conte } } +static NV_STATUS notify_tools_and_process_flags(uvm_gpu_t *gpu, + uvm_access_counter_buffer_entry_t **notification_start, + NvU32 num_entries, + NvU32 flags) +{ + NV_STATUS status = NV_OK; + + if (uvm_enable_builtin_tests) { + // TODO: Bug 4310744: [UVM][TOOLS] Attribute access counter tools events + // to va_space instead of broadcasting. + NvU32 i; + + for (i = 0; i < num_entries; i++) + uvm_tools_broadcast_access_counter(gpu, notification_start[i], flags & UVM_ACCESS_COUNTER_PHYS_ON_MANAGED); + } + + if (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR) + status = access_counter_clear_notifications(gpu, notification_start, num_entries); + + return status; +} + static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, @@ -1163,7 +1167,7 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *current_entry, const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { size_t index; uvm_va_block_t *va_block = reverse_mappings[0].va_block; @@ -1190,7 +1194,6 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, // If an mm is registered with the VA space, we have to retain it // in order to lock it before locking the VA space. mm = uvm_va_space_mm_retain_lock(va_space); - uvm_va_space_down_read(va_space); // Re-check that the VA block is valid after taking the VA block lock. @@ -1251,7 +1254,7 @@ static NV_STATUS service_phys_va_blocks(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *current_entry, const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { NV_STATUS status = NV_OK; size_t index; @@ -1259,7 +1262,7 @@ static NV_STATUS service_phys_va_blocks(uvm_gpu_t *gpu, *out_flags &= ~UVM_ACCESS_COUNTER_ACTION_CLEAR; for (index = 0; index < num_reverse_mappings; ++index) { - unsigned out_flags_local = 0; + NvU32 out_flags_local = 0; status = service_phys_single_va_block(gpu, batch_context, current_entry, @@ -1318,7 +1321,7 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, NvU64 address, unsigned long sub_granularity, size_t *num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { NV_STATUS status; NvU32 region_start, region_end; @@ -1327,7 +1330,10 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, // Get the reverse_map translations for all the regions set in the // sub_granularity field of the counter. - for_each_sub_granularity_region(region_start, region_end, sub_granularity, config->sub_granularity_regions_per_translation) { + for_each_sub_granularity_region(region_start, + region_end, + sub_granularity, + config->sub_granularity_regions_per_translation) { NvU64 local_address = address + region_start * config->sub_granularity_region_size; NvU32 local_translation_size = (region_end - region_start) * config->sub_granularity_region_size; uvm_reverse_map_t *local_reverse_mappings = batch_context->phys.translations + *num_reverse_mappings; @@ -1376,7 +1382,7 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context, const uvm_access_counter_buffer_entry_t *current_entry, - unsigned *out_flags) + NvU32 *out_flags) { NvU64 address; NvU64 translation_index; @@ -1387,7 +1393,7 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, size_t total_reverse_mappings = 0; uvm_gpu_t *resident_gpu = NULL; NV_STATUS status = NV_OK; - unsigned flags = 0; + NvU32 flags = 0; address = current_entry->address.address; UVM_ASSERT(address % config->translation_size == 0); @@ -1415,7 +1421,7 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, for (translation_index = 0; translation_index < config->translations_per_counter; ++translation_index) { size_t num_reverse_mappings; - unsigned out_flags_local = 0; + NvU32 out_flags_local = 0; status = service_phys_notification_translation(gpu, resident_gpu, batch_context, @@ -1437,11 +1443,8 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, sub_granularity = sub_granularity >> config->sub_granularity_regions_per_translation; } - // Currently we only report events for our tests, not for tools - if (uvm_enable_builtin_tests) { - *out_flags |= UVM_ACCESS_COUNTER_ACTION_NOTIFY; - *out_flags |= ((total_reverse_mappings != 0) ? UVM_ACCESS_COUNTER_ON_MANAGED : 0); - } + if (uvm_enable_builtin_tests) + *out_flags |= ((total_reverse_mappings != 0) ? UVM_ACCESS_COUNTER_PHYS_ON_MANAGED : 0); if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) *out_flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; @@ -1454,22 +1457,21 @@ static NV_STATUS service_phys_notifications(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context) { NvU32 i; + uvm_access_counter_buffer_entry_t **notifications = batch_context->phys.notifications; + preprocess_phys_notifications(batch_context); for (i = 0; i < batch_context->phys.num_notifications; ++i) { NV_STATUS status; - uvm_access_counter_buffer_entry_t *current_entry = batch_context->phys.notifications[i]; - unsigned flags = 0; + uvm_access_counter_buffer_entry_t *current_entry = notifications[i]; + NvU32 flags = 0; if (!UVM_ID_IS_VALID(current_entry->physical_info.resident_id)) continue; status = service_phys_notification(gpu, batch_context, current_entry, &flags); - if (flags & UVM_ACCESS_COUNTER_ACTION_NOTIFY) - uvm_tools_broadcast_access_counter(gpu, current_entry, flags & UVM_ACCESS_COUNTER_ON_MANAGED); - if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) - status = access_counter_clear_targeted(gpu, current_entry); + notify_tools_and_process_flags(gpu, ¬ifications[i], 1, flags); if (status != NV_OK) return status; @@ -1478,152 +1480,218 @@ static NV_STATUS service_phys_notifications(uvm_gpu_t *gpu, return NV_OK; } -static int cmp_sort_gpu_phys_addr(const void *_a, const void *_b) +static NV_STATUS service_notification_va_block_helper(struct mm_struct *mm, + uvm_va_block_t *va_block, + uvm_processor_id_t processor, + uvm_access_counter_service_batch_context_t *batch_context) { - return uvm_gpu_phys_addr_cmp(*(uvm_gpu_phys_address_t*)_a, - *(uvm_gpu_phys_address_t*)_b); -} + uvm_va_block_retry_t va_block_retry; + uvm_page_mask_t *accessed_pages = &batch_context->accessed_pages; + uvm_service_block_context_t *service_context = &batch_context->block_service_context; -static bool gpu_phys_same_region(uvm_gpu_phys_address_t a, uvm_gpu_phys_address_t b, NvU64 granularity) -{ - if (a.aperture != b.aperture) - return false; + if (uvm_page_mask_empty(accessed_pages)) + return NV_OK; - UVM_ASSERT(is_power_of_2(granularity)); + uvm_assert_mutex_locked(&va_block->lock); - return UVM_ALIGN_DOWN(a.address, granularity) == UVM_ALIGN_DOWN(b.address, granularity); + service_context->operation = UVM_SERVICE_OPERATION_ACCESS_COUNTERS; + service_context->num_retries = 0; + service_context->block_context.mm = mm; + + return UVM_VA_BLOCK_RETRY_LOCKED(va_block, + &va_block_retry, + service_va_block_locked(processor, + va_block, + &va_block_retry, + service_context, + accessed_pages)); } -static bool phys_address_in_accessed_sub_region(uvm_gpu_phys_address_t address, - NvU64 region_size, - NvU64 sub_region_size, - NvU32 accessed_mask) +static void expand_notification_block(struct mm_struct *mm, + uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_t *va_block, + uvm_page_mask_t *accessed_pages, + const uvm_access_counter_buffer_entry_t *current_entry) { - const unsigned accessed_index = (address.address % region_size) / sub_region_size; + NvU64 addr; + NvU64 granularity = 0; + uvm_gpu_t *resident_gpu = NULL; + uvm_processor_id_t resident_id; + uvm_page_index_t page_index; + uvm_gpu_t *gpu = gpu_va_space->gpu; + const uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; + const uvm_gpu_access_counter_type_config_t *config = get_config_for_type(access_counters, + UVM_ACCESS_COUNTER_TYPE_MIMC); - // accessed_mask is only filled for tracking granularities larger than 64K - if (region_size == UVM_PAGE_SIZE_64K) - return true; + config_granularity_to_bytes(config->rm.granularity, &granularity); - UVM_ASSERT(accessed_index < 32); - return ((1 << accessed_index) & accessed_mask) != 0; + // Granularities other than 2MB can only be enabled by UVM tests. Do nothing + // in that case. + if (granularity != UVM_PAGE_SIZE_2M) + return; + + addr = current_entry->address.address; + + uvm_assert_rwsem_locked(&gpu_va_space->va_space->lock); + uvm_assert_mutex_locked(&va_block->lock); + + page_index = uvm_va_block_cpu_page_index(va_block, addr); + + resident_id = uvm_va_block_page_get_closest_resident(va_block, page_index, gpu->id); + + // resident_id might be invalid or might already be the same as the GPU + // which received the notification if the memory was already migrated before + // acquiring the locks either during the servicing of previous notifications + // or during faults or because of explicit migrations or if the VA range was + // freed after receving the notification. Return NV_OK in such cases. + if (!UVM_ID_IS_VALID(resident_id) || uvm_id_equal(resident_id, gpu->id)) + return; + + if (UVM_ID_IS_GPU(resident_id)) + resident_gpu = uvm_va_space_get_gpu(gpu_va_space->va_space, resident_id); + + if (uvm_va_block_get_physical_size(va_block, resident_id, page_index) != granularity) { + uvm_page_mask_set(accessed_pages, page_index); + } + else { + NvU32 region_start; + NvU32 region_end; + unsigned long sub_granularity = current_entry->sub_granularity; + NvU32 num_regions = config->sub_granularity_regions_per_translation; + NvU32 num_sub_pages = config->sub_granularity_region_size / PAGE_SIZE; + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, resident_id); + + UVM_ASSERT(num_sub_pages >= 1); + + // region_start and region_end refer to sub_granularity indices, not + // page_indices. + for_each_sub_granularity_region(region_start, region_end, sub_granularity, num_regions) { + uvm_page_mask_region_fill(accessed_pages, + uvm_va_block_region(region_start * num_sub_pages, + region_end * num_sub_pages)); + } + + // Remove pages in the va_block which are not resident on resident_id. + // If the GPU is heavily accessing those pages, future access counter + // migrations will migrate them to the GPU. + uvm_page_mask_and(accessed_pages, accessed_pages, resident_mask); + } } -static NV_STATUS service_virt_notification(uvm_gpu_t *gpu, - uvm_access_counter_service_batch_context_t *batch_context, - const uvm_access_counter_buffer_entry_t *current_entry, - unsigned *out_flags) +static NV_STATUS service_virt_notifications_in_block(struct mm_struct *mm, + uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_t *va_block, + uvm_access_counter_service_batch_context_t *batch_context, + NvU32 index, + NvU32 *out_index) { + NvU32 i = index; + NvU32 flags = 0; NV_STATUS status = NV_OK; - NvU64 notification_size; - NvU64 address; - uvm_processor_id_t *resident_processors = batch_context->virt.scratch.resident_processors; - uvm_gpu_phys_address_t *phys_addresses = batch_context->virt.scratch.phys_addresses; - int num_addresses = 0; - int i; + NV_STATUS flags_status; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_va_space_t *va_space = gpu_va_space->va_space; + uvm_page_mask_t *accessed_pages = &batch_context->accessed_pages; + uvm_access_counter_buffer_entry_t **notifications = batch_context->virt.notifications; - // Virtual address notifications are always 64K aligned - NvU64 region_start = current_entry->address.address; - NvU64 region_end = current_entry->address.address + UVM_PAGE_SIZE_64K; - + UVM_ASSERT(va_block); + UVM_ASSERT(i < batch_context->virt.num_notifications); - uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; - uvm_access_counter_type_t counter_type = current_entry->counter_type; + uvm_assert_rwsem_locked(&va_space->lock); - const uvm_gpu_access_counter_type_config_t *config = get_config_for_type(access_counters, counter_type); + uvm_page_mask_zero(accessed_pages); - uvm_va_space_t *va_space = current_entry->virtual_info.va_space; + uvm_mutex_lock(&va_block->lock); - UVM_ASSERT(counter_type == UVM_ACCESS_COUNTER_TYPE_MIMC); + while (i < batch_context->virt.num_notifications) { + uvm_access_counter_buffer_entry_t *current_entry = notifications[i]; + NvU64 address = current_entry->address.address; - // Entries with NULL va_space are simply dropped. - if (!va_space) - return NV_OK; + if ((current_entry->virtual_info.va_space != va_space) || (address > va_block->end)) { + *out_index = i; + break; + } - status = config_granularity_to_bytes(config->rm.granularity, ¬ification_size); - if (status != NV_OK) - return status; + expand_notification_block(mm, gpu_va_space, va_block, accessed_pages, current_entry); - // Collect physical locations that could have been touched - // in the reported 64K VA region. The notification mask can - // correspond to any of them. - uvm_va_space_down_read(va_space); - for (address = region_start; address < region_end;) { - uvm_va_block_t *va_block; + i++; + *out_index = i; + } - NV_STATUS local_status = uvm_va_block_find(va_space, address, &va_block); - if (local_status == NV_ERR_INVALID_ADDRESS || local_status == NV_ERR_OBJECT_NOT_FOUND) { - address += PAGE_SIZE; - continue; - } + status = service_notification_va_block_helper(mm, va_block, gpu->id, batch_context); - uvm_mutex_lock(&va_block->lock); - while (address < va_block->end && address < region_end) { - const unsigned page_index = uvm_va_block_cpu_page_index(va_block, address); - - // UVM va_block always maps the closest resident location to processor - const uvm_processor_id_t res_id = uvm_va_block_page_get_closest_resident(va_block, page_index, gpu->id); - - // Add physical location if it's valid and not local vidmem - if (UVM_ID_IS_VALID(res_id) && !uvm_id_equal(res_id, gpu->id)) { - uvm_gpu_phys_address_t phys_address = uvm_va_block_res_phys_page_address(va_block, page_index, res_id, gpu); - if (phys_address_in_accessed_sub_region(phys_address, - notification_size, - config->sub_granularity_region_size, - current_entry->sub_granularity)) { - resident_processors[num_addresses] = res_id; - phys_addresses[num_addresses] = phys_address; - ++num_addresses; - } - else { - UVM_DBG_PRINT_RL("Skipping phys address %llx:%s, because it couldn't have been accessed in mask %x", - phys_address.address, - uvm_aperture_string(phys_address.aperture), - current_entry->sub_granularity); - } - } + uvm_mutex_unlock(&va_block->lock); - address += PAGE_SIZE; - } - uvm_mutex_unlock(&va_block->lock); - } - uvm_va_space_up_read(va_space); + // Atleast one notification should have been processed. + UVM_ASSERT(index < *out_index); - // The addresses need to be sorted to aid coalescing. - sort(phys_addresses, - num_addresses, - sizeof(*phys_addresses), - cmp_sort_gpu_phys_addr, - NULL); + if (status == NV_OK) + flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; - for (i = 0; i < num_addresses; ++i) { - uvm_access_counter_buffer_entry_t *fake_entry = &batch_context->virt.scratch.phys_entry; + flags_status = notify_tools_and_process_flags(gpu, ¬ifications[index], *out_index - index, flags); - // Skip the current pointer if the physical region was already handled - if (i > 0 && gpu_phys_same_region(phys_addresses[i - 1], phys_addresses[i], notification_size)) { - UVM_ASSERT(uvm_id_equal(resident_processors[i - 1], resident_processors[i])); - continue; - } - UVM_DBG_PRINT_RL("Faking MIMC address[%i/%i]: %llx (granularity mask: %llx) in aperture %s on device %s\n", - i, - num_addresses, - phys_addresses[i].address, - notification_size - 1, - uvm_aperture_string(phys_addresses[i].aperture), - uvm_gpu_name(gpu)); - - // Construct a fake phys addr AC entry - fake_entry->counter_type = current_entry->counter_type; - fake_entry->address.address = UVM_ALIGN_DOWN(phys_addresses[i].address, notification_size); - fake_entry->address.aperture = phys_addresses[i].aperture; - fake_entry->address.is_virtual = false; - fake_entry->physical_info.resident_id = resident_processors[i]; - fake_entry->counter_value = current_entry->counter_value; - fake_entry->sub_granularity = current_entry->sub_granularity; - - status = service_phys_notification(gpu, batch_context, fake_entry, out_flags); - if (status != NV_OK) - break; + if ((status == NV_OK) && (flags_status != NV_OK)) + status = flags_status; + + return status; +} + +static NV_STATUS service_virt_notifications_batch(struct mm_struct *mm, + uvm_gpu_va_space_t *gpu_va_space, + uvm_access_counter_service_batch_context_t *batch_context, + NvU32 index, + NvU32 *out_index) +{ + NV_STATUS status; + uvm_va_block_t *va_block; + uvm_va_space_t *va_space = gpu_va_space->va_space; + uvm_access_counter_buffer_entry_t *current_entry = batch_context->virt.notifications[index]; + NvU64 address = current_entry->address.address; + + UVM_ASSERT(va_space); + + uvm_assert_rwsem_locked(&va_space->lock); + + // Virtual address notifications are always 64K aligned + UVM_ASSERT(IS_ALIGNED(address, UVM_PAGE_SIZE_64K)); + + // TODO: Bug 4309292: [UVM][HMM] Re-enable access counter HMM block + // migrations for virtual notifications on configs with + // 4KB page size + status = uvm_va_block_find(va_space, address, &va_block); + if ((status == NV_OK) && !uvm_va_block_is_hmm(va_block)) { + + UVM_ASSERT(va_block); + + status = service_virt_notifications_in_block(mm, gpu_va_space, va_block, batch_context, index, out_index); + } + else { + NvU32 flags = 0; + + UVM_ASSERT((status == NV_ERR_OBJECT_NOT_FOUND) || + (status == NV_ERR_INVALID_ADDRESS) || + uvm_va_block_is_hmm(va_block)); + + // NV_ERR_OBJECT_NOT_FOUND is returned if the VA range is valid but no + // VA block has been allocated yet. This can happen if there are stale + // notifications in the batch. A new VA range may have been allocated in + // that range. So, clear the notification entry to continue getting + // notifications for the new VA range. + if (status == NV_ERR_OBJECT_NOT_FOUND) + flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; + + // NV_ERR_INVALID_ADDRESS is returned if the corresponding VA range + // doesn't exist or it's not a managed range. Access counter migrations + // are not currently supported on such ranges. + // + // TODO: Bug 1990466: [uvm] Use access counters to trigger migrations + // When support for SAM migrations is addded, clear the notification + // entry if the VA range doesn't exist in order to receive notifications + // when a new VA range is allocated in that region. + status = notify_tools_and_process_flags(gpu_va_space->gpu, &batch_context->virt.notifications[index], 1, flags); + *out_index = index + 1; + + status = NV_OK; } return status; @@ -1632,33 +1700,67 @@ static NV_STATUS service_virt_notification(uvm_gpu_t *gpu, static NV_STATUS service_virt_notifications(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context) { - NvU32 i; + NvU32 i = 0; NV_STATUS status = NV_OK; + struct mm_struct *mm = NULL; + uvm_va_space_t *va_space = NULL; + uvm_va_space_t *prev_va_space = NULL; + uvm_gpu_va_space_t *gpu_va_space = NULL; + + // TODO: Bug 4299018 : Add support for virtual access counter migrations on + // 4K page sizes. + if (PAGE_SIZE == UVM_PAGE_SIZE_4K) { + return notify_tools_and_process_flags(gpu, + batch_context->virt.notifications, + batch_context->virt.num_notifications, + 0); + } + preprocess_virt_notifications(gpu, batch_context); - for (i = 0; i < batch_context->virt.num_notifications; ++i) { - unsigned flags = 0; + while (i < batch_context->virt.num_notifications) { uvm_access_counter_buffer_entry_t *current_entry = batch_context->virt.notifications[i]; + va_space = current_entry->virtual_info.va_space; + + if (va_space != prev_va_space) { + + // New va_space detected, drop locks of the old va_space. + if (prev_va_space) { + uvm_va_space_up_read(prev_va_space); + uvm_va_space_mm_release_unlock(prev_va_space, mm); - status = service_virt_notification(gpu, batch_context, current_entry, &flags); + mm = NULL; + gpu_va_space = NULL; + } + + // Acquire locks for the new va_space. + if (va_space) { + mm = uvm_va_space_mm_retain_lock(va_space); + uvm_va_space_down_read(va_space); - UVM_DBG_PRINT_RL("Processed virt access counter (%d/%d): %sMANAGED (status: %d) clear: %s\n", - i + 1, - batch_context->virt.num_notifications, - (flags & UVM_ACCESS_COUNTER_ON_MANAGED) ? "" : "NOT ", - status, - (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR) ? "YES" : "NO"); + gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); + } - if (uvm_enable_builtin_tests) - uvm_tools_broadcast_access_counter(gpu, current_entry, flags & UVM_ACCESS_COUNTER_ON_MANAGED); + prev_va_space = va_space; + } - if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) - status = access_counter_clear_targeted(gpu, current_entry); + if (va_space && gpu_va_space && uvm_va_space_has_access_counter_migrations(va_space)) { + status = service_virt_notifications_batch(mm, gpu_va_space, batch_context, i, &i); + } + else { + status = notify_tools_and_process_flags(gpu, &batch_context->virt.notifications[i], 1, 0); + i++; + } if (status != NV_OK) break; } + if (va_space) { + uvm_va_space_up_read(va_space); + uvm_va_space_mm_release_unlock(va_space, mm); + } + return status; } @@ -1941,6 +2043,7 @@ NV_STATUS uvm_test_reset_access_counters(UVM_TEST_RESET_ACCESS_COUNTERS_PARAMS * } else { uvm_access_counter_buffer_entry_t entry = { 0 }; + uvm_access_counter_buffer_entry_t *notification = &entry; if (params->counter_type == UVM_TEST_ACCESS_COUNTER_TYPE_MIMC) entry.counter_type = UVM_ACCESS_COUNTER_TYPE_MIMC; @@ -1950,7 +2053,7 @@ NV_STATUS uvm_test_reset_access_counters(UVM_TEST_RESET_ACCESS_COUNTERS_PARAMS * entry.bank = params->bank; entry.tag = params->tag; - status = access_counter_clear_targeted(gpu, &entry); + status = access_counter_clear_notifications(gpu, ¬ification, 1); } if (status == NV_OK) diff --git a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c index 3ba2cde20..7199557f0 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c @@ -235,17 +235,27 @@ static NV_STATUS fetch_non_replayable_fault_buffer_entries(uvm_parent_gpu_t *par return NV_OK; } -// In SRIOV, the UVM (guest) driver does not have access to the privileged -// registers used to clear the faulted bit. Instead, UVM requests host RM to do -// the clearing on its behalf, using a SW method. static bool use_clear_faulted_channel_sw_method(uvm_gpu_t *gpu) { - if (uvm_gpu_is_virt_mode_sriov(gpu)) { + // If true, UVM uses a SW method to request RM to do the clearing on its + // behalf. + bool use_sw_method = false; + + // In SRIOV, the UVM (guest) driver does not have access to the privileged + // registers used to clear the faulted bit. + if (uvm_gpu_is_virt_mode_sriov(gpu)) + use_sw_method = true; + + // In Confidential Computing access to the privileged registers is blocked, + // in order to prevent interference between guests, or between the + // (untrusted) host and the guests. + if (g_uvm_global.conf_computing_enabled) + use_sw_method = true; + + if (use_sw_method) UVM_ASSERT(gpu->parent->has_clear_faulted_channel_sw_method); - return true; - } - return false; + return use_sw_method; } static NV_STATUS clear_faulted_method_on_gpu(uvm_gpu_t *gpu, @@ -570,7 +580,7 @@ static NV_STATUS service_non_managed_fault(uvm_gpu_va_space_t *gpu_va_space, ats_context->client_type = UVM_FAULT_CLIENT_TYPE_HUB; - ats_invalidate->write_faults_in_batch = false; + ats_invalidate->tlb_batch_pending = false; va_range_next = uvm_va_space_iter_first(gpu_va_space->va_space, fault_entry->fault_address, ~0ULL); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c index 0edc9950d..1cad2dcb2 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -362,7 +362,8 @@ static NV_STATUS push_cancel_on_gpu(uvm_gpu_t *gpu, "Cancel targeting instance_ptr {0x%llx:%s}\n", instance_ptr.address, uvm_aperture_string(instance_ptr.aperture)); - } else { + } + else { status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, &replayable_faults->replay_tracker, @@ -697,9 +698,6 @@ static inline int cmp_access_type(uvm_fault_access_type_t a, uvm_fault_access_ty typedef enum { - // Fetch a batch of faults from the buffer. - FAULT_FETCH_MODE_BATCH_ALL, - // Fetch a batch of faults from the buffer. Stop at the first entry that is // not ready yet FAULT_FETCH_MODE_BATCH_READY, @@ -857,9 +855,7 @@ static NV_STATUS fetch_fault_buffer_entries(uvm_gpu_t *gpu, // written out of order UVM_SPIN_WHILE(!gpu->parent->fault_buffer_hal->entry_is_valid(gpu->parent, get), &spin) { // We have some entry to work on. Let's do the rest later. - if (fetch_mode != FAULT_FETCH_MODE_ALL && - fetch_mode != FAULT_FETCH_MODE_BATCH_ALL && - fault_index > 0) + if (fetch_mode == FAULT_FETCH_MODE_BATCH_READY && fault_index > 0) goto done; } @@ -888,6 +884,7 @@ static NV_STATUS fetch_fault_buffer_entries(uvm_gpu_t *gpu, current_entry->va_space = NULL; current_entry->filtered = false; + current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; if (current_entry->fault_source.utlb_id > batch_context->max_utlb_id) { UVM_ASSERT(current_entry->fault_source.utlb_id < replayable_faults->utlb_count); @@ -1184,7 +1181,11 @@ static void mark_fault_fatal(uvm_fault_service_batch_context_t *batch_context, fault_entry->replayable.cancel_va_mode = cancel_va_mode; utlb->has_fatal_faults = true; - batch_context->has_fatal_faults = true; + + if (!batch_context->fatal_va_space) { + UVM_ASSERT(fault_entry->va_space); + batch_context->fatal_va_space = fault_entry->va_space; + } } static void fault_entry_duplicate_flags(uvm_fault_service_batch_context_t *batch_context, @@ -1378,7 +1379,10 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, UVM_ASSERT(current_entry->fault_access_type == uvm_fault_access_type_mask_highest(current_entry->access_type_mask)); - current_entry->is_fatal = false; + // Unserviceable faults were already skipped by the caller. There are no + // unserviceable fault types that could be in the same VA block as a + // serviceable fault. + UVM_ASSERT(!current_entry->is_fatal); current_entry->is_throttled = false; current_entry->is_invalid_prefetch = false; @@ -1512,7 +1516,7 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, ++block_context->num_retries; - if (status == NV_OK && batch_context->has_fatal_faults) + if (status == NV_OK && batch_context->fatal_va_space) status = uvm_va_block_set_cancel(va_block, &block_context->block_context, gpu); return status; @@ -1676,7 +1680,8 @@ static NV_STATUS service_fault_batch_ats_sub_vma(uvm_gpu_va_space_t *gpu_va_spac if (access_type <= UVM_FAULT_ACCESS_TYPE_READ) { cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; } - else if (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE) { + else { + UVM_ASSERT(access_type >= UVM_FAULT_ACCESS_TYPE_WRITE); if (uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ) && !uvm_page_mask_test(reads_serviced_mask, page_index)) cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; @@ -1735,6 +1740,10 @@ static NV_STATUS service_fault_batch_ats_sub(uvm_gpu_va_space_t *gpu_va_space, uvm_fault_access_type_t access_type = current_entry->fault_access_type; bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); + // ATS faults can't be unserviceable, since unserviceable faults require + // GMMU PTEs. + UVM_ASSERT(!current_entry->is_fatal); + i++; update_batch_and_notify_fault(gpu_va_space->gpu, @@ -1934,14 +1943,198 @@ static NV_STATUS service_fault_batch_dispatch(uvm_va_space_t *va_space, return status; } +// Called when a fault in the batch has been marked fatal. Flush the buffer +// under the VA and mmap locks to remove any potential stale fatal faults, then +// service all new faults for just that VA space and cancel those which are +// fatal. Faults in other VA spaces are replayed when done and will be processed +// when normal fault servicing resumes. +static NV_STATUS service_fault_batch_for_cancel(uvm_gpu_t *gpu, uvm_fault_service_batch_context_t *batch_context) +{ + NV_STATUS status = NV_OK; + NvU32 i; + uvm_va_space_t *va_space = batch_context->fatal_va_space; + uvm_gpu_va_space_t *gpu_va_space = NULL; + struct mm_struct *mm; + uvm_replayable_fault_buffer_info_t *replayable_faults = &gpu->parent->fault_buffer_info.replayable; + uvm_service_block_context_t *service_context = &gpu->parent->fault_buffer_info.replayable.block_service_context; + uvm_va_block_context_t *va_block_context = &service_context->block_context; + + UVM_ASSERT(gpu->parent->replayable_faults_supported); + UVM_ASSERT(va_space); + + // Perform the flush and re-fetch while holding the mmap_lock and the + // VA space lock. This avoids stale faults because it prevents any vma + // modifications (mmap, munmap, mprotect) from happening between the time HW + // takes the fault and we cancel it. + mm = uvm_va_space_mm_retain_lock(va_space); + va_block_context->mm = mm; + uvm_va_space_down_read(va_space); + + // We saw fatal faults in this VA space before. Flush while holding + // mmap_lock to make sure those faults come back (aren't stale). + // + // We need to wait until all old fault messages have arrived before + // flushing, hence UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT. + status = fault_buffer_flush_locked(gpu, + UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, + UVM_FAULT_REPLAY_TYPE_START, + batch_context); + if (status != NV_OK) + goto done; + + // Wait for the flush's replay to finish to give the legitimate faults a + // chance to show up in the buffer again. + status = uvm_tracker_wait(&replayable_faults->replay_tracker); + if (status != NV_OK) + goto done; + + // We expect all replayed faults to have arrived in the buffer so we can re- + // service them. The replay-and-wait sequence above will ensure they're all + // in the HW buffer. When GSP owns the HW buffer, we also have to wait for + // GSP to copy all available faults from the HW buffer into the shadow + // buffer. + // + // TODO: Bug 2533557: This flush does not actually guarantee that GSP will + // copy over all faults. + status = hw_fault_buffer_flush_locked(gpu->parent); + if (status != NV_OK) + goto done; + + // If there is no GPU VA space for the GPU, ignore all faults in the VA + // space. This can happen if the GPU VA space has been destroyed since we + // unlocked the VA space in service_fault_batch. That means the fatal faults + // are stale, because unregistering the GPU VA space requires preempting the + // context and detaching all channels in that VA space. Restart fault + // servicing from the top. + gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); + if (!gpu_va_space) + goto done; + + // Re-parse the new faults + batch_context->num_invalid_prefetch_faults = 0; + batch_context->num_duplicate_faults = 0; + batch_context->num_replays = 0; + batch_context->fatal_va_space = NULL; + batch_context->has_throttled_faults = false; + + status = fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_ALL); + if (status != NV_OK) + goto done; + + // No more faults left. Either the previously-seen fatal entry was stale, or + // RM killed the context underneath us. + if (batch_context->num_cached_faults == 0) + goto done; + + ++batch_context->batch_id; + + status = preprocess_fault_batch(gpu, batch_context); + if (status != NV_OK) { + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + // Another flush happened due to stale faults or a context-fatal + // error. The previously-seen fatal fault might not exist anymore, + // so restart fault servicing from the top. + status = NV_OK; + } + + goto done; + } + + // Search for the target VA space + for (i = 0; i < batch_context->num_coalesced_faults; i++) { + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + UVM_ASSERT(current_entry->va_space); + if (current_entry->va_space == va_space) + break; + } + + while (i < batch_context->num_coalesced_faults) { + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + + if (current_entry->va_space != va_space) + break; + + // service_fault_batch_dispatch() doesn't expect unserviceable faults. + // Just cancel them directly. + if (current_entry->is_fatal) { + status = cancel_fault_precise_va(gpu, current_entry, UVM_FAULT_CANCEL_VA_MODE_ALL); + if (status != NV_OK) + break; + + ++i; + } + else { + uvm_ats_fault_invalidate_t *ats_invalidate = &gpu->parent->fault_buffer_info.replayable.ats_invalidate; + NvU32 block_faults; + + ats_invalidate->tlb_batch_pending = false; + uvm_hmm_service_context_init(service_context); + + // Service all the faults that we can. We only really need to search + // for fatal faults, but attempting to service all is the easiest + // way to do that. + status = service_fault_batch_dispatch(va_space, gpu_va_space, batch_context, i, &block_faults, false); + if (status != NV_OK) { + // TODO: Bug 3900733: clean up locking in service_fault_batch(). + // We need to drop lock and retry. That means flushing and + // starting over. + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) + status = NV_OK; + + break; + } + + // Invalidate TLBs before cancel to ensure that fatal faults don't + // get stuck in HW behind non-fatal faults to the same line. + status = uvm_ats_invalidate_tlbs(gpu_va_space, ats_invalidate, &batch_context->tracker); + if (status != NV_OK) + break; + + while (block_faults-- > 0) { + current_entry = batch_context->ordered_fault_cache[i]; + if (current_entry->is_fatal) { + status = cancel_fault_precise_va(gpu, current_entry, current_entry->replayable.cancel_va_mode); + if (status != NV_OK) + break; + } + + ++i; + } + } + } + +done: + uvm_va_space_up_read(va_space); + uvm_va_space_mm_release_unlock(va_space, mm); + + if (status == NV_OK) { + // There are two reasons to flush the fault buffer here. + // + // 1) Functional. We need to replay both the serviced non-fatal faults + // and the skipped faults in other VA spaces. The former need to be + // restarted and the latter need to be replayed so the normal fault + // service mechanism can fetch and process them. + // + // 2) Performance. After cancelling the fatal faults, a flush removes + // any potential duplicated fault that may have been added while + // processing the faults in this batch. This flush also avoids doing + // unnecessary processing after the fatal faults have been cancelled, + // so all the rest are unlikely to remain after a replay because the + // context is probably in the process of dying. + status = fault_buffer_flush_locked(gpu, + UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, + UVM_FAULT_REPLAY_TYPE_START, + batch_context); + } + + return status; +} // Scan the ordered view of faults and group them by different va_blocks // (managed faults) and service faults for each va_block, in batch. // Service non-managed faults one at a time as they are encountered during the // scan. // -// This function returns NV_WARN_MORE_PROCESSING_REQUIRED if the fault buffer -// was flushed because the needs_fault_buffer_flush flag was set on some GPU VA -// space +// Fatal faults are marked for later processing by the caller. static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, fault_service_mode_t service_mode, uvm_fault_service_batch_context_t *batch_context) @@ -1960,7 +2153,7 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, UVM_ASSERT(gpu->parent->replayable_faults_supported); - ats_invalidate->write_faults_in_batch = false; + ats_invalidate->tlb_batch_pending = false; uvm_hmm_service_context_init(service_context); for (i = 0; i < batch_context->num_coalesced_faults;) { @@ -1995,38 +2188,25 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, va_block_context->mm = mm; uvm_va_space_down_read(va_space); - gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); - if (uvm_processor_mask_test_and_clear_atomic(&va_space->needs_fault_buffer_flush, gpu->id)) { - status = fault_buffer_flush_locked(gpu, - UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, - UVM_FAULT_REPLAY_TYPE_START, - batch_context); - if (status == NV_OK) - status = NV_WARN_MORE_PROCESSING_REQUIRED; - - break; - } - - // The case where there is no valid GPU VA space for the GPU in this - // VA space is handled next } // Some faults could be already fatal if they cannot be handled by // the UVM driver if (current_entry->is_fatal) { ++i; - batch_context->has_fatal_faults = true; + if (!batch_context->fatal_va_space) + batch_context->fatal_va_space = va_space; + utlb->has_fatal_faults = true; UVM_ASSERT(utlb->num_pending_faults > 0); continue; } - if (!uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, gpu->parent->id)) { + if (!gpu_va_space) { // If there is no GPU VA space for the GPU, ignore the fault. This // can happen if a GPU VA space is destroyed without explicitly - // freeing all memory ranges (destroying the VA range triggers a - // flush of the fault buffer) and there are stale entries in the + // freeing all memory ranges and there are stale entries in the // buffer that got fixed by the servicing in a previous batch. ++i; continue; @@ -2044,15 +2224,17 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, uvm_va_space_mm_release_unlock(va_space, mm); mm = NULL; va_space = NULL; + status = NV_OK; continue; } + if (status != NV_OK) goto fail; i += block_faults; // Don't issue replays in cancel mode - if (replay_per_va_block && !batch_context->has_fatal_faults) { + if (replay_per_va_block && !batch_context->fatal_va_space) { status = push_replay_on_gpu(gpu, UVM_FAULT_REPLAY_TYPE_START, batch_context); if (status != NV_OK) goto fail; @@ -2064,8 +2246,6 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, } } - // Only clobber status if invalidate_status != NV_OK, since status may also - // contain NV_WARN_MORE_PROCESSING_REQUIRED. if (va_space != NULL) { NV_STATUS invalidate_status = uvm_ats_invalidate_tlbs(gpu_va_space, ats_invalidate, &batch_context->tracker); if (invalidate_status != NV_OK) @@ -2273,77 +2453,48 @@ static NvU32 is_fatal_fault_in_buffer(uvm_fault_service_batch_context_t *batch_c return false; } -typedef enum -{ - // Only cancel faults flagged as fatal - FAULT_CANCEL_MODE_FATAL, - - // Cancel all faults in the batch unconditionally - FAULT_CANCEL_MODE_ALL, -} fault_cancel_mode_t; - -// Cancel faults in the given fault service batch context. The function provides -// two different modes depending on the value of cancel_mode: -// - If cancel_mode == FAULT_CANCEL_MODE_FATAL, only faults flagged as fatal -// will be cancelled. In this case, the reason reported to tools is the one -// contained in the fault entry itself. -// - If cancel_mode == FAULT_CANCEL_MODE_ALL, all faults will be cancelled -// unconditionally. In this case, the reason reported to tools for non-fatal -// faults is the one passed to this function. -static NV_STATUS cancel_faults_precise_va(uvm_gpu_t *gpu, - uvm_fault_service_batch_context_t *batch_context, - fault_cancel_mode_t cancel_mode, - UvmEventFatalReason reason) +// Cancel all faults in the given fault service batch context, even those not +// marked as fatal. +static NV_STATUS cancel_faults_all(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + UvmEventFatalReason reason) { NV_STATUS status = NV_OK; NV_STATUS fault_status; - uvm_va_space_t *va_space = NULL; - NvU32 i; + NvU32 i = 0; UVM_ASSERT(gpu->parent->fault_cancel_va_supported); - if (cancel_mode == FAULT_CANCEL_MODE_ALL) - UVM_ASSERT(reason != UvmEventFatalReasonInvalid); + UVM_ASSERT(reason != UvmEventFatalReasonInvalid); - for (i = 0; i < batch_context->num_coalesced_faults; ++i) { + while (i < batch_context->num_coalesced_faults && status == NV_OK) { uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + uvm_va_space_t *va_space = current_entry->va_space; + bool skip_va_space; - UVM_ASSERT(current_entry->va_space); + UVM_ASSERT(va_space); - if (current_entry->va_space != va_space) { - // Fault on a different va_space, drop the lock of the old one... - if (va_space != NULL) - uvm_va_space_up_read(va_space); + uvm_va_space_down_read(va_space); - va_space = current_entry->va_space; + // If there is no GPU VA space for the GPU, ignore all faults in + // that VA space. This can happen if the GPU VA space has been + // destroyed since we unlocked the VA space in service_fault_batch. + // Ignoring the fault avoids targetting a PDB that might have been + // reused by another process. + skip_va_space = !uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); - // ... and take the lock of the new one - uvm_va_space_down_read(va_space); - - // We don't need to check whether a buffer flush is required - // (due to VA range destruction). - // - For cancel_mode == FAULT_CANCEL_MODE_FATAL, once a fault is - // flagged as fatal we need to cancel it, even if its VA range no - // longer exists. - // - For cancel_mode == FAULT_CANCEL_MODE_ALL we don't care about - // any of this, we just want to trigger RC in RM. - } + for (; + i < batch_context->num_coalesced_faults && current_entry->va_space == va_space; + current_entry = batch_context->ordered_fault_cache[++i]) { + uvm_fault_cancel_va_mode_t cancel_va_mode; - if (!uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, gpu->parent->id)) { - // If there is no GPU VA space for the GPU, ignore the fault. - // This can happen if the GPU VA did not exist in - // service_fault_batch(), or it was destroyed since then. - // This is to avoid targetting a PDB that might have been reused - // by another process. - continue; - } - - // Cancel the fault - if (cancel_mode == FAULT_CANCEL_MODE_ALL || current_entry->is_fatal) { - uvm_fault_cancel_va_mode_t cancel_va_mode = current_entry->replayable.cancel_va_mode; + if (skip_va_space) + continue; - // If cancelling unconditionally and the fault was not fatal, - // set the cancel reason passed to this function - if (!current_entry->is_fatal) { + if (current_entry->is_fatal) { + UVM_ASSERT(current_entry->fatal_reason != UvmEventFatalReasonInvalid); + cancel_va_mode = current_entry->replayable.cancel_va_mode; + } + else { current_entry->fatal_reason = reason; cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; } @@ -2352,17 +2503,13 @@ static NV_STATUS cancel_faults_precise_va(uvm_gpu_t *gpu, if (status != NV_OK) break; } - } - if (va_space != NULL) uvm_va_space_up_read(va_space); + } - // After cancelling the fatal faults, the fault buffer is flushed to remove - // any potential duplicated fault that may have been added while processing - // the faults in this batch. This flush also avoids doing unnecessary - // processing after the fatal faults have been cancelled, so all the rest - // are unlikely to remain after a replay because the context is probably in - // the process of dying. + // Because each cancel itself triggers a replay, there may be a large number + // of new duplicated faults in the buffer after cancelling all the known + // ones. Flushing the buffer discards them to avoid unnecessary processing. fault_status = fault_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START, @@ -2410,12 +2557,12 @@ static void cancel_fault_batch(uvm_gpu_t *gpu, uvm_fault_service_batch_context_t *batch_context, UvmEventFatalReason reason) { - if (gpu->parent->fault_cancel_va_supported) { - cancel_faults_precise_va(gpu, batch_context, FAULT_CANCEL_MODE_ALL, reason); - return; - } - - cancel_fault_batch_tlb(gpu, batch_context, reason); + // Return code is ignored since we're on a global error path and wouldn't be + // able to recover anyway. + if (gpu->parent->fault_cancel_va_supported) + cancel_faults_all(gpu, batch_context, reason); + else + cancel_fault_batch_tlb(gpu, batch_context, reason); } @@ -2502,7 +2649,7 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat batch_context->num_invalid_prefetch_faults = 0; batch_context->num_replays = 0; - batch_context->has_fatal_faults = false; + batch_context->fatal_va_space = NULL; batch_context->has_throttled_faults = false; // 5) Fetch all faults from buffer @@ -2549,9 +2696,6 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat // 8) Service all non-fatal faults and mark all non-serviceable faults // as fatal status = service_fault_batch(gpu, FAULT_SERVICE_MODE_CANCEL, batch_context); - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) - continue; - UVM_ASSERT(batch_context->num_replays == 0); if (status == NV_ERR_NO_MEMORY) continue; @@ -2559,7 +2703,7 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat break; // No more fatal faults left, we are done - if (!batch_context->has_fatal_faults) + if (!batch_context->fatal_va_space) break; // 9) Search for uTLBs that contain fatal faults and meet the @@ -2581,13 +2725,9 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat static NV_STATUS cancel_faults_precise(uvm_gpu_t *gpu, uvm_fault_service_batch_context_t *batch_context) { - UVM_ASSERT(batch_context->has_fatal_faults); - if (gpu->parent->fault_cancel_va_supported) { - return cancel_faults_precise_va(gpu, - batch_context, - FAULT_CANCEL_MODE_FATAL, - UvmEventFatalReasonInvalid); - } + UVM_ASSERT(batch_context->fatal_va_space); + if (gpu->parent->fault_cancel_va_supported) + return service_fault_batch_for_cancel(gpu, batch_context); return cancel_faults_precise_tlb(gpu, batch_context); } @@ -2643,7 +2783,7 @@ void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu) batch_context->num_invalid_prefetch_faults = 0; batch_context->num_duplicate_faults = 0; batch_context->num_replays = 0; - batch_context->has_fatal_faults = false; + batch_context->fatal_va_space = NULL; batch_context->has_throttled_faults = false; status = fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_BATCH_READY); @@ -2671,9 +2811,6 @@ void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu) // was flushed num_replays += batch_context->num_replays; - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) - continue; - enable_disable_prefetch_faults(gpu->parent, batch_context); if (status != NV_OK) { @@ -2687,10 +2824,17 @@ void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu) break; } - if (batch_context->has_fatal_faults) { + if (batch_context->fatal_va_space) { status = uvm_tracker_wait(&batch_context->tracker); - if (status == NV_OK) + if (status == NV_OK) { status = cancel_faults_precise(gpu, batch_context); + if (status == NV_OK) { + // Cancel handling should've issued at least one replay + UVM_ASSERT(batch_context->num_replays > 0); + ++num_batches; + continue; + } + } break; } diff --git a/kernel-open/nvidia-uvm/uvm_hopper.c b/kernel-open/nvidia-uvm/uvm_hopper.c index 2ae803d2c..959b6beeb 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper.c +++ b/kernel-open/nvidia-uvm/uvm_hopper.c @@ -103,5 +103,7 @@ void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = true; } diff --git a/kernel-open/nvidia-uvm/uvm_hopper_mmu.c b/kernel-open/nvidia-uvm/uvm_hopper_mmu.c index 092a7e2ba..025343d25 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_hopper_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020-2022 NVIDIA Corporation + Copyright (c) 2020-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,6 +33,7 @@ #include "uvm_types.h" #include "uvm_global.h" +#include "uvm_common.h" #include "uvm_hal.h" #include "uvm_hal_types.h" #include "uvm_hopper_fault_buffer.h" @@ -42,6 +43,10 @@ #define MMU_BIG 0 #define MMU_SMALL 1 +// Used in pde_pcf(). +#define ATS_ALLOWED 0 +#define ATS_NOT_ALLOWED 1 + uvm_mmu_engine_type_t uvm_hal_hopper_mmu_engine_id_to_type(NvU16 mmu_engine_id) { if (mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_HOST0 && mmu_engine_id <= NV_PFAULT_MMU_ENG_ID_HOST44) @@ -260,7 +265,108 @@ static NvU64 poisoned_pte_hopper(void) return WRITE_HWCONST64(pte_bits, _MMU_VER3, PTE, PCF, PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD); } -static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, NvU32 depth) +typedef enum +{ + PDE_TYPE_SINGLE, + PDE_TYPE_DUAL_BIG, + PDE_TYPE_DUAL_SMALL, + PDE_TYPE_COUNT, +} pde_type_t; + +static const NvU8 valid_pcf[][2] = { { NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED } }; + +static const NvU8 invalid_pcf[][2] = { { NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED, + NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED } }; + +static const NvU8 va_base[] = { 56, 47, 38, 29, 21 }; + +static bool is_ats_range_valid(uvm_page_directory_t *dir, NvU32 child_index) +{ + NvU64 pde_base_va; + NvU64 min_va_upper; + NvU64 max_va_lower; + NvU32 index_in_dir; + + uvm_cpu_get_unaddressable_range(&max_va_lower, &min_va_upper); + + UVM_ASSERT(dir->depth < ARRAY_SIZE(va_base)); + + // We can use UVM_PAGE_SIZE_AGNOSTIC because page_size is only used in + // index_bits_hopper() for PTE table, i.e., depth 5+, which does not use a + // PDE PCF or an ATS_ALLOWED/NOT_ALLOWED setting. + UVM_ASSERT(child_index < (1ull << index_bits_hopper(dir->depth, UVM_PAGE_SIZE_AGNOSTIC))); + + pde_base_va = 0; + index_in_dir = child_index; + while (dir) { + pde_base_va += index_in_dir * (1ull << va_base[dir->depth]); + index_in_dir = dir->index_in_parent; + dir = dir->host_parent; + } + pde_base_va = (NvU64)((NvS64)(pde_base_va << (64 - num_va_bits_hopper())) >> (64 - num_va_bits_hopper())); + + if (pde_base_va < max_va_lower || pde_base_va >= min_va_upper) + return true; + + return false; +} + +// PDE Permission Control Flags +static NvU32 pde_pcf(bool valid, pde_type_t pde_type, uvm_page_directory_t *dir, NvU32 child_index) +{ + const NvU8 (*pcf)[2] = valid ? valid_pcf : invalid_pcf; + NvU8 depth = dir->depth; + + UVM_ASSERT(pde_type < PDE_TYPE_COUNT); + UVM_ASSERT(depth < 5); + + // On non-ATS systems, PDE PCF only sets the valid and volatile/cache bits. + if (!g_uvm_global.ats.enabled) + return pcf[pde_type][ATS_ALLOWED]; + + // We assume all supported ATS platforms use canonical form address. + // See comments in uvm_gpu.c:uvm_gpu_can_address() and in + // uvm_mmu.c:page_tree_ats_init(); + UVM_ASSERT(uvm_platform_uses_canonical_form_address()); + + // Hopper GPUs on ATS-enabled systems, perform a parallel lookup on both + // ATS and GMMU page tables. For managed memory we need to prevent this + // parallel lookup since we would not get any GPU fault if the CPU has + // a valid mapping. Also, for external ranges that are known to be + // mapped entirely on the GMMU page table we can skip the ATS lookup + // for performance reasons. Parallel ATS lookup is disabled in PDE1 + // (depth 3) and, therefore, it applies to the underlying 512MB VA + // range. + // + // UVM sets ATS_NOT_ALLOWED for all Hopper+ mappings on ATS systems. + // This is fine because CUDA ensures that all managed and external + // allocations are properly compartmentalized in 512MB-aligned VA + // regions. For cudaHostRegister CUDA cannot control the VA range, but + // we rely on ATS for those allocations so they can't choose the + // ATS_NOT_ALLOWED mode. + // TODO: Bug 3254055: Relax the NO_ATS setting from 512MB (pde1) range to + // PTEs. + // HW complies with the leaf PDE's ATS_ALLOWED/ATS_NOT_ALLOWED settings, + // enabling us to treat any upper-level PDE as a don't care as long as there + // are leaf PDEs for the entire upper-level PDE range. We assume PDE4 + // entries (depth == 0) are always ATS enabled, and the no_ats_range is in + // PDE3 or lower. + if (depth == 0 || (!valid && is_ats_range_valid(dir, child_index))) + return pcf[pde_type][ATS_ALLOWED]; + + return pcf[pde_type][ATS_NOT_ALLOWED]; +} + +static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -280,38 +386,17 @@ static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, NvU32 dep break; } - // PCF (permission control flags) 5:3 - // Hopper GPUs on ATS-enabled systems, perform a parallel lookup on both - // ATS and GMMU page tables. For managed memory we need to prevent this - // parallel lookup since we would not get any GPU fault if the CPU has - // a valid mapping. Also, for external ranges that are known to be - // mapped entirely on the GMMU page table we can skip the ATS lookup - // for performance reasons. Parallel ATS lookup is disabled in PDE1 - // (depth 3) and, therefore, it applies to the underlying 512MB VA - // range. - // - // UVM sets ATS_NOT_ALLOWED for all Hopper+ mappings on ATS systems. - // This is fine because CUDA ensures that all managed and external - // allocations are properly compartmentalized in 512MB-aligned VA - // regions. For cudaHostRegister CUDA cannot control the VA range, but - // we rely on ATS for those allocations so they can't choose the - // ATS_NOT_ALLOWED mode. - // - // TODO: Bug 3254055: Relax the NO_ATS setting from 512MB (pde1) range - // to PTEs. - if (depth == 3 && g_uvm_global.ats.enabled) - pde_bits |= HWCONST64(_MMU_VER3, PDE, PCF, VALID_UNCACHED_ATS_NOT_ALLOWED); - else - pde_bits |= HWCONST64(_MMU_VER3, PDE, PCF, VALID_UNCACHED_ATS_ALLOWED); - // address 51:12 pde_bits |= HWVALUE64(_MMU_VER3, PDE, ADDRESS, address); } + // PCF (permission control flags) 5:3 + pde_bits |= HWVALUE64(_MMU_VER3, PDE, PCF, pde_pcf(phys_alloc != NULL, PDE_TYPE_SINGLE, dir, child_index)); + return pde_bits; } -static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) +static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -330,17 +415,20 @@ static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) break; } - // PCF (permission control flags) 5:3 - pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, PCF_BIG, VALID_UNCACHED_ATS_NOT_ALLOWED); - // address 51:8 pde_bits |= HWVALUE64(_MMU_VER3, DUAL_PDE, ADDRESS_BIG, address); } + // PCF (permission control flags) 5:3 + pde_bits |= HWVALUE64(_MMU_VER3, + DUAL_PDE, + PCF_BIG, + pde_pcf(phys_alloc != NULL, PDE_TYPE_DUAL_BIG, dir, child_index)); + return pde_bits; } -static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) +static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -359,29 +447,40 @@ static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) break; } - // PCF (permission control flags) 69:67 [5:3] - pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, PCF_SMALL, VALID_UNCACHED_ATS_NOT_ALLOWED); - // address 115:76 [51:12] pde_bits |= HWVALUE64(_MMU_VER3, DUAL_PDE, ADDRESS_SMALL, address); } + + // PCF (permission control flags) 69:67 [5:3] + pde_bits |= HWVALUE64(_MMU_VER3, + DUAL_PDE, + PCF_SMALL, + pde_pcf(phys_alloc != NULL, PDE_TYPE_DUAL_SMALL, dir, child_index)); + return pde_bits; } -static void make_pde_hopper(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_hopper(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_hopper(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_hopper(dir->depth); + if (entry_count == 1) { - *entry_bits = single_pde_hopper(*phys_allocs, depth); + *entry_bits = single_pde_hopper(*phys_allocs, dir, child_index); } else if (entry_count == 2) { - entry_bits[MMU_BIG] = big_half_pde_hopper(phys_allocs[MMU_BIG]); - entry_bits[MMU_SMALL] = small_half_pde_hopper(phys_allocs[MMU_SMALL]); + entry_bits[MMU_BIG] = big_half_pde_hopper(phys_allocs[MMU_BIG], dir, child_index); + entry_bits[MMU_SMALL] = small_half_pde_hopper(phys_allocs[MMU_SMALL], dir, child_index); // This entry applies to the whole dual PDE but is stored in the lower - // bits + // bits. entry_bits[MMU_BIG] |= HWCONST64(_MMU_VER3, DUAL_PDE, IS_PTE, FALSE); } else { diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index e752eed83..94c224339 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -128,8 +128,9 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) // present if we see the callback. // // The callback was added in commit 0f0a327fa12cd55de5e7f8c05a70ac3d047f405e, -// v3.19 (2014-11-13). - #if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) +// v3.19 (2014-11-13) and renamed in commit 1af5a8109904. + #if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) || \ + defined(NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS) #define UVM_CAN_USE_MMU_NOTIFIERS() 1 #else #define UVM_CAN_USE_MMU_NOTIFIERS() 0 @@ -153,10 +154,6 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) #define VM_MIXEDMAP 0x00000000 #endif -#if !defined(MPOL_PREFERRED_MANY) -#define MPOL_PREFERRED_MANY 5 -#endif - // // printk.h already defined pr_fmt, so we have to redefine it so the pr_* // routines pick up our version diff --git a/kernel-open/nvidia-uvm/uvm_maxwell.c b/kernel-open/nvidia-uvm/uvm_maxwell.c index b6ccf3962..246dfb8e2 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -71,4 +71,6 @@ void uvm_hal_maxwell_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c b/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c index 4f3e05552..d2107844d 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -106,10 +106,16 @@ static NvU64 small_half_pde_maxwell(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_maxwell(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_maxwell(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { NvU64 pde_bits = 0; - UVM_ASSERT(depth == 0); + + UVM_ASSERT(dir); + UVM_ASSERT(dir->depth == 0); + pde_bits |= HWCONST64(_MMU, PDE, SIZE, FULL); pde_bits |= big_half_pde_maxwell(phys_allocs[MMU_BIG]) | small_half_pde_maxwell(phys_allocs[MMU_SMALL]); diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c index 44b5e857c..6b95e2038 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c @@ -672,14 +672,6 @@ static NV_STATUS nv_migrate_vma(struct migrate_vma *args, migrate_vma_state_t *s .finalize_and_map = uvm_migrate_vma_finalize_and_map_helper, }; - // WAR for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU TLB - // invalidates on read-only to read-write upgrades - // - // This code path isn't used on GH180 but we need to maintain consistent - // behaviour on systems that do. - if (!vma_is_anonymous(args->vma)) - return NV_WARN_NOTHING_TO_DO; - ret = migrate_vma(&uvm_migrate_vma_ops, args->vma, args->start, args->end, args->src, args->dst, state); if (ret < 0) return errno_to_nv_status(ret); @@ -693,24 +685,6 @@ static NV_STATUS nv_migrate_vma(struct migrate_vma *args, migrate_vma_state_t *s if (ret < 0) return errno_to_nv_status(ret); - // TODO: Bug 2419180: support file-backed pages in migrate_vma, when - // support for it is added to the Linux kernel - // - // A side-effect of migrate_vma_setup() is it calls mmu notifiers even if a - // page can't be migrated (eg. because it's a non-anonymous mapping). We - // need this side-effect for SMMU on GH180 to ensure any cached read-only - // entries are flushed from SMMU on permission upgrade. - // - // TODO: Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU TLB - // invalidates on read-only to read-write upgrades - // - // The above WAR doesn't work for HugeTLBfs mappings because - // migrate_vma_setup() will fail in that case. - if (!vma_is_anonymous(args->vma)) { - migrate_vma_finalize(args); - return NV_WARN_NOTHING_TO_DO; - } - uvm_migrate_vma_alloc_and_copy(args, state); if (state->status == NV_OK) { migrate_vma_pages(args); @@ -862,6 +836,17 @@ static NV_STATUS migrate_pageable_vma_region(struct vm_area_struct *vma, return NV_OK; } +NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + uvm_va_space_down_write(va_space); + va_space->test.skip_migrate_vma = params->skip; + uvm_va_space_up_write(va_space); + + return NV_OK; +} + static NV_STATUS migrate_pageable_vma(struct vm_area_struct *vma, unsigned long start, unsigned long outer, @@ -884,13 +869,12 @@ static NV_STATUS migrate_pageable_vma(struct vm_area_struct *vma, start = max(start, vma->vm_start); outer = min(outer, vma->vm_end); - // migrate_vma only supports anonymous VMAs. We check for those after - // calling migrate_vma_setup() to workaround Bug 4130089. We need to check - // for HugeTLB VMAs here because migrate_vma_setup() will return a fatal - // error for those. - // TODO: Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU TLB - // invalidates on read-only to read-write upgrades - if (is_vm_hugetlb_page(vma)) + if (va_space->test.skip_migrate_vma) + return NV_WARN_NOTHING_TO_DO; + + // TODO: Bug 2419180: support file-backed pages in migrate_vma, when + // support for it is added to the Linux kernel + if (!vma_is_anonymous(vma)) return NV_WARN_NOTHING_TO_DO; if (uvm_processor_mask_empty(&va_space->registered_gpus)) @@ -950,7 +934,9 @@ static NV_STATUS migrate_pageable(migrate_vma_state_t *state) bool touch = uvm_migrate_args->touch; uvm_populate_permissions_t populate_permissions = uvm_migrate_args->populate_permissions; - UVM_ASSERT(!vma_is_anonymous(vma) || uvm_processor_mask_empty(&va_space->registered_gpus)); + UVM_ASSERT(va_space->test.skip_migrate_vma || + !vma_is_anonymous(vma) || + uvm_processor_mask_empty(&va_space->registered_gpus)); // We can't use migrate_vma to move the pages as desired. Normally // this fallback path is supposed to populate the memory then inform diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h index 41c01b237..85956de46 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h @@ -51,7 +51,7 @@ typedef struct #if defined(CONFIG_MIGRATE_VMA_HELPER) #define UVM_MIGRATE_VMA_SUPPORTED 1 #else -#if defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MIGRATE_VMA_SETUP_PRESENT) +#if NV_IS_EXPORT_SYMBOL_PRESENT_migrate_vma_setup #define UVM_MIGRATE_VMA_SUPPORTED 1 #endif #endif @@ -218,6 +218,9 @@ NV_STATUS uvm_migrate_pageable(uvm_migrate_args_t *uvm_migrate_args); NV_STATUS uvm_migrate_pageable_init(void); void uvm_migrate_pageable_exit(void); + +NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp); + #else // UVM_MIGRATE_VMA_SUPPORTED static NV_STATUS uvm_migrate_pageable(uvm_migrate_args_t *uvm_migrate_args) @@ -251,6 +254,10 @@ static void uvm_migrate_pageable_exit(void) { } +static inline NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp) +{ + return NV_OK; +} #endif // UVM_MIGRATE_VMA_SUPPORTED #endif diff --git a/kernel-open/nvidia-uvm/uvm_mmu.c b/kernel-open/nvidia-uvm/uvm_mmu.c index 609337f08..6379fd2df 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_mmu.c @@ -323,37 +323,156 @@ static void uvm_mmu_page_table_cpu_memset_16(uvm_gpu_t *gpu, uvm_mmu_page_table_cpu_unmap(gpu, phys_alloc); } -static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_directory_t *dir, uvm_push_t *push) +static void pde_fill_cpu(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr) { - NvU64 clear_bits[2]; - uvm_mmu_mode_hal_t *hal = tree->hal; + NvU64 pde_data[2], entry_size; + NvU32 i; - if (dir->depth == tree->hal->page_table_depth(page_size)) { - *clear_bits = 0; // Invalid PTE + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + entry_size = tree->hal->entry_size(directory->depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + for (i = 0; i < pde_count; i++) { + tree->hal->make_pde(pde_data, phys_addr, directory, start_index + i); + + if (entry_size == sizeof(pde_data[0])) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, &directory->phys_alloc, start_index + i, pde_data[0], 1); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, &directory->phys_alloc, start_index + i, pde_data, 1); } - else { - // passing in NULL for the phys_allocs will mark the child entries as invalid - uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; - hal->make_pde(clear_bits, phys_allocs, dir->depth); +} + +static void pde_fill_gpu(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + NvU64 pde_data[2], entry_size; + uvm_gpu_address_t pde_entry_addr = uvm_mmu_gpu_address(tree->gpu, directory->phys_alloc.addr); + NvU32 max_inline_entries; + uvm_push_flag_t push_membar_flag = UVM_PUSH_FLAG_COUNT; + uvm_gpu_address_t inline_data_addr; + uvm_push_inline_data_t inline_data; + NvU32 entry_count, i, j; + + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); - // Make sure that using only clear_bits[0] will work - UVM_ASSERT(hal->entry_size(dir->depth) == sizeof(clear_bits[0]) || clear_bits[0] == clear_bits[1]); + entry_size = tree->hal->entry_size(directory->depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + max_inline_entries = UVM_PUSH_INLINE_DATA_MAX_SIZE / entry_size; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + + pde_entry_addr.address += start_index * entry_size; + + for (i = 0; i < pde_count;) { + // All but the first memory operation can be pipelined. We respect the + // caller's pipelining settings for the first push. + if (i != 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + entry_count = min(pde_count - i, max_inline_entries); + + // No membar is needed until the last memory operation. Otherwise, + // use caller's membar flag. + if ((i + entry_count) < pde_count) + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + else if (push_membar_flag != UVM_PUSH_FLAG_COUNT) + uvm_push_set_flag(push, push_membar_flag); + + uvm_push_inline_data_begin(push, &inline_data); + for (j = 0; j < entry_count; j++) { + tree->hal->make_pde(pde_data, phys_addr, directory, start_index + i + j); + uvm_push_inline_data_add(&inline_data, pde_data, entry_size); + } + inline_data_addr = uvm_push_inline_data_end(&inline_data); + + tree->gpu->parent->ce_hal->memcopy(push, pde_entry_addr, inline_data_addr, entry_count * entry_size); + + i += entry_count; + pde_entry_addr.address += entry_size * entry_count; } +} + +// pde_fill() populates pde_count PDE entries (starting at start_index) with +// the same mapping, i.e., with the same physical address (phys_addr). +// pde_fill() is optimized for pde_count == 1, which is the common case. +static void pde_fill(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, directory->depth, UVM_PAGE_SIZE_AGNOSTIC)); - // initialize the memory to a reasonable value - if (push) { - tree->gpu->parent->ce_hal->memset_8(push, - uvm_mmu_gpu_address(tree->gpu, dir->phys_alloc.addr), + if (push) + pde_fill_gpu(tree, directory, start_index, pde_count, phys_addr, push); + else + pde_fill_cpu(tree, directory, start_index, pde_count, phys_addr); +} + +static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_directory_t *dir, uvm_push_t *push) +{ + NvU32 entries_count = uvm_mmu_page_tree_entries(tree, dir->depth, page_size); + NvU8 max_pde_depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_AGNOSTIC) - 1; + + // Passing in NULL for the phys_allocs will mark the child entries as + // invalid. + uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; + + // Init with an invalid PTE or clean PDE. Only Maxwell PDEs can have more + // than 512 entries. In this case, we initialize them all with the same + // clean PDE. ATS systems may require clean PDEs with + // ATS_ALLOWED/ATS_NOT_ALLOWED bit settings based on the mapping VA. + // We only clean_bits to 0 at the lowest page table level (PTE table), i.e., + // when depth is greater than the max_pde_depth. + if ((dir->depth > max_pde_depth) || (entries_count > 512 && !g_uvm_global.ats.enabled)) { + NvU64 clear_bits[2]; + + // If it is not a PTE, make a clean PDE. + if (dir->depth != tree->hal->page_table_depth(page_size)) { + // make_pde() child index is zero/ignored, since it is only used in + // PDEs on ATS-enabled systems where pde_fill() is preferred. + tree->hal->make_pde(clear_bits, phys_allocs, dir, 0); + + // Make sure that using only clear_bits[0] will work. + UVM_ASSERT(tree->hal->entry_size(dir->depth) == sizeof(clear_bits[0]) || clear_bits[0] == clear_bits[1]); + } + else { + *clear_bits = 0; + } + + // Initialize the memory to a reasonable value. + if (push) { + tree->gpu->parent->ce_hal->memset_8(push, + uvm_mmu_gpu_address(tree->gpu, dir->phys_alloc.addr), + *clear_bits, + dir->phys_alloc.size); + } + else { + uvm_mmu_page_table_cpu_memset_8(tree->gpu, + &dir->phys_alloc, + 0, *clear_bits, - dir->phys_alloc.size); + dir->phys_alloc.size / sizeof(*clear_bits)); + } } else { - uvm_mmu_page_table_cpu_memset_8(tree->gpu, - &dir->phys_alloc, - 0, - *clear_bits, - dir->phys_alloc.size / sizeof(*clear_bits)); + pde_fill(tree, dir, 0, entries_count, phys_allocs, push); } + } static uvm_page_directory_t *allocate_directory(uvm_page_tree_t *tree, @@ -367,8 +486,10 @@ static uvm_page_directory_t *allocate_directory(uvm_page_tree_t *tree, NvLength phys_alloc_size = hal->allocation_size(depth, page_size); uvm_page_directory_t *dir; - // The page tree doesn't cache PTEs so space is not allocated for entries that are always PTEs. - // 2M PTEs may later become PDEs so pass UVM_PAGE_SIZE_AGNOSTIC, not page_size. + // The page tree doesn't cache PTEs so space is not allocated for entries + // that are always PTEs. + // 2M PTEs may later become PDEs so pass UVM_PAGE_SIZE_AGNOSTIC, not + // page_size. if (depth == hal->page_table_depth(UVM_PAGE_SIZE_AGNOSTIC)) entry_count = 0; else @@ -409,108 +530,6 @@ static inline NvU32 index_to_entry(uvm_mmu_mode_hal_t *hal, NvU32 entry_index, N return hal->entries_per_index(depth) * entry_index + hal->entry_offset(depth, page_size); } -static void pde_fill_cpu(uvm_page_tree_t *tree, - NvU32 depth, - uvm_mmu_page_table_alloc_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr) -{ - NvU64 pde_data[2], entry_size; - - UVM_ASSERT(uvm_mmu_use_cpu(tree)); - entry_size = tree->hal->entry_size(depth); - UVM_ASSERT(sizeof(pde_data) >= entry_size); - - tree->hal->make_pde(pde_data, phys_addr, depth); - - if (entry_size == sizeof(pde_data[0])) - uvm_mmu_page_table_cpu_memset_8(tree->gpu, directory, start_index, pde_data[0], pde_count); - else - uvm_mmu_page_table_cpu_memset_16(tree->gpu, directory, start_index, pde_data, pde_count); -} - -static void pde_fill_gpu(uvm_page_tree_t *tree, - NvU32 depth, - uvm_mmu_page_table_alloc_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr, - uvm_push_t *push) -{ - NvU64 pde_data[2], entry_size; - uvm_gpu_address_t pde_entry_addr = uvm_mmu_gpu_address(tree->gpu, directory->addr); - - UVM_ASSERT(!uvm_mmu_use_cpu(tree)); - - entry_size = tree->hal->entry_size(depth); - UVM_ASSERT(sizeof(pde_data) >= entry_size); - - tree->hal->make_pde(pde_data, phys_addr, depth); - pde_entry_addr.address += start_index * entry_size; - - if (entry_size == sizeof(pde_data[0])) { - tree->gpu->parent->ce_hal->memset_8(push, pde_entry_addr, pde_data[0], sizeof(pde_data[0]) * pde_count); - } - else { - NvU32 max_inline_entries = UVM_PUSH_INLINE_DATA_MAX_SIZE / sizeof(pde_data); - uvm_gpu_address_t inline_data_addr; - uvm_push_inline_data_t inline_data; - NvU32 membar_flag = 0; - NvU32 i; - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) - membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; - else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) - membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; - - for (i = 0; i < pde_count;) { - NvU32 j; - NvU32 entry_count = min(pde_count - i, max_inline_entries); - - uvm_push_inline_data_begin(push, &inline_data); - for (j = 0; j < entry_count; j++) - uvm_push_inline_data_add(&inline_data, pde_data, sizeof(pde_data)); - inline_data_addr = uvm_push_inline_data_end(&inline_data); - - // All but the first memcopy can be pipelined. We respect the - // caller's pipelining settings for the first push. - if (i != 0) - uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); - - // No membar is needed until the last copy. Otherwise, use - // caller's membar flag. - if (i + entry_count < pde_count) - uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - else if (membar_flag) - uvm_push_set_flag(push, membar_flag); - - tree->gpu->parent->ce_hal->memcopy(push, pde_entry_addr, inline_data_addr, entry_count * sizeof(pde_data)); - - i += entry_count; - pde_entry_addr.address += sizeof(pde_data) * entry_count; - } - } -} - -// pde_fill() populates pde_count PDE entries (starting at start_index) with -// the same mapping, i.e., with the same physical address (phys_addr). -static void pde_fill(uvm_page_tree_t *tree, - NvU32 depth, - uvm_mmu_page_table_alloc_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr, - uvm_push_t *push) -{ - UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, depth, UVM_PAGE_SIZE_AGNOSTIC)); - - if (push) - pde_fill_gpu(tree, depth, directory, start_index, pde_count, phys_addr, push); - else - pde_fill_cpu(tree, depth, directory, start_index, pde_count, phys_addr); -} - static uvm_page_directory_t *host_pde_write(uvm_page_directory_t *dir, uvm_page_directory_t *parent, NvU32 index_in_parent) @@ -540,7 +559,7 @@ static void pde_write(uvm_page_tree_t *tree, phys_allocs[i] = &entry->phys_alloc; } - pde_fill(tree, dir->depth, &dir->phys_alloc, entry_index, 1, phys_allocs, push); + pde_fill(tree, dir, entry_index, 1, phys_allocs, push); } static void host_pde_clear(uvm_page_tree_t *tree, uvm_page_directory_t *dir, NvU32 entry_index, NvU32 page_size) @@ -800,7 +819,6 @@ static void free_unused_directories(uvm_page_tree_t *tree, } } } - } static NV_STATUS allocate_page_table(uvm_page_tree_t *tree, NvU32 page_size, uvm_mmu_page_table_alloc_t *out) @@ -811,10 +829,93 @@ static NV_STATUS allocate_page_table(uvm_page_tree_t *tree, NvU32 page_size, uvm return phys_mem_allocate(tree, alloc_size, tree->location, UVM_PMM_ALLOC_FLAGS_EVICT, out); } +static bool page_tree_ats_init_required(uvm_page_tree_t *tree) +{ + // We have full control of the kernel page tables mappings, no ATS address + // aliases is expected. + if (tree->type == UVM_PAGE_TREE_TYPE_KERNEL) + return false; + + // Enable uvm_page_tree_init() from the page_tree test. + if (uvm_enable_builtin_tests && tree->gpu_va_space == NULL) + return false; + + if (!tree->gpu_va_space->ats.enabled) + return false; + + return tree->gpu->parent->no_ats_range_required; +} + +static NV_STATUS page_tree_ats_init(uvm_page_tree_t *tree) +{ + NV_STATUS status; + NvU64 min_va_upper, max_va_lower; + NvU32 page_size; + + if (!page_tree_ats_init_required(tree)) + return NV_OK; + + page_size = uvm_mmu_biggest_page_size(tree); + + uvm_cpu_get_unaddressable_range(&max_va_lower, &min_va_upper); + + // Potential violation of the UVM internal get/put_ptes contract. get_ptes() + // creates and initializes enough PTEs to populate all PDEs covering the + // no_ats_ranges. We store the no_ats_ranges in the tree, so they can be + // put_ptes()'ed on deinit(). It doesn't preclude the range to be used by a + // future get_ptes(), since we don't write to the PTEs (range->table) from + // the tree->no_ats_ranges. + // + // Lower half + status = uvm_page_tree_get_ptes(tree, + page_size, + max_va_lower, + page_size, + UVM_PMM_ALLOC_FLAGS_EVICT, + &tree->no_ats_ranges[0]); + if (status != NV_OK) + return status; + + UVM_ASSERT(tree->no_ats_ranges[0].entry_count == 1); + + if (uvm_platform_uses_canonical_form_address()) { + // Upper half + status = uvm_page_tree_get_ptes(tree, + page_size, + min_va_upper - page_size, + page_size, + UVM_PMM_ALLOC_FLAGS_EVICT, + &tree->no_ats_ranges[1]); + if (status != NV_OK) + return status; + + UVM_ASSERT(tree->no_ats_ranges[1].entry_count == 1); + } + + return NV_OK; +} + +static void page_tree_ats_deinit(uvm_page_tree_t *tree) +{ + size_t i; + + if (page_tree_ats_init_required(tree)) { + for (i = 0; i < ARRAY_SIZE(tree->no_ats_ranges); i++) { + if (tree->no_ats_ranges[i].entry_count) + uvm_page_tree_put_ptes(tree, &tree->no_ats_ranges[i]); + } + + memset(tree->no_ats_ranges, 0, sizeof(tree->no_ats_ranges)); + } +} + static void map_remap_deinit(uvm_page_tree_t *tree) { - if (tree->map_remap.pde0.size) - phys_mem_deallocate(tree, &tree->map_remap.pde0); + if (tree->map_remap.pde0) { + phys_mem_deallocate(tree, &tree->map_remap.pde0->phys_alloc); + uvm_kvfree(tree->map_remap.pde0); + tree->map_remap.pde0 = NULL; + } if (tree->map_remap.ptes_invalid_4k.size) phys_mem_deallocate(tree, &tree->map_remap.ptes_invalid_4k); @@ -839,10 +940,16 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // PDE1-depth(512M) PTE. We first map it to the pde0 directory, then we // return the PTE for the get_ptes()'s caller. if (tree->hal->page_sizes() & UVM_PAGE_SIZE_512M) { - status = allocate_page_table(tree, UVM_PAGE_SIZE_2M, &tree->map_remap.pde0); - if (status != NV_OK) + tree->map_remap.pde0 = allocate_directory(tree, + UVM_PAGE_SIZE_2M, + tree->hal->page_table_depth(UVM_PAGE_SIZE_2M), + UVM_PMM_ALLOC_FLAGS_EVICT); + if (tree->map_remap.pde0 == NULL) { + status = NV_ERR_NO_MEMORY; goto error; + } } + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "map remap init"); if (status != NV_OK) goto error; @@ -864,22 +971,23 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; NvU32 depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_4K) - 1; size_t index_4k = tree->hal->entry_offset(depth, UVM_PAGE_SIZE_4K); - - // pde0 depth equals UVM_PAGE_SIZE_2M. - NvU32 pde0_depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_2M); - NvU32 pde0_entries = tree->map_remap.pde0.size / tree->hal->entry_size(pde0_depth); + NvU32 pde0_entries = tree->map_remap.pde0->phys_alloc.size / tree->hal->entry_size(tree->map_remap.pde0->depth); // The big-page entry is NULL which makes it an invalid entry. phys_allocs[index_4k] = &tree->map_remap.ptes_invalid_4k; // By default CE operations include a MEMBAR_SYS. MEMBAR_GPU is // sufficient when pde0 is allocated in VIDMEM. - if (tree->map_remap.pde0.addr.aperture == UVM_APERTURE_VID) + if (tree->map_remap.pde0->phys_alloc.addr.aperture == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + // This is an orphan directory, make_pde() requires a directory to + // compute the VA. The UVM depth map_remap() operates on is not in the + // range make_pde() must operate. We only need to supply the fields used + // by make_pde() to not access invalid memory addresses. + pde_fill(tree, - pde0_depth, - &tree->map_remap.pde0, + tree->map_remap.pde0, 0, pde0_entries, (uvm_mmu_page_table_alloc_t **)&phys_allocs, @@ -1006,11 +1114,22 @@ NV_STATUS uvm_page_tree_init(uvm_gpu_t *gpu, return status; phys_mem_init(tree, UVM_PAGE_SIZE_AGNOSTIC, tree->root, &push); - return page_tree_end_and_wait(tree, &push); + + status = page_tree_end_and_wait(tree, &push); + if (status != NV_OK) + return status; + + status = page_tree_ats_init(tree); + if (status != NV_OK) + return status; + + return NV_OK; } void uvm_page_tree_deinit(uvm_page_tree_t *tree) { + page_tree_ats_deinit(tree); + UVM_ASSERT(tree->root->ref_count == 0); // Take the tree lock only to avoid assertions. It is not required for @@ -1249,7 +1368,6 @@ static NV_STATUS try_get_ptes(uvm_page_tree_t *tree, UVM_ASSERT(uvm_gpu_can_address_kernel(tree->gpu, start, size)); while (true) { - // index of the entry, for the first byte of the range, within its // containing directory NvU32 start_index; @@ -1281,7 +1399,8 @@ static NV_STATUS try_get_ptes(uvm_page_tree_t *tree, if (dir_cache[dir->depth] == NULL) { *cur_depth = dir->depth; - // Undo the changes to the tree so that the dir cache remains private to the thread + // Undo the changes to the tree so that the dir cache + // remains private to the thread. for (i = 0; i < used_count; i++) host_pde_clear(tree, dirs_used[i]->host_parent, dirs_used[i]->index_in_parent, page_size); @@ -1332,10 +1451,9 @@ static NV_STATUS map_remap(uvm_page_tree_t *tree, NvU64 start, NvLength size, uv if (uvm_page_table_range_aperture(range) == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); - phys_alloc[0] = &tree->map_remap.pde0; + phys_alloc[0] = &tree->map_remap.pde0->phys_alloc; pde_fill(tree, - range->table->depth, - &range->table->phys_alloc, + range->table, range->start_index, range->entry_count, (uvm_mmu_page_table_alloc_t **)&phys_alloc, @@ -1380,7 +1498,8 @@ NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, dir_cache)) == NV_ERR_MORE_PROCESSING_REQUIRED) { uvm_mutex_unlock(&tree->lock); - // try_get_ptes never needs depth 0, so store a directory at its parent's depth + // try_get_ptes never needs depth 0, so store a directory at its + // parent's depth. // TODO: Bug 1766655: Allocate everything below cur_depth instead of // retrying for every level. dir_cache[cur_depth] = allocate_directory(tree, page_size, cur_depth + 1, pmm_flags); @@ -1663,8 +1782,12 @@ NV_STATUS uvm_page_table_range_vec_init(uvm_page_tree_t *tree, range); if (status != NV_OK) { UVM_ERR_PRINT("Failed to get PTEs for subrange %zd [0x%llx, 0x%llx) size 0x%llx, part of [0x%llx, 0x%llx)\n", - i, range_start, range_start + range_size, range_size, - start, size); + i, + range_start, + range_start + range_size, + range_size, + start, + size); goto out; } } diff --git a/kernel-open/nvidia-uvm/uvm_mmu.h b/kernel-open/nvidia-uvm/uvm_mmu.h index 2f21b6ee7..4f53e3ffb 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.h +++ b/kernel-open/nvidia-uvm/uvm_mmu.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -215,11 +215,14 @@ struct uvm_mmu_mode_hal_struct // memory out-of-range error so we can immediately identify bad PTE usage. NvU64 (*poisoned_pte)(void); - // write a PDE bit-pattern to entry based on the data in entries (which may + // Write a PDE bit-pattern to entry based on the data in allocs (which may // point to two items for dual PDEs). - // any of allocs are allowed to be NULL, in which case they are to be - // treated as empty. - void (*make_pde)(void *entry, uvm_mmu_page_table_alloc_t **allocs, NvU32 depth); + // Any of allocs are allowed to be NULL, in which case they are to be + // treated as empty. make_pde() uses dir and child_index to compute the + // mapping PDE VA. On ATS-enabled systems, we may set PDE's PCF as + // ATS_ALLOWED or ATS_NOT_ALLOWED based on the mapping PDE VA, even for + // invalid/clean PDE entries. + void (*make_pde)(void *entry, uvm_mmu_page_table_alloc_t **allocs, uvm_page_directory_t *dir, NvU32 child_index); // size of an entry in a directory/table. Generally either 8 or 16 bytes. // (in the case of Pascal dual PDEs) @@ -229,7 +232,7 @@ struct uvm_mmu_mode_hal_struct NvU32 (*entries_per_index)(NvU32 depth); // For dual PDEs, this is ether 1 or 0, depending on the page size. - // This is used to index the host copy only. GPU PDEs are always entirely + // This is used to index the host copy only. GPU PDEs are always entirely // re-written using make_pde. NvLength (*entry_offset)(NvU32 depth, NvU32 page_size); @@ -295,11 +298,16 @@ struct uvm_page_tree_struct // PDE0 where all big-page entries are invalid, and small-page entries // point to ptes_invalid_4k. - // pde0 is only used on Pascal-Ampere, i.e., they have the same PDE - // format. - uvm_mmu_page_table_alloc_t pde0; + // pde0 is used on Pascal+ GPUs, i.e., they have the same PDE format. + uvm_page_directory_t *pde0; } map_remap; + // On ATS-enabled systems where the CPU VA width is smaller than the GPU VA + // width, the excess address range is set with ATS_NOT_ALLOWED on all leaf + // PDEs covering that range. We have at most 2 no_ats_ranges, due to + // canonical form address systems. + uvm_page_table_range_t no_ats_ranges[2]; + // Tracker for all GPU operations on the tree uvm_tracker_t tracker; }; @@ -365,21 +373,32 @@ void uvm_page_tree_deinit(uvm_page_tree_t *tree); // the same page size without an intervening put_ptes. To duplicate a subset of // an existing range or change the size of an existing range, use // uvm_page_table_range_get_upper() and/or uvm_page_table_range_shrink(). -NV_STATUS uvm_page_tree_get_ptes(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *range); +NV_STATUS uvm_page_tree_get_ptes(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + NvLength size, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *range); // Same as uvm_page_tree_get_ptes(), but doesn't synchronize the GPU work. // // All pending operations can be waited on with uvm_page_tree_wait(). -NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *range); +NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + NvLength size, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *range); // Returns a single-entry page table range for the addresses passed. // The size parameter must be a page size supported by this tree. // This is equivalent to calling uvm_page_tree_get_ptes() with size equal to // page_size. -NV_STATUS uvm_page_tree_get_entry(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *single); +NV_STATUS uvm_page_tree_get_entry(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *single); // For a single-entry page table range, write the PDE (which could be a dual // PDE) to the GPU. @@ -478,8 +497,8 @@ NV_STATUS uvm_page_table_range_vec_create(uvm_page_tree_t *tree, // new_range_vec will contain the upper portion of range_vec, starting at // new_end + 1. // -// new_end + 1 is required to be within the address range of range_vec and be aligned to -// range_vec's page_size. +// new_end + 1 is required to be within the address range of range_vec and be +// aligned to range_vec's page_size. // // On failure, the original range vector is left unmodified. NV_STATUS uvm_page_table_range_vec_split_upper(uvm_page_table_range_vec_t *range_vec, @@ -501,18 +520,22 @@ void uvm_page_table_range_vec_destroy(uvm_page_table_range_vec_t *range_vec); // for each offset. // The caller_data pointer is what the caller passed in as caller_data to // uvm_page_table_range_vec_write_ptes(). -typedef NvU64 (*uvm_page_table_range_pte_maker_t)(uvm_page_table_range_vec_t *range_vec, NvU64 offset, - void *caller_data); +typedef NvU64 (*uvm_page_table_range_pte_maker_t)(uvm_page_table_range_vec_t *range_vec, + NvU64 offset, + void *caller_data); -// Write all PTEs covered by the range vector using the given PTE making function. +// Write all PTEs covered by the range vector using the given PTE making +// function. // // After writing all the PTEs a TLB invalidate operation is performed including // the passed in tlb_membar. // // See comments about uvm_page_table_range_pte_maker_t for details about the // PTE making callback. -NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar, - uvm_page_table_range_pte_maker_t pte_maker, void *caller_data); +NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data); // Set all PTEs covered by the range vector to an empty PTE // @@ -636,8 +659,9 @@ static NvU64 uvm_page_table_range_size(uvm_page_table_range_t *range) // Get the physical address of the entry at entry_index within the range // (counted from range->start_index). -static uvm_gpu_phys_address_t uvm_page_table_range_entry_address(uvm_page_tree_t *tree, uvm_page_table_range_t *range, - size_t entry_index) +static uvm_gpu_phys_address_t uvm_page_table_range_entry_address(uvm_page_tree_t *tree, + uvm_page_table_range_t *range, + size_t entry_index) { NvU32 entry_size = uvm_mmu_pte_size(tree, range->page_size); uvm_gpu_phys_address_t entry = range->table->phys_alloc.addr; diff --git a/kernel-open/nvidia-uvm/uvm_page_tree_test.c b/kernel-open/nvidia-uvm/uvm_page_tree_test.c index a5710e582..782ac5113 100644 --- a/kernel-open/nvidia-uvm/uvm_page_tree_test.c +++ b/kernel-open/nvidia-uvm/uvm_page_tree_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -146,9 +146,15 @@ static void fake_tlb_invals_disable(void) g_fake_tlb_invals_tracking_enabled = false; } -// Fake TLB invalidate VA that just saves off the parameters so that they can be verified later -static void fake_tlb_invalidate_va(uvm_push_t *push, uvm_gpu_phys_address_t pdb, - NvU32 depth, NvU64 base, NvU64 size, NvU32 page_size, uvm_membar_t membar) +// Fake TLB invalidate VA that just saves off the parameters so that they can be +// verified later. +static void fake_tlb_invalidate_va(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + NvU32 depth, + NvU64 base, + NvU64 size, + NvU32 page_size, + uvm_membar_t membar) { if (!g_fake_tlb_invals_tracking_enabled) return; @@ -210,8 +216,8 @@ static bool assert_and_reset_last_invalidate(NvU32 expected_depth, bool expected } if ((g_last_fake_inval->membar == UVM_MEMBAR_NONE) == expected_membar) { UVM_TEST_PRINT("Expected %s membar, got %s instead\n", - expected_membar ? "a" : "no", - uvm_membar_string(g_last_fake_inval->membar)); + expected_membar ? "a" : "no", + uvm_membar_string(g_last_fake_inval->membar)); result = false; } @@ -230,7 +236,8 @@ static bool assert_last_invalidate_all(NvU32 expected_depth, bool expected_memba } if (g_last_fake_inval->base != 0 || g_last_fake_inval->size != -1) { UVM_TEST_PRINT("Expected invalidate all but got range [0x%llx, 0x%llx) instead\n", - g_last_fake_inval->base, g_last_fake_inval->base + g_last_fake_inval->size); + g_last_fake_inval->base, + g_last_fake_inval->base + g_last_fake_inval->size); return false; } if (g_last_fake_inval->depth != expected_depth) { @@ -247,15 +254,16 @@ static bool assert_invalidate_range_specific(fake_tlb_invalidate_t *inval, UVM_ASSERT(g_fake_tlb_invals_tracking_enabled); if (g_fake_invals_count == 0) { - UVM_TEST_PRINT("Expected an invalidate for range [0x%llx, 0x%llx), but got none\n", - base, base + size); + UVM_TEST_PRINT("Expected an invalidate for range [0x%llx, 0x%llx), but got none\n", base, base + size); return false; } if ((inval->base != base || inval->size != size) && inval->base != 0 && inval->size != -1) { UVM_TEST_PRINT("Expected invalidate range [0x%llx, 0x%llx), but got range [0x%llx, 0x%llx) instead\n", - base, base + size, - inval->base, inval->base + inval->size); + base, + base + size, + inval->base, + inval->base + inval->size); return false; } if (inval->depth != expected_depth) { @@ -270,7 +278,13 @@ static bool assert_invalidate_range_specific(fake_tlb_invalidate_t *inval, return true; } -static bool assert_invalidate_range(NvU64 base, NvU64 size, NvU32 page_size, bool allow_inval_all, NvU32 range_depth, NvU32 all_depth, bool expected_membar) +static bool assert_invalidate_range(NvU64 base, + NvU64 size, + NvU32 page_size, + bool allow_inval_all, + NvU32 range_depth, + NvU32 all_depth, + bool expected_membar) { NvU32 i; @@ -488,7 +502,6 @@ static NV_STATUS alloc_adjacent_pde_64k_memory(uvm_gpu_t *gpu) return NV_OK; } - static NV_STATUS alloc_nearby_pde_64k_memory(uvm_gpu_t *gpu) { uvm_page_tree_t tree; @@ -842,6 +855,7 @@ static NV_STATUS get_two_free_apart(uvm_gpu_t *gpu) TEST_CHECK_RET(range2.entry_count == 256); TEST_CHECK_RET(range2.table->ref_count == 512); TEST_CHECK_RET(range1.table == range2.table); + // 4k page is second entry in a dual PDE TEST_CHECK_RET(range1.table == tree.root->entries[0]->entries[0]->entries[0]->entries[1]); TEST_CHECK_RET(range1.start_index == 256); @@ -871,6 +885,7 @@ static NV_STATUS get_overlapping_dual_pdes(uvm_gpu_t *gpu) MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, size, size, &range64k), NV_OK); TEST_CHECK_RET(range64k.entry_count == 16); TEST_CHECK_RET(range64k.table->ref_count == 16); + // 4k page is second entry in a dual PDE TEST_CHECK_RET(range64k.table == tree.root->entries[0]->entries[0]->entries[0]->entries[0]); TEST_CHECK_RET(range64k.start_index == 16); @@ -1030,10 +1045,13 @@ static NV_STATUS test_tlb_invalidates(uvm_gpu_t *gpu) // Depth 4 NvU64 extent_pte = UVM_PAGE_SIZE_2M; + // Depth 3 NvU64 extent_pde0 = extent_pte * (1ull << 8); + // Depth 2 NvU64 extent_pde1 = extent_pde0 * (1ull << 9); + // Depth 1 NvU64 extent_pde2 = extent_pde1 * (1ull << 9); @@ -1081,7 +1099,11 @@ static NV_STATUS test_tlb_invalidates(uvm_gpu_t *gpu) return status; } -static NV_STATUS test_tlb_batch_invalidates_case(uvm_page_tree_t *tree, NvU64 base, NvU64 size, NvU32 min_page_size, NvU32 max_page_size) +static NV_STATUS test_tlb_batch_invalidates_case(uvm_page_tree_t *tree, + NvU64 base, + NvU64 size, + NvU32 min_page_size, + NvU32 max_page_size) { NV_STATUS status = NV_OK; uvm_push_t push; @@ -1205,7 +1227,11 @@ static bool assert_range_vec_ptes(uvm_page_table_range_vec_t *range_vec, bool ex NvU64 expected_pte = expecting_cleared ? 0 : range_vec->size + offset; if (*pte != expected_pte) { UVM_TEST_PRINT("PTE is 0x%llx instead of 0x%llx for offset 0x%llx within range [0x%llx, 0x%llx)\n", - *pte, expected_pte, offset, range_vec->start, range_vec->size); + *pte, + expected_pte, + offset, + range_vec->start, + range_vec->size); return false; } offset += range_vec->page_size; @@ -1226,7 +1252,11 @@ static NV_STATUS test_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec TEST_CHECK_RET(data.status == NV_OK); TEST_CHECK_RET(data.count == range_vec->size / range_vec->page_size); TEST_CHECK_RET(assert_invalidate_range_specific(g_last_fake_inval, - range_vec->start, range_vec->size, range_vec->page_size, page_table_depth, membar != UVM_MEMBAR_NONE)); + range_vec->start, + range_vec->size, + range_vec->page_size, + page_table_depth, + membar != UVM_MEMBAR_NONE)); TEST_CHECK_RET(assert_range_vec_ptes(range_vec, false)); fake_tlb_invals_disable(); @@ -1249,7 +1279,11 @@ static NV_STATUS test_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_vec return NV_OK; } -static NV_STATUS test_range_vec_create(uvm_page_tree_t *tree, NvU64 start, NvU64 size, NvU32 page_size, uvm_page_table_range_vec_t **range_vec_out) +static NV_STATUS test_range_vec_create(uvm_page_tree_t *tree, + NvU64 start, + NvU64 size, + NvU32 page_size, + uvm_page_table_range_vec_t **range_vec_out) { uvm_page_table_range_vec_t *range_vec; uvm_pmm_alloc_flags_t pmm_flags = UVM_PMM_ALLOC_FLAGS_EVICT; @@ -1544,25 +1578,28 @@ static NV_STATUS entry_test_maxwell(uvm_gpu_t *gpu) uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); uvm_mmu_mode_hal_t *hal; + uvm_page_directory_t dir; NvU32 i, j, big_page_size, page_size; + dir.depth = 0; + for (i = 0; i < ARRAY_SIZE(big_page_sizes); i++) { big_page_size = big_page_sizes[i]; hal = gpu->parent->arch_hal->mmu_mode_hal(big_page_size); memset(phys_allocs, 0, sizeof(phys_allocs)); - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x0L); phys_allocs[0] = &alloc_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x1BBBBBBD99999992LL); phys_allocs[0] = &alloc_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x9999999E1BBBBBB1LL); for (j = 0; j <= 2; j++) { @@ -1632,38 +1669,47 @@ static NV_STATUS entry_test_pascal(uvm_gpu_t *gpu, entry_test_page_size_func ent uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); + uvm_page_directory_t dir; + // big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999900LL); uvm_mmu_page_table_alloc_t alloc_big_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBBB00LL); uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + dir.index_in_parent = 0; + dir.host_parent = NULL; + dir.depth = 0; + // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0); memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); + dir.depth = 0; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999990C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB0A); // Dual PDEs phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999999C && pde_bits[1] == 0x1BBBBBB0A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 3); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBBBA && pde_bits[1] == 0x3999999999990C); // uncached, i.e., the sysmem data is not cached in GPU's L2 cache. Clear @@ -1719,6 +1765,7 @@ static NV_STATUS entry_test_volta(uvm_gpu_t *gpu, entry_test_page_size_func entr uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); + uvm_page_directory_t dir; // big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999900LL); @@ -1726,37 +1773,45 @@ static NV_STATUS entry_test_volta(uvm_gpu_t *gpu, entry_test_page_size_func entr uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + dir.index_in_parent = 0; + dir.host_parent = NULL; + dir.depth = 0; + // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0); memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); + dir.depth = 0; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999990C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB0A); // Dual PDEs phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999999C && pde_bits[1] == 0x1BBBBBB0A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 3); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBBBA && pde_bits[1] == 0x3999999999990C); // NO_ATS PDE1 (depth 2) phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 2); + dir.depth = 2; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); if (g_uvm_global.ats.enabled) TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB2A); else @@ -1791,104 +1846,203 @@ static NV_STATUS entry_test_ampere(uvm_gpu_t *gpu, entry_test_page_size_func ent static NV_STATUS entry_test_hopper(uvm_gpu_t *gpu, entry_test_page_size_func entry_test_page_size) { + NV_STATUS status = NV_OK; NvU32 page_sizes[MAX_NUM_PAGE_SIZES]; NvU64 pde_bits[2]; + uvm_page_directory_t *dirs[5]; size_t i, num_page_sizes; uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0xBBBBBBB000LL); - // big versions have [11:8] set as well to test the page table merging + // Big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999999900LL); uvm_mmu_page_table_alloc_t alloc_big_vid = fake_table_alloc(UVM_APERTURE_VID, 0xBBBBBBBB00LL); uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); - // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0); + memset(dirs, 0, sizeof(dirs)); + // Fake directory tree. + for (i = 0; i < ARRAY_SIZE(dirs); i++) { + dirs[i] = uvm_kvmalloc_zero(sizeof(uvm_page_directory_t) + sizeof(dirs[i]->entries[0]) * 512); + TEST_CHECK_GOTO(dirs[i] != NULL, cleanup); + + dirs[i]->depth = i; + dirs[i]->index_in_parent = 0; + + if (i == 0) + dirs[i]->host_parent = NULL; + else + dirs[i]->host_parent = dirs[i - 1]; + } + + // Make sure cleared PDEs work as expected. + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0, cleanup); // Cleared PDEs work as expected for big and small PDEs. memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0 && pde_bits[1] == 0, cleanup); // Sys and vidmem PDEs, uncached ATS allowed. phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0x999999999900C); + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBB00A); + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBB00A, cleanup); - // Dual PDEs, uncached. + // Dual PDEs, uncached. We don't use child_dir in the depth 4 checks because + // our policy decides the PDE's PCF without using it. phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0x999999999991C && pde_bits[1] == 0xBBBBBBB01A); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + if (g_uvm_global.ats.enabled) + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999991C && pde_bits[1] == 0xBBBBBBB01A, cleanup); + else + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999990C && pde_bits[1] == 0xBBBBBBB00A, cleanup); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBBB1A && pde_bits[1] == 0x999999999901C); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + if (g_uvm_global.ats.enabled) + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBBB1A && pde_bits[1] == 0x999999999901C, cleanup); + else + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBBB0A && pde_bits[1] == 0x999999999900C, cleanup); + + // We only need to test make_pde() on ATS when the CPU VA width < GPU's. + if (g_uvm_global.ats.enabled && uvm_cpu_num_va_bits() < hal->num_va_bits()) { + phys_allocs[0] = &alloc_sys; + + dirs[1]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 1; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 1); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 2; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 2); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 511; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 511); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[1]->index_in_parent = 1; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 1); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 509; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 509); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 510; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 510); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + phys_allocs[0] = NULL; + + dirs[1]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + + dirs[2]->index_in_parent = 2; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 2); + TEST_CHECK_GOTO(pde_bits[0] == 0x10, cleanup); + + dirs[1]->index_in_parent = 1; + dirs[2]->index_in_parent = 509; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 509); + TEST_CHECK_GOTO(pde_bits[0] == 0x10, cleanup); + + dirs[2]->index_in_parent = 510; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 510); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + } // uncached, i.e., the sysmem data is not cached in GPU's L2 cache, and // access counters disabled. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == 0x999999999968D); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == 0x999999999968D, + cleanup); // change to cached. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_CACHED | UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == - 0x9999999999685); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_CACHED | UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == + 0x9999999999685, + cleanup); // enable access counters. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999605); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999605, + cleanup); // remove atomic - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999645); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999645, + cleanup); // read only - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999665); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999665, + cleanup); // local video - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_VID, - 0xBBBBBBB000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0xBBBBBBB661); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_VID, + 0xBBBBBBB000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0xBBBBBBB661, + cleanup); // peer 1 - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_PEER_1, - 0xBBBBBBB000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0x200000BBBBBBB663); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_PEER_1, + 0xBBBBBBB000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0x200000BBBBBBB663, + cleanup); // sparse - TEST_CHECK_RET(hal->make_sparse_pte() == 0x8); + TEST_CHECK_GOTO(hal->make_sparse_pte() == 0x8, cleanup); // sked reflected - TEST_CHECK_RET(hal->make_sked_reflected_pte() == 0xF09); + TEST_CHECK_GOTO(hal->make_sked_reflected_pte() == 0xF09, cleanup); num_page_sizes = get_page_sizes(gpu, page_sizes); for (i = 0; i < num_page_sizes; i++) - TEST_NV_CHECK_RET(entry_test_page_size(gpu, page_sizes[i])); + TEST_NV_CHECK_GOTO(entry_test_page_size(gpu, page_sizes[i]), cleanup); - return NV_OK; +cleanup: + for (i = 0; i < ARRAY_SIZE(dirs); i++) + uvm_kvfree(dirs[i]); + + return status; } static NV_STATUS alloc_4k_maxwell(uvm_gpu_t *gpu) @@ -2303,7 +2457,8 @@ NV_STATUS uvm_test_page_tree(UVM_TEST_PAGE_TREE_PARAMS *params, struct file *fil gpu->parent = parent_gpu; // At least test_tlb_invalidates() relies on global state - // (g_tlb_invalidate_*) so make sure only one test instance can run at a time. + // (g_tlb_invalidate_*) so make sure only one test instance can run at a + // time. uvm_mutex_lock(&g_uvm_global.global_lock); // Allocate the fake TLB tracking state. Notably tests still need to enable @@ -2311,7 +2466,13 @@ NV_STATUS uvm_test_page_tree(UVM_TEST_PAGE_TREE_PARAMS *params, struct file *fil // calls. TEST_NV_CHECK_GOTO(fake_tlb_invals_alloc(), done); - TEST_NV_CHECK_GOTO(maxwell_test_page_tree(gpu), done); + // We prevent the maxwell_test_page_tree test from running on ATS-enabled + // systems. On "fake" Maxwell-based ATS systems pde_fill() may push more + // methods than what we support in UVM. Specifically, on + // uvm_page_tree_init() which eventually calls phys_mem_init(). On Maxwell, + // upper PDE levels have more than 512 entries. + if (!g_uvm_global.ats.enabled) + TEST_NV_CHECK_GOTO(maxwell_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(pascal_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(volta_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(ampere_test_page_tree(gpu), done); diff --git a/kernel-open/nvidia-uvm/uvm_pascal.c b/kernel-open/nvidia-uvm/uvm_pascal.c index 83c675a27..200f36618 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal.c +++ b/kernel-open/nvidia-uvm/uvm_pascal.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2020 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -100,4 +100,6 @@ void uvm_hal_pascal_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_pascal_mmu.c b/kernel-open/nvidia-uvm/uvm_pascal_mmu.c index 8b17319e9..52db04699 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_pascal_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2020 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -140,11 +140,18 @@ static NvU64 small_half_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_pascal(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_pascal(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_pascal(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_pascal(dir->depth); + if (entry_count == 1) { *entry_bits = single_pde_pascal(*phys_allocs); } @@ -152,7 +159,8 @@ static void make_pde_pascal(void *entry, uvm_mmu_page_table_alloc_t **phys_alloc entry_bits[MMU_BIG] = big_half_pde_pascal(phys_allocs[MMU_BIG]); entry_bits[MMU_SMALL] = small_half_pde_pascal(phys_allocs[MMU_SMALL]); - // This entry applies to the whole dual PDE but is stored in the lower bits + // This entry applies to the whole dual PDE but is stored in the lower + // bits. entry_bits[MMU_BIG] |= HWCONST64(_MMU_VER2, DUAL_PDE, IS_PDE, TRUE); } else { diff --git a/kernel-open/nvidia-uvm/uvm_test.c b/kernel-open/nvidia-uvm/uvm_test.c index f9f5744c0..50a1a0c72 100644 --- a/kernel-open/nvidia-uvm/uvm_test.c +++ b/kernel-open/nvidia-uvm/uvm_test.c @@ -36,6 +36,7 @@ #include "uvm_mmu.h" #include "uvm_gpu_access_counters.h" #include "uvm_pmm_sysmem.h" +#include "uvm_migrate_pageable.h" static NV_STATUS uvm_test_get_gpu_ref_count(UVM_TEST_GET_GPU_REF_COUNT_PARAMS *params, struct file *filp) { @@ -331,6 +332,7 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED, uvm_test_cgroup_accounting_supported); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SPLIT_INVALIDATE_DELAY, uvm_test_split_invalidate_delay); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_CPU_CHUNK_API, uvm_test_cpu_chunk_api); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SKIP_MIGRATE_VMA, uvm_test_skip_migrate_vma); } return -EINVAL; diff --git a/kernel-open/nvidia-uvm/uvm_test_ioctl.h b/kernel-open/nvidia-uvm/uvm_test_ioctl.h index ef73be0c0..19dc08c34 100644 --- a/kernel-open/nvidia-uvm/uvm_test_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_test_ioctl.h @@ -28,6 +28,13 @@ #include "uvm_ioctl.h" #include "nv_uvm_types.h" +#define UVM_TEST_SKIP_MIGRATE_VMA UVM_TEST_IOCTL_BASE(103) +typedef struct +{ + NvBool skip; // In + NV_STATUS rmStatus; // Out +} UVM_TEST_SKIP_MIGRATE_VMA_PARAMS; + #ifdef __cplusplus extern "C" { #endif diff --git a/kernel-open/nvidia-uvm/uvm_tools.c b/kernel-open/nvidia-uvm/uvm_tools.c index 607ace44a..3619a7ceb 100644 --- a/kernel-open/nvidia-uvm/uvm_tools.c +++ b/kernel-open/nvidia-uvm/uvm_tools.c @@ -1082,25 +1082,19 @@ void uvm_tools_broadcast_replay(uvm_gpu_t *gpu, } -void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, - NvU32 batch_id, - uvm_fault_client_type_t client_type) +void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, NvU32 batch_id, uvm_fault_client_type_t client_type) { UVM_ASSERT(!gpu->parent->has_clear_faulted_channel_method); if (!tools_is_event_enabled_in_any_va_space(UvmEventTypeGpuFaultReplay)) return; - record_replay_event_helper(gpu->id, - batch_id, - client_type, - NV_GETTIME(), - gpu->parent->host_hal->get_time(gpu)); + record_replay_event_helper(gpu->id, batch_id, client_type, NV_GETTIME(), gpu->parent->host_hal->get_time(gpu)); } void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *buffer_entry, - bool on_managed) + bool on_managed_phys) { UvmEventEntry entry; UvmEventTestAccessCounterInfo *info = &entry.testEventData.accessCounter; @@ -1119,6 +1113,7 @@ void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, info->srcIndex = uvm_id_value(gpu->id); info->address = buffer_entry->address.address; info->isVirtual = buffer_entry->address.is_virtual? 1: 0; + if (buffer_entry->address.is_virtual) { info->instancePtr = buffer_entry->virtual_info.instance_ptr.address; info->instancePtrAperture = g_hal_to_tools_aperture_table[buffer_entry->virtual_info.instance_ptr.aperture]; @@ -1126,9 +1121,10 @@ void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, } else { info->aperture = g_hal_to_tools_aperture_table[buffer_entry->address.aperture]; + info->physOnManaged = on_managed_phys? 1 : 0; } + info->isFromCpu = buffer_entry->counter_type == UVM_ACCESS_COUNTER_TYPE_MOMC? 1: 0; - info->onManaged = on_managed? 1 : 0; info->value = buffer_entry->counter_value; info->subGranularity = buffer_entry->sub_granularity; info->bank = buffer_entry->bank; diff --git a/kernel-open/nvidia-uvm/uvm_tools.h b/kernel-open/nvidia-uvm/uvm_tools.h index 988b10f46..0a8d4f847 100644 --- a/kernel-open/nvidia-uvm/uvm_tools.h +++ b/kernel-open/nvidia-uvm/uvm_tools.h @@ -102,18 +102,13 @@ void uvm_tools_record_read_duplicate_invalidate(uvm_va_block_t *va_block, uvm_va_block_region_t region, const uvm_page_mask_t *page_mask); -void uvm_tools_broadcast_replay(uvm_gpu_t *gpu, - uvm_push_t *push, - NvU32 batch_id, - uvm_fault_client_type_t client_type); +void uvm_tools_broadcast_replay(uvm_gpu_t *gpu, uvm_push_t *push, NvU32 batch_id, uvm_fault_client_type_t client_type); -void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, - NvU32 batch_id, - uvm_fault_client_type_t client_type); +void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, NvU32 batch_id, uvm_fault_client_type_t client_type); void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *buffer_entry, - bool on_managed); + bool on_managed_phys); void uvm_tools_test_hmm_split_invalidate(uvm_va_space_t *va_space); diff --git a/kernel-open/nvidia-uvm/uvm_turing.c b/kernel-open/nvidia-uvm/uvm_turing.c index 29a1fa68d..86f000b39 100644 --- a/kernel-open/nvidia-uvm/uvm_turing.c +++ b/kernel-open/nvidia-uvm/uvm_turing.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -93,4 +93,6 @@ void uvm_hal_turing_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->smc.supported = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_types.h b/kernel-open/nvidia-uvm/uvm_types.h index da3e6da7a..56f42f9b6 100644 --- a/kernel-open/nvidia-uvm/uvm_types.h +++ b/kernel-open/nvidia-uvm/uvm_types.h @@ -967,8 +967,10 @@ typedef struct NvU8 isFromCpu; NvU8 veId; - NvU8 onManaged; // The access counter notification was triggered on - // a managed memory region + + // The physical access counter notification was triggered on a managed + // memory region. This is not set for virtual access counter notifications. + NvU8 physOnManaged; NvU32 value; NvU32 subGranularity; diff --git a/kernel-open/nvidia-uvm/uvm_va_block.c b/kernel-open/nvidia-uvm/uvm_va_block.c index cce4dcf8d..9d7d1913c 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.c +++ b/kernel-open/nvidia-uvm/uvm_va_block.c @@ -1760,6 +1760,21 @@ static NvU32 block_phys_page_size(uvm_va_block_t *block, block_phys_page_t page) return (NvU32)chunk_size; } +NvU32 uvm_va_block_get_physical_size(uvm_va_block_t *block, + uvm_processor_id_t processor, + uvm_page_index_t page_index) +{ + block_phys_page_t page; + + UVM_ASSERT(block); + + uvm_assert_mutex_locked(&block->lock); + + page = block_phys_page(processor, page_index); + + return block_phys_page_size(block, page); +} + static uvm_pte_bits_cpu_t get_cpu_pte_bit_index(uvm_prot_t prot) { uvm_pte_bits_cpu_t pte_bit_index = UVM_PTE_BITS_CPU_MAX; @@ -8248,14 +8263,6 @@ void uvm_va_block_munmap_region(uvm_va_block_t *va_block, event_data.block_munmap.region = region; uvm_perf_event_notify(&va_space->perf_events, UVM_PERF_EVENT_BLOCK_MUNMAP, &event_data); - // Set a flag so that GPU fault events are flushed since they might refer - // to the region being unmapped. - // Note that holding the va_block lock prevents GPU VA spaces from - // being removed so the registered_gpu_va_spaces mask is stable. - for_each_gpu_id_in_mask(gpu_id, &va_space->registered_gpu_va_spaces) { - uvm_processor_mask_set_atomic(&va_space->needs_fault_buffer_flush, gpu_id); - } - // Release any remaining vidmem chunks in the given region. for_each_gpu_id(gpu_id) { uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, gpu_id); @@ -10155,6 +10162,34 @@ static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(preferred_location)], processor_id)) return preferred_location; + // Check if we should map the closest resident processor remotely on remote CPU fault + // + // When faulting on CPU, there's a linux process on behalf of it, which is associated + // with a unique VM pointed by current->mm. A block of memory residing on GPU is also + // associated with VM, pointed by va_block_context->mm. If they match, it's a regular + // (local) fault, and we may want to migrate a page from GPU to CPU. + // If it's a 'remote' fault, i.e. linux process differs from one associated with block + // VM, we might preserve residence. + // + // Establishing a remote fault without access counters means the memory could stay in + // the wrong spot for a long time, which is why we prefer to avoid creating remote + // mappings. However when NIC accesses a memory residing on GPU, it's worth to keep it + // in place for NIC accesses. + // + // The logic that's used to detect remote faulting also keeps memory in place for + // ptrace accesses. We would prefer to control those policies separately, but the + // NIC case takes priority. + // If the accessing processor is CPU, we're either handling a fault + // from other than owning process, or we're handling an MOMC + // notification. Only prevent migration for the former. + if (UVM_ID_IS_CPU(processor_id) && + operation != UVM_SERVICE_OPERATION_ACCESS_COUNTERS && + uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(closest_resident_processor)], processor_id) && + va_block_context->mm != current->mm) { + UVM_ASSERT(va_block_context->mm != NULL); + return closest_resident_processor; + } + // If the page is resident on a processor other than the preferred location, // or the faulting processor can't access the preferred location, we select // the faulting processor as the new residency. @@ -10713,7 +10748,7 @@ NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id, uvm_page_index_t page_index, - uvm_fault_type_t access_type, + uvm_fault_access_type_t access_type, bool allow_migration) { uvm_va_range_t *va_range = va_block->va_range; diff --git a/kernel-open/nvidia-uvm/uvm_va_block.h b/kernel-open/nvidia-uvm/uvm_va_block.h index 364cba79d..3d19fa020 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.h +++ b/kernel-open/nvidia-uvm/uvm_va_block.h @@ -1000,7 +1000,7 @@ NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id, uvm_page_index_t page_index, - uvm_fault_type_t access_type, + uvm_fault_access_type_t access_type, bool allow_migration); // API for access privilege revocation @@ -2072,6 +2072,14 @@ void uvm_va_block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *va_block, // Locking: The va_block lock must be held. void uvm_va_block_remove_cpu_chunks(uvm_va_block_t *va_block, uvm_va_block_region_t region); +// Get the size of the physical allocation backing the page at page_index on the +// specified processor in the block. Returns 0 if the address is not resident on +// the specified processor. +// Locking: The va_block lock must be held. +NvU32 uvm_va_block_get_physical_size(uvm_va_block_t *block, + uvm_processor_id_t processor, + uvm_page_index_t page_index); + // Get CPU page size or 0 if it is not mapped NvU32 uvm_va_block_page_size_cpu(uvm_va_block_t *va_block, uvm_page_index_t page_index); diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.h b/kernel-open/nvidia-uvm/uvm_va_policy.h index cd207287e..11b54ab4a 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.h +++ b/kernel-open/nvidia-uvm/uvm_va_policy.h @@ -193,7 +193,8 @@ uvm_va_policy_node_t *uvm_va_policy_node_iter_next(uvm_va_block_t *va_block, uvm for ((node) = uvm_va_policy_node_iter_first((va_block), (start), (end)), \ (next) = uvm_va_policy_node_iter_next((va_block), (node), (end)); \ (node); \ - (node) = (next)) + (node) = (next), \ + (next) = uvm_va_policy_node_iter_next((va_block), (node), (end))) // Returns the first policy in the range [start, end], if any. // Locking: The va_block lock must be held. diff --git a/kernel-open/nvidia-uvm/uvm_va_space.c b/kernel-open/nvidia-uvm/uvm_va_space.c index daa49d2fb..a275aad96 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.c +++ b/kernel-open/nvidia-uvm/uvm_va_space.c @@ -1540,7 +1540,6 @@ static void remove_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space, atomic_inc(&va_space->gpu_va_space_deferred_free.num_pending); uvm_processor_mask_clear(&va_space->registered_gpu_va_spaces, gpu_va_space->gpu->id); - uvm_processor_mask_clear_atomic(&va_space->needs_fault_buffer_flush, gpu_va_space->gpu->id); va_space->gpu_va_spaces[uvm_id_gpu_index(gpu_va_space->gpu->id)] = NULL; gpu_va_space->state = UVM_GPU_VA_SPACE_STATE_DEAD; } diff --git a/kernel-open/nvidia-uvm/uvm_va_space.h b/kernel-open/nvidia-uvm/uvm_va_space.h index 1962ada98..8be6be25a 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.h +++ b/kernel-open/nvidia-uvm/uvm_va_space.h @@ -253,17 +253,6 @@ struct uvm_va_space_struct // corrupting state. uvm_processor_mask_t gpu_unregister_in_progress; - // On VMA destruction, the fault buffer needs to be flushed for all the GPUs - // registered in the VA space to avoid leaving stale entries of the VA range - // that is going to be destroyed. Otherwise, these fault entries can be - // attributed to new VA ranges reallocated at the same addresses. However, - // uvm_vm_close is called with mm->mmap_lock taken and we cannot take the - // ISR lock. Therefore, we use a flag to notify the GPU fault handler that - // the fault buffer needs to be flushed, before servicing the faults that - // belong to the va_space. The bits are set and cleared atomically so no - // va_space lock is required. - uvm_processor_mask_t needs_fault_buffer_flush; - // Mask of processors that are participating in system-wide atomics uvm_processor_mask_t system_wide_atomics_enabled_processors; @@ -353,6 +342,7 @@ struct uvm_va_space_struct struct { bool page_prefetch_enabled; + bool skip_migrate_vma; atomic_t migrate_vma_allocation_fail_nth; diff --git a/kernel-open/nvidia-uvm/uvm_va_space_mm.c b/kernel-open/nvidia-uvm/uvm_va_space_mm.c index 19b570500..f08aa296c 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space_mm.c +++ b/kernel-open/nvidia-uvm/uvm_va_space_mm.c @@ -215,7 +215,13 @@ bool uvm_va_space_mm_enabled(uvm_va_space_t *va_space) static struct mmu_notifier_ops uvm_mmu_notifier_ops_ats = { +#if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) .invalidate_range = uvm_mmu_notifier_invalidate_range_ats, +#elif defined(NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS) + .arch_invalidate_secondary_tlbs = uvm_mmu_notifier_invalidate_range_ats, +#else + #error One of invalidate_range/arch_invalid_secondary must be present +#endif }; static int uvm_mmu_notifier_register(uvm_va_space_mm_t *va_space_mm) diff --git a/kernel-open/nvidia-uvm/uvm_volta.c b/kernel-open/nvidia-uvm/uvm_volta.c index 058449086..ad3b2f846 100644 --- a/kernel-open/nvidia-uvm/uvm_volta.c +++ b/kernel-open/nvidia-uvm/uvm_volta.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -98,4 +98,6 @@ void uvm_hal_volta_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_volta_mmu.c b/kernel-open/nvidia-uvm/uvm_volta_mmu.c index e06436002..76da47ab4 100644 --- a/kernel-open/nvidia-uvm/uvm_volta_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_volta_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -145,13 +145,20 @@ static NvU64 small_half_pde_volta(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_volta(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_volta(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_volta(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_volta(dir->depth); + if (entry_count == 1) { - *entry_bits = single_pde_volta(*phys_allocs, depth); + *entry_bits = single_pde_volta(*phys_allocs, dir->depth); } else if (entry_count == 2) { entry_bits[MMU_BIG] = big_half_pde_volta(phys_allocs[MMU_BIG]); diff --git a/kernel-open/nvidia/libspdm_shash.c b/kernel-open/nvidia/libspdm_shash.c index 10e9bff1a..5a9650100 100644 --- a/kernel-open/nvidia/libspdm_shash.c +++ b/kernel-open/nvidia/libspdm_shash.c @@ -23,10 +23,16 @@ #include "internal_crypt_lib.h" +#ifdef USE_LKCA +#ifndef NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT +#include <crypto/internal/hash.h> +#endif +#endif + void *lkca_hash_new(const char* alg_name) { #ifndef USE_LKCA - return false; + return NULL; #else //XXX: can we reuse crypto_shash part and just allocate desc struct crypto_shash *alg; @@ -87,9 +93,24 @@ bool lkca_hmac_duplicate(struct shash_desc *dst, struct shash_desc const *src) struct crypto_shash *src_tfm = src->tfm; struct crypto_shash *dst_tfm = dst->tfm; + int ss = crypto_shash_statesize(dst_tfm); + +#ifdef NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT char *src_ipad = crypto_tfm_ctx_aligned(&src_tfm->base); char *dst_ipad = crypto_tfm_ctx_aligned(&dst_tfm->base); - int ss = crypto_shash_statesize(dst_tfm); +#else + int ctx_size = crypto_shash_alg(dst_tfm)->base.cra_ctxsize; + char *src_ipad = crypto_shash_ctx(src_tfm); + char *dst_ipad = crypto_shash_ctx(dst_tfm); + /* + * Actual struct definition is hidden, so I assume data we need is at + * the end. In 6.0 the struct has a pointer to crpyto_shash followed by: + * 'u8 ipad[statesize];', then 'u8 opad[statesize];' + */ + src_ipad += ctx_size - 2 * ss; + dst_ipad += ctx_size - 2 * ss; +#endif + memcpy(dst_ipad, src_ipad, crypto_shash_blocksize(src->tfm)); memcpy(dst_ipad + ss, src_ipad + ss, crypto_shash_blocksize(src->tfm)); crypto_shash_clear_flags(dst->tfm, CRYPTO_TFM_NEED_KEY); diff --git a/kernel-open/nvidia/nv-msi.c b/kernel-open/nvidia/nv-msi.c index a5a6a485b..959bc3426 100644 --- a/kernel-open/nvidia/nv-msi.c +++ b/kernel-open/nvidia/nv-msi.c @@ -156,7 +156,7 @@ NvS32 NV_API_CALL nv_request_msix_irq(nv_linux_state_t *nvl) { for( j = 0; j < i; j++) { - free_irq(nvl->msix_entries[i].vector, (void *)nvl); + free_irq(nvl->msix_entries[j].vector, (void *)nvl); } break; } diff --git a/kernel-open/nvidia/nv-p2p.c b/kernel-open/nvidia/nv-p2p.c index e6fa5c5e8..3e1ab526a 100644 --- a/kernel-open/nvidia/nv-p2p.c +++ b/kernel-open/nvidia/nv-p2p.c @@ -316,14 +316,14 @@ int nvidia_p2p_init_mapping( return -ENOTSUPP; } -EXPORT_SYMBOL(nvidia_p2p_init_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_init_mapping); int nvidia_p2p_destroy_mapping(uint64_t p2p_token) { return -ENOTSUPP; } -EXPORT_SYMBOL(nvidia_p2p_destroy_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_destroy_mapping); static void nv_p2p_mem_info_free_callback(void *data) { @@ -506,8 +506,13 @@ static int nv_p2p_get_pages( (*page_table)->page_size = page_size_index; os_free_mem(physical_addresses); + physical_addresses = NULL; + os_free_mem(wreqmb_h); + wreqmb_h = NULL; + os_free_mem(rreqmb_h); + rreqmb_h = NULL; if (free_callback != NULL) { @@ -582,7 +587,7 @@ int nvidia_p2p_get_pages( p2p_token, va_space, virtual_address, length, page_table, free_callback, data); } -EXPORT_SYMBOL(nvidia_p2p_get_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_get_pages); int nvidia_p2p_get_pages_persistent( uint64_t virtual_address, @@ -600,7 +605,7 @@ int nvidia_p2p_get_pages_persistent( virtual_address, length, page_table, NULL, NULL); } -EXPORT_SYMBOL(nvidia_p2p_get_pages_persistent); +NV_EXPORT_SYMBOL(nvidia_p2p_get_pages_persistent); /* * This function is a no-op, but is left in place (for now), in order to allow @@ -613,7 +618,7 @@ int nvidia_p2p_free_page_table(struct nvidia_p2p_page_table *page_table) return 0; } -EXPORT_SYMBOL(nvidia_p2p_free_page_table); +NV_EXPORT_SYMBOL(nvidia_p2p_free_page_table); int nvidia_p2p_put_pages( uint64_t p2p_token, @@ -645,7 +650,7 @@ int nvidia_p2p_put_pages( return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_put_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_put_pages); int nvidia_p2p_put_pages_persistent( uint64_t virtual_address, @@ -685,7 +690,7 @@ int nvidia_p2p_put_pages_persistent( return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_put_pages_persistent); +NV_EXPORT_SYMBOL(nvidia_p2p_put_pages_persistent); int nvidia_p2p_dma_map_pages( struct pci_dev *peer, @@ -800,7 +805,7 @@ failed: return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_dma_map_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_dma_map_pages); int nvidia_p2p_dma_unmap_pages( struct pci_dev *peer, @@ -840,7 +845,7 @@ int nvidia_p2p_dma_unmap_pages( return 0; } -EXPORT_SYMBOL(nvidia_p2p_dma_unmap_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_dma_unmap_pages); /* * This function is a no-op, but is left in place (for now), in order to allow @@ -855,7 +860,7 @@ int nvidia_p2p_free_dma_mapping( return 0; } -EXPORT_SYMBOL(nvidia_p2p_free_dma_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_free_dma_mapping); int nvidia_p2p_register_rsync_driver( nvidia_p2p_rsync_driver_t *driver, @@ -884,7 +889,7 @@ int nvidia_p2p_register_rsync_driver( driver->wait_for_rsync, data); } -EXPORT_SYMBOL(nvidia_p2p_register_rsync_driver); +NV_EXPORT_SYMBOL(nvidia_p2p_register_rsync_driver); void nvidia_p2p_unregister_rsync_driver( nvidia_p2p_rsync_driver_t *driver, @@ -916,7 +921,7 @@ void nvidia_p2p_unregister_rsync_driver( driver->wait_for_rsync, data); } -EXPORT_SYMBOL(nvidia_p2p_unregister_rsync_driver); +NV_EXPORT_SYMBOL(nvidia_p2p_unregister_rsync_driver); int nvidia_p2p_get_rsync_registers( nvidia_p2p_rsync_reg_info_t **reg_info @@ -1009,7 +1014,7 @@ int nvidia_p2p_get_rsync_registers( return 0; } -EXPORT_SYMBOL(nvidia_p2p_get_rsync_registers); +NV_EXPORT_SYMBOL(nvidia_p2p_get_rsync_registers); void nvidia_p2p_put_rsync_registers( nvidia_p2p_rsync_reg_info_t *reg_info @@ -1041,4 +1046,4 @@ void nvidia_p2p_put_rsync_registers( os_free_mem(reg_info); } -EXPORT_SYMBOL(nvidia_p2p_put_rsync_registers); +NV_EXPORT_SYMBOL(nvidia_p2p_put_rsync_registers); diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 38464875a..b9a4eb71c 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -1224,12 +1224,11 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) rm_read_registry_dword(sp, nv, NV_REG_ENABLE_MSI, &msi_config); if (msi_config == 1) { - if (pci_find_capability(nvl->pci_dev, PCI_CAP_ID_MSIX)) + if (nvl->pci_dev->msix_cap && rm_is_msix_allowed(sp, nv)) { nv_init_msix(nv); } - if (pci_find_capability(nvl->pci_dev, PCI_CAP_ID_MSI) && - !(nv->flags & NV_FLAG_USES_MSIX)) + if (nvl->pci_dev->msi_cap && !(nv->flags & NV_FLAG_USES_MSIX)) { nv_init_msi(nv); } diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild index e868c6c32..7908ce716 100644 --- a/kernel-open/nvidia/nvidia.Kbuild +++ b/kernel-open/nvidia/nvidia.Kbuild @@ -195,6 +195,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_task_ioprio NV_CONFTEST_FUNCTION_COMPILE_TESTS += mdev_set_iommu_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += offline_and_remove_memory +NV_CONFTEST_FUNCTION_COMPILE_TESTS += crypto_tfm_ctx_aligned NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_of_node_to_nid NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sme_active @@ -215,6 +216,7 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_get_dram_num_channe NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_dram_types NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pxm_to_node NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_screen_info +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_screen_info NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_i2c_bus_status NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_fuse_control_read NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_get_platform diff --git a/kernel-open/nvidia/nvlink_export.h b/kernel-open/nvidia/nvlink_export.h index 471ec8380..e7deaff02 100644 --- a/kernel-open/nvidia/nvlink_export.h +++ b/kernel-open/nvidia/nvlink_export.h @@ -46,6 +46,11 @@ NvlStatus nvlink_lib_unload(void); */ NvlStatus nvlink_lib_ioctl_ctrl(nvlink_ioctrl_params *ctrl_params); +/* +* Gets number of devices with type deviceType +*/ +NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices); + #ifdef __cplusplus } #endif diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index 5969e6970..10afcba3e 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -28,6 +28,11 @@ #include "nv-time.h" +#include <linux/mmzone.h> +#include <linux/numa.h> + +#include <linux/pid.h> + extern char *NVreg_TemporaryFilePath; #define MAX_ERROR_STRING 512 @@ -1242,9 +1247,12 @@ void NV_API_CALL os_get_screen_info( * SYSFB_SIMPLEFB registers a dummy framebuffer which does not contain the * information required by os_get_screen_info(), therefore you need to * fall back onto the screen_info structure. + * + * After commit b8466fe82b79 ("efi: move screen_info into efi init code") + * in v6.7, 'screen_info' is exported as GPL licensed symbol for ARM64. */ -#if NV_IS_EXPORT_SYMBOL_PRESENT_screen_info +#if NV_CHECK_EXPORT_SYMBOL(screen_info) /* * If there is not a framebuffer console, return 0 size. * @@ -2122,6 +2130,43 @@ void NV_API_CALL os_nv_cap_close_fd nv_cap_close_fd(fd); } +/* + * Reads the total memory and free memory of a NUMA node from the kernel. + */ +NV_STATUS NV_API_CALL os_get_numa_node_memory_usage +( + NvS32 node_id, + NvU64 *free_memory_bytes, + NvU64 *total_memory_bytes +) +{ + struct pglist_data *pgdat; + struct zone *zone; + NvU32 zone_id; + + if (node_id >= MAX_NUMNODES) + { + nv_printf(NV_DBG_ERRORS, "Invalid NUMA node ID\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + pgdat = NODE_DATA(node_id); + + *free_memory_bytes = 0; + *total_memory_bytes = 0; + + for (zone_id = 0; zone_id < MAX_NR_ZONES; zone_id++) + { + zone = &(pgdat->node_zones[zone_id]); + if (!populated_zone(zone)) + continue; + *free_memory_bytes += (zone_page_state_snapshot(zone, NR_FREE_PAGES) * PAGE_SIZE); + *total_memory_bytes += (zone->present_pages * PAGE_SIZE); + } + + return NV_OK; +} + typedef struct os_numa_gpu_mem_hotplug_notifier_s { NvU64 start_pa; @@ -2373,3 +2418,28 @@ NV_STATUS NV_API_CALL os_offline_page_at_address #endif } +void* NV_API_CALL os_get_pid_info(void) +{ + return get_task_pid(current, PIDTYPE_PID); +} + +void NV_API_CALL os_put_pid_info(void *pid_info) +{ + if (pid_info != NULL) + put_pid(pid_info); +} + +NV_STATUS NV_API_CALL os_find_ns_pid(void *pid_info, NvU32 *ns_pid) +{ + if ((pid_info == NULL) || (ns_pid == NULL)) + return NV_ERR_INVALID_ARGUMENT; + + *ns_pid = pid_vnr((struct pid *)pid_info); + + // The call returns 0 if the PID is not found in the current ns + if (*ns_pid == 0) + return NV_ERR_OBJECT_NOT_FOUND; + + return NV_OK; +} + diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index 370274c52..516620963 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -1360,7 +1360,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0) { NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); - NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * 1000000000); + NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * (NvU64)1000000000); if (requiredBW > availableBw) { compoundQueryResult = false; @@ -1375,10 +1375,10 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, else if (dev->pconCaps.maxTmdsClkRate != 0) { NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate); - NvU64 requireBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + NvU64 requiredBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); if (modesetParams.colorFormat == dpColorFormat_YCbCr420) { - if (maxTmdsClkRateU64 < ((requireBw/24)/2)) + if (maxTmdsClkRateU64 < ((requiredBw/24)/2)) { compoundQueryResult = false; return false; @@ -1386,7 +1386,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, } else { - if (maxTmdsClkRateU64 < (requireBw/24)) + if (maxTmdsClkRateU64 < (requiredBw/24)) { compoundQueryResult = false; return false; @@ -4740,7 +4740,7 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, { LinkTrainingType preferredTrainingType = trainType; bool result; - bool bEnableFecOnSor; + // // Validate link config against caps // @@ -4832,16 +4832,7 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, result = postLTAdjustment(activeLinkConfig, force); } - bEnableFecOnSor = lConfig.bEnableFEC; - - if (main->isEDP()) - { - DeviceImpl * nativeDev = findDeviceInList(Address()); - if (nativeDev && nativeDev->bIsPreviouslyFakedMuxDevice) - bEnableFecOnSor = activeLinkConfig.bEnableFEC; - } - - if((lConfig.lanes != 0) && result && bEnableFecOnSor) + if((lConfig.lanes != 0) && result && activeLinkConfig.bEnableFEC) { // // Extended latency from link-train end to FEC enable pattern @@ -6057,7 +6048,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) if (this->bReassessMaxLink) { // - // If the highest assessed LC is not equal to + // If the highest assessed LC is not equal to // max possible link config, re-assess link // NvU8 retries = 0U; diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index 04f6c5c64..bccfb2307 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -43,18 +43,18 @@ #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/VK535_87-147" -#define NV_BUILD_CHANGELIST_NUM (33800935) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/VK535_87-148" +#define NV_BUILD_CHANGELIST_NUM (33833102) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r535/VK535_87-147" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33800935) +#define NV_BUILD_NAME "rel/gpu_drv/r535/VK535_87-148" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33833102) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "VK535_87-24" -#define NV_BUILD_CHANGELIST_NUM (33800935) +#define NV_BUILD_BRANCH_VERSION "VK535_87-25" +#define NV_BUILD_CHANGELIST_NUM (33833102) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "538.31" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33800935) +#define NV_BUILD_NAME "538.35" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33833102) #define NV_BUILD_BRANCH_BASE_VERSION R535 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index ffec77e74..846c422fa 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "535.43.23" +#define NV_VERSION_STRING "535.43.24" #else diff --git a/src/common/inc/nvVer.h b/src/common/inc/nvVer.h index 4e55a3c77..c8113d618 100644 --- a/src/common/inc/nvVer.h +++ b/src/common/inc/nvVer.h @@ -3,7 +3,7 @@ #define NV_COMPANY_NAME_STRING_SHORT "NVIDIA" #define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation" #define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL -#define NV_COPYRIGHT_YEAR "2023" +#define NV_COPYRIGHT_YEAR "2024" #define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C). #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ diff --git a/src/common/inc/nveGPUConfig.h b/src/common/inc/nveGPUConfig.h index 751e0736b..44873a823 100644 --- a/src/common/inc/nveGPUConfig.h +++ b/src/common/inc/nveGPUConfig.h @@ -39,48 +39,63 @@ extern "C" { #endif //NV_UNIX #endif //!__cplusplus -// Surprise removal capable TB3 and TB2 BUS Device ID -#define BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01 0x1578 -#define BUS_DEVICE_ID_TB3_02 0x1576 -#define BUS_DEVICE_ID_TB3_03 0x15C0 -#define BUS_DEVICE_ID_TB3_04 0x15D3 -#define BUS_DEVICE_ID_TB3_05 0x15DA -#define BUS_DEVICE_ID_TB3_06 0x15EA -#define BUS_DEVICE_ID_TB3_07 0x15E7 -#define BUS_DEVICE_ID_TB3_08 0x15EF -#define BUS_DEVICE_ID_TB3_09 0x1133 -#define BUS_DEVICE_ID_TB3_10 0x1136 +#define PARENT_EGPU_BUS_DEVICE_43 0x57A4 +#define PARENT_EGPU_BUS_DEVICE_42 0x5786 +#define PARENT_EGPU_BUS_DEVICE_41 0x1578 +#define PARENT_EGPU_BUS_DEVICE_40 0x1576 +#define PARENT_EGPU_BUS_DEVICE_39 0x15C0 +#define PARENT_EGPU_BUS_DEVICE_38 0x15D3 +#define PARENT_EGPU_BUS_DEVICE_37 0x15DA +#define PARENT_EGPU_BUS_DEVICE_36 0x15EA +#define PARENT_EGPU_BUS_DEVICE_35 0x15E7 +#define PARENT_EGPU_BUS_DEVICE_34 0x15EF +#define PARENT_EGPU_BUS_DEVICE_33 0x1133 +#define PARENT_EGPU_BUS_DEVICE_32 0x1136 -// IceLake-U TB3 device ids. Below TB3 would be integrated to CPU. -#define BUS_DEVICE_ID_ICELAKE_TB3_01 0x8A1D -#define BUS_DEVICE_ID_ICELAKE_TB3_02 0x8A1F -#define BUS_DEVICE_ID_ICELAKE_TB3_03 0x8A21 -#define BUS_DEVICE_ID_ICELAKE_TB3_04 0x8A23 -#define BUS_DEVICE_ID_ICELAKE_TB3_05 0x8A0D -#define BUS_DEVICE_ID_ICELAKE_TB3_06 0x8A17 +#define PARENT_EGPU_BUS_DEVICE_31 0x8A1D +#define PARENT_EGPU_BUS_DEVICE_30 0x8A1F +#define PARENT_EGPU_BUS_DEVICE_29 0x8A21 +#define PARENT_EGPU_BUS_DEVICE_28 0x8A23 +#define PARENT_EGPU_BUS_DEVICE_27 0x8A0D +#define PARENT_EGPU_BUS_DEVICE_26 0x8A17 -// TigerLake Thunderbolt device ids. -#define BUS_DEVICE_ID_TIGERLAKE_TB3_01 0x9A1B -#define BUS_DEVICE_ID_TIGERLAKE_TB3_02 0x9A1D -#define BUS_DEVICE_ID_TIGERLAKE_TB3_03 0x9A1F -#define BUS_DEVICE_ID_TIGERLAKE_TB3_04 0x9A21 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_05 0x9A23 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_06 0x9A25 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_07 0x9A27 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_08 0x9A29 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B -#define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D -//#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete -#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D -#define BUS_DEVICE_ID_TB2_03 0x157E -#define BUS_DEVICE_ID_TB2_04 0x156B -#define BUS_DEVICE_ID_TB2_05 0x1567 -#define BUS_DEVICE_ID_TB2_06 0x1569 -//#define BUS_DEVICE_ID_TB2_07 0x1548 // obsolete -#define BUS_DEVICE_ID_TB2_08 0x151B -#define BUS_DEVICE_ID_TB2_09 0x1549 -#define BUS_DEVICE_ID_TB2_10 0x1513 +#define PARENT_EGPU_BUS_DEVICE_25 0x9A1B +#define PARENT_EGPU_BUS_DEVICE_24 0x9A1D +#define PARENT_EGPU_BUS_DEVICE_23 0x9A1F +#define PARENT_EGPU_BUS_DEVICE_22 0x9A21 +#define PARENT_EGPU_BUS_DEVICE_21 0x9A23 +#define PARENT_EGPU_BUS_DEVICE_20 0x9A25 +#define PARENT_EGPU_BUS_DEVICE_19 0x9A27 +#define PARENT_EGPU_BUS_DEVICE_18 0x9A29 +#define PARENT_EGPU_BUS_DEVICE_17 0x9A2B +#define PARENT_EGPU_BUS_DEVICE_16 0x9A2D + +#define PARENT_EGPU_BUS_DEVICE_15 0x7EB2 +#define PARENT_EGPU_BUS_DEVICE_14 0x7EC2 +#define PARENT_EGPU_BUS_DEVICE_13 0x7EC3 +#define PARENT_EGPU_BUS_DEVICE_12 0x7EB4 +#define PARENT_EGPU_BUS_DEVICE_11 0x7EC4 +#define PARENT_EGPU_BUS_DEVICE_10 0x7EB5 +#define PARENT_EGPU_BUS_DEVICE_09 0x7EC5 +#define PARENT_EGPU_BUS_DEVICE_08 0x7EC6 +#define PARENT_EGPU_BUS_DEVICE_07 0x7EC7 + +#define PARENT_EGPU_BUS_DEVICE_06 0xA73E +#define PARENT_EGPU_BUS_DEVICE_05 0xA76D +#define PARENT_EGPU_BUS_DEVICE_04 0x466E +#define PARENT_EGPU_BUS_DEVICE_03 0x463F +#define PARENT_EGPU_BUS_DEVICE_02 0x462F +#define PARENT_EGPU_BUS_DEVICE_01 0x461F + +#define PARENT_EGPU_BUS_DEVICE_02_08 0X156D +#define PARENT_EGPU_BUS_DEVICE_02_07 0x157E +#define PARENT_EGPU_BUS_DEVICE_02_06 0x156B +#define PARENT_EGPU_BUS_DEVICE_02_05 0x1567 +#define PARENT_EGPU_BUS_DEVICE_02_04 0x1569 +#define PARENT_EGPU_BUS_DEVICE_02_03 0x151B +#define PARENT_EGPU_BUS_DEVICE_02_02 0x1549 +#define PARENT_EGPU_BUS_DEVICE_02_01 0x1513 //***************************************************************************** // Function: isTB3DeviceID @@ -103,33 +118,51 @@ extern "C" { EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID) { NvU32 index; - NvU16 tb3DeviceIDList[]={ BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01, - BUS_DEVICE_ID_TB3_02, - BUS_DEVICE_ID_TB3_03, - BUS_DEVICE_ID_TB3_04, - BUS_DEVICE_ID_TB3_05, - BUS_DEVICE_ID_TB3_06, - BUS_DEVICE_ID_TB3_07, - BUS_DEVICE_ID_TB3_08, - BUS_DEVICE_ID_TB3_09, - BUS_DEVICE_ID_TB3_10, - BUS_DEVICE_ID_ICELAKE_TB3_01, - BUS_DEVICE_ID_ICELAKE_TB3_02, - BUS_DEVICE_ID_ICELAKE_TB3_03, - BUS_DEVICE_ID_ICELAKE_TB3_04, - BUS_DEVICE_ID_ICELAKE_TB3_05, - BUS_DEVICE_ID_ICELAKE_TB3_06, - BUS_DEVICE_ID_TIGERLAKE_TB3_01, - BUS_DEVICE_ID_TIGERLAKE_TB3_02, - BUS_DEVICE_ID_TIGERLAKE_TB3_03, - BUS_DEVICE_ID_TIGERLAKE_TB3_04, - BUS_DEVICE_ID_TIGERLAKE_TB3_05, - BUS_DEVICE_ID_TIGERLAKE_TB3_06, - BUS_DEVICE_ID_TIGERLAKE_TB3_07, - BUS_DEVICE_ID_TIGERLAKE_TB3_08, - BUS_DEVICE_ID_TIGERLAKE_TB3_09, - BUS_DEVICE_ID_TIGERLAKE_TB3_10 - }; + NvU16 tb3DeviceIDList[]={ PARENT_EGPU_BUS_DEVICE_01, + PARENT_EGPU_BUS_DEVICE_02, + PARENT_EGPU_BUS_DEVICE_03, + PARENT_EGPU_BUS_DEVICE_04, + PARENT_EGPU_BUS_DEVICE_05, + PARENT_EGPU_BUS_DEVICE_06, + PARENT_EGPU_BUS_DEVICE_07, + PARENT_EGPU_BUS_DEVICE_08, + PARENT_EGPU_BUS_DEVICE_09, + PARENT_EGPU_BUS_DEVICE_10, + PARENT_EGPU_BUS_DEVICE_11, + PARENT_EGPU_BUS_DEVICE_12, + PARENT_EGPU_BUS_DEVICE_13, + PARENT_EGPU_BUS_DEVICE_14, + PARENT_EGPU_BUS_DEVICE_15, + PARENT_EGPU_BUS_DEVICE_16, + PARENT_EGPU_BUS_DEVICE_17, + PARENT_EGPU_BUS_DEVICE_18, + PARENT_EGPU_BUS_DEVICE_19, + PARENT_EGPU_BUS_DEVICE_20, + PARENT_EGPU_BUS_DEVICE_21, + PARENT_EGPU_BUS_DEVICE_22, + PARENT_EGPU_BUS_DEVICE_23, + PARENT_EGPU_BUS_DEVICE_24, + PARENT_EGPU_BUS_DEVICE_25, + PARENT_EGPU_BUS_DEVICE_26, + PARENT_EGPU_BUS_DEVICE_27, + PARENT_EGPU_BUS_DEVICE_28, + PARENT_EGPU_BUS_DEVICE_29, + PARENT_EGPU_BUS_DEVICE_30, + PARENT_EGPU_BUS_DEVICE_31, + PARENT_EGPU_BUS_DEVICE_32, + PARENT_EGPU_BUS_DEVICE_33, + PARENT_EGPU_BUS_DEVICE_34, + PARENT_EGPU_BUS_DEVICE_35, + PARENT_EGPU_BUS_DEVICE_36, + PARENT_EGPU_BUS_DEVICE_37, + PARENT_EGPU_BUS_DEVICE_38, + PARENT_EGPU_BUS_DEVICE_39, + PARENT_EGPU_BUS_DEVICE_40, + PARENT_EGPU_BUS_DEVICE_41, + PARENT_EGPU_BUS_DEVICE_42, + PARENT_EGPU_BUS_DEVICE_43 + }; + for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++) { if (deviceID == tb3DeviceIDList[index]) @@ -161,11 +194,14 @@ EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID) EGPU_INLINE NvBool isTB2DeviceID(NvU16 deviceID) { NvU32 index; - NvU16 tb2DeviceIDList[]={ BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02, - BUS_DEVICE_ID_TB2_03, BUS_DEVICE_ID_TB2_04, - BUS_DEVICE_ID_TB2_05, BUS_DEVICE_ID_TB2_06, - BUS_DEVICE_ID_TB2_08, BUS_DEVICE_ID_TB2_09, - BUS_DEVICE_ID_TB2_10 + NvU16 tb2DeviceIDList[]={ PARENT_EGPU_BUS_DEVICE_02_01, + PARENT_EGPU_BUS_DEVICE_02_02, + PARENT_EGPU_BUS_DEVICE_02_03, + PARENT_EGPU_BUS_DEVICE_02_04, + PARENT_EGPU_BUS_DEVICE_02_05, + PARENT_EGPU_BUS_DEVICE_02_06, + PARENT_EGPU_BUS_DEVICE_02_07, + PARENT_EGPU_BUS_DEVICE_02_08 }; for (index = 0; index < (sizeof(tb2DeviceIDList)/sizeof(NvU16)); index++) { diff --git a/src/common/inc/swref/published/ampere/ga100/hwproject.h b/src/common/inc/swref/published/ampere/ga100/hwproject.h new file mode 100644 index 000000000..21c6b4538 --- /dev/null +++ b/src/common/inc/swref/published/ampere/ga100/hwproject.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __ga100_hwproject_h__ +#define __ga100_hwproject_h__ + +#define NV_SCAL_LITTER_NUM_FBPAS 24 + +#endif // __ga100_hwproject_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fb.h b/src/common/inc/swref/published/hopper/gh100/dev_fb.h index e40d088f0..24df1cd80 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_fb.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_fb.h @@ -20,7 +20,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - + #ifndef __gh100_dev_fb_h_ #define __gh100_dev_fb_h_ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */ @@ -29,4 +29,5 @@ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */ + #endif // __gh100_dev_fb_h_ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fbpa.h b/src/common/inc/swref/published/hopper/gh100/dev_fbpa.h new file mode 100644 index 000000000..e98d15470 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_fbpa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_fbpa_h_ +#define __gh100_dev_fbpa_h_ + +#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 4 /* */ +#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x009025A0+(i)*4) /* RW-4A */ +#endif // __gh100_dev_fbpa_h_ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_gsp.h b/src/common/inc/swref/published/hopper/gh100/dev_gsp.h index c598d2b1a..61eb8014c 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_gsp.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_gsp.h @@ -31,4 +31,22 @@ #define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */ #define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */ #define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */ +#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMC__SIZE_1 8 /* */ +#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */ +#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */ +#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMD__SIZE_1 8 /* */ +#define NV_PGSP_EMEMD_DATA 31:0 /* RWXVF */ + #endif // __gh100_dev_gsp_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_nv_xpl.h b/src/common/inc/swref/published/hopper/gh100/dev_nv_xpl.h new file mode 100644 index 000000000..5eff7477b --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_nv_xpl.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_nv_xpl_h_ +#define __gh100_dev_nv_xpl_h_ +#define NV_XPL_DL_ERR_COUNT_RBUF 0x00000a54 /* R--4R */ +#define NV_XPL_DL_ERR_COUNT_RBUF__PRIV_LEVEL_MASK 0x00000b08 /* */ +#define NV_XPL_DL_ERR_COUNT_RBUF_CORR_ERR 15:0 /* R-EVF */ +#define NV_XPL_DL_ERR_COUNT_RBUF_CORR_ERR_INIT 0x0000 /* R-E-V */ +#define NV_XPL_DL_ERR_COUNT_RBUF_UNCORR_ERR 31:16 /* R-EVF */ +#define NV_XPL_DL_ERR_COUNT_RBUF_UNCORR_ERR_INIT 0x0000 /* R-E-V */ +#define NV_XPL_DL_ERR_COUNT_SEQ_LUT 0x00000a58 /* R--4R */ +#define NV_XPL_DL_ERR_COUNT_SEQ_LUT__PRIV_LEVEL_MASK 0x00000b08 /* */ +#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_CORR_ERR 15:0 /* R-EVF */ +#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_CORR_ERR_INIT 0x0000 /* R-E-V */ +#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_UNCORR_ERR 31:16 /* R-EVF */ +#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_UNCORR_ERR_INIT 0x0000 /* R-E-V */ + +#define NV_XPL_DL_ERR_RESET 0x00000a5c /* RW-4R */ +#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT 0:0 /* RWCVF */ +#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT_DONE 0x0 /* RWC-V */ +#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT_PENDING 0x1 /* -W--T */ +#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT 1:1 /* RWCVF */ +#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT_DONE 0x0 /* RWC-V */ +#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT_PENDING 0x1 /* -W--T */ +#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT 16:16 /* RWCVF */ +#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT_DONE 0x0 /* RWC-V */ +#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT_PENDING 0x1 /* -W--T */ +#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT 17:17 /* RWCVF */ +#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT_DONE 0x0 /* RWC-V */ +#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT_PENDING 0x1 /* -W--T */ +#endif // __gh100_dev_nv_xpl_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h index db96d0b6e..eb475eef4 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h @@ -24,4 +24,7 @@ #ifndef __gh100_dev_xtl_ep_pri_h__ #define __gh100_dev_xtl_ep_pri_h__ #define NV_EP_PCFGM 0x92FFF:0x92000 /* RW--D */ + +#define NV_XTL_EP_PRI_DED_ERROR_STATUS 0x0000043C /* RW-4R */ +#define NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS 0x000003C8 /* RW-4R */ #endif // __gh100_dev_xtl_ep_pri_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/hwproject.h b/src/common/inc/swref/published/hopper/gh100/hwproject.h index 4fda40527..7725d0e95 100644 --- a/src/common/inc/swref/published/hopper/gh100/hwproject.h +++ b/src/common/inc/swref/published/hopper/gh100/hwproject.h @@ -21,3 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ #define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52 +#define NV_XPL_BASE_ADDRESS 540672 +#define NV_XTL_BASE_ADDRESS 593920 +#define NV_FBPA_PRI_STRIDE 16384 diff --git a/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h b/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h index ff1576dbe..897fd9623 100644 --- a/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h +++ b/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h @@ -47,5 +47,17 @@ #define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT 3:3 #define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT_PENDING 0x1 #define NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT 0xbadf0200 + +#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT 0x0010f364 /* RW-4R */ +#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */ +#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */ +#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */ +#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */ + +#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT 0x0010f37c /* RW-4R */ +#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */ +#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */ +#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */ +#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */ #endif // __gh100_pri_nv_xal_ep_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h index a4ac4bf5d..2117acae7 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -635,4 +635,7 @@ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT 28:28 /* RWIVF */ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_SCRATCH_WARM 0x000007c0 /* RW-4R */ +#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA 31:0 /* RWEVF */ +#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */ #endif // __ls10_dev_nvlipt_lnk_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h b/src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h new file mode 100644 index 000000000..93d2c403a --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_ptop_discovery_ip_h__ +#define __ls10_ptop_discovery_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */ +#endif // __ls10_ptop_discovery_ip_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_fb.h b/src/common/inc/swref/published/turing/tu102/dev_fb.h index 4c9fb4632..be959b0d4 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_fb.h +++ b/src/common/inc/swref/published/turing/tu102/dev_fb.h @@ -38,4 +38,25 @@ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + #endif // __tu102_dev_fb_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_fbpa.h b/src/common/inc/swref/published/turing/tu102/dev_fbpa.h new file mode 100644 index 000000000..c1465c953 --- /dev/null +++ b/src/common/inc/swref/published/turing/tu102/dev_fbpa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __tu102_dev_fbpa_h_ +#define __tu102_dev_fbpa_h_ + +#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 2 /* */ +#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x00900488+(i)*4) /* RW-4A */ +#endif // __tu102_dev_fbpa_h_ diff --git a/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h b/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h index 51f6c4725..4f89a4ebc 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h +++ b/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h @@ -24,6 +24,7 @@ #ifndef __tu102_dev_gc6_island_h__ #define __tu102_dev_gc6_island_h__ +#define NV_PGC6 0x118fff:0x118000 /* RW--D */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ diff --git a/src/common/inc/swref/published/turing/tu102/dev_gsp.h b/src/common/inc/swref/published/turing/tu102/dev_gsp.h index 7a00e288d..0e6e4a360 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_gsp.h +++ b/src/common/inc/swref/published/turing/tu102/dev_gsp.h @@ -38,5 +38,22 @@ #define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */ #define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */ #define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */ +#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMC__SIZE_1 4 /* */ +#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */ +#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */ +#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMD__SIZE_1 4 /* */ +#define NV_PGSP_EMEMD_DATA 31:0 /* RW-VF */ #endif // __tu102_dev_gsp_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_ltc.h b/src/common/inc/swref/published/turing/tu102/dev_ltc.h new file mode 100644 index 000000000..0206ed7e7 --- /dev/null +++ b/src/common/inc/swref/published/turing/tu102/dev_ltc.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __tu102_dev_ltc_h_ +#define __tu102_dev_ltc_h_ + +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */ +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */ +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */ +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */ +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */ + +#endif // __tu102_dev_ltc_h_ diff --git a/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h b/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h index 701cb2da8..d6f4ca4f3 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h +++ b/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h @@ -28,6 +28,10 @@ #define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */ #define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */ #define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */ #define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */ #define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */ diff --git a/src/common/inc/swref/published/turing/tu102/hwproject.h b/src/common/inc/swref/published/turing/tu102/hwproject.h index 26bb4a548..d329a883e 100644 --- a/src/common/inc/swref/published/turing/tu102/hwproject.h +++ b/src/common/inc/swref/published/turing/tu102/hwproject.h @@ -25,5 +25,9 @@ #define __tu102_hwproject_h__ #define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 47 +#define NV_SCAL_LITTER_NUM_FBPAS 16 +#define NV_FBPA_PRI_STRIDE 16384 +#define NV_LTC_PRI_STRIDE 8192 +#define NV_LTS_PRI_STRIDE 512 #endif // __tu102_hwproject_h__ diff --git a/src/common/nvlink/interface/nvlink.h b/src/common/nvlink/interface/nvlink.h index 59e76cd2e..b93480a26 100644 --- a/src/common/nvlink/interface/nvlink.h +++ b/src/common/nvlink/interface/nvlink.h @@ -439,6 +439,11 @@ NvlStatus nvlink_lib_register_link(nvlink_device *dev, nvlink_link *link); */ NvlStatus nvlink_lib_unregister_link(nvlink_link *link); +/* +* Gets number of devices with type deviceType +*/ +NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices); + /************************************************************************************************/ /******************************* NVLink link management functions *******************************/ diff --git a/src/common/nvlink/interface/nvlink_export.h b/src/common/nvlink/interface/nvlink_export.h index 471ec8380..e7deaff02 100644 --- a/src/common/nvlink/interface/nvlink_export.h +++ b/src/common/nvlink/interface/nvlink_export.h @@ -46,6 +46,11 @@ NvlStatus nvlink_lib_unload(void); */ NvlStatus nvlink_lib_ioctl_ctrl(nvlink_ioctrl_params *ctrl_params); +/* +* Gets number of devices with type deviceType +*/ +NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices); + #ifdef __cplusplus } #endif diff --git a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c index 06e674963..9f1a66488 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c @@ -198,3 +198,48 @@ nvlink_lib_is_registerd_device_with_reduced_config(void) return bIsReducedConfg; } + +/* +* Get the number of devices that have the device type deviceType +*/ +NvlStatus +nvlink_lib_return_device_count_by_type +( + NvU32 deviceType, + NvU32 *numDevices +) +{ + NvlStatus lock_status = NVL_SUCCESS; + nvlink_device *dev = NULL; + NvU32 device_count = 0; + + if (nvlink_lib_is_initialized()) + { + // Acquire top-level lock + lock_status = nvlink_lib_top_lock_acquire(); + if (lock_status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire top-level lock\n", + __FUNCTION__)); + + return lock_status; + } + + // Top-level lock is now acquired + + // Loop through device list + FOR_EACH_DEVICE_REGISTERED(dev, nvlinkLibCtx.nv_devicelist_head, node) + { + if (dev->type == deviceType) + { + device_count++; + } + } + + // Release top-level lock + nvlink_lib_top_lock_release(); + } + *numDevices = device_count; + return NVL_SUCCESS; +} diff --git a/src/common/nvswitch/common/inc/soe/soeififr.h b/src/common/nvswitch/common/inc/soe/soeififr.h index b7504ce3f..a5dd5b8bb 100644 --- a/src/common/nvswitch/common/inc/soe/soeififr.h +++ b/src/common/nvswitch/common/inc/soe/soeififr.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -37,6 +37,17 @@ enum RM_SOE_IFR_BBX_SHUTDOWN, RM_SOE_IFR_BBX_SXID_ADD, RM_SOE_IFR_BBX_SXID_GET, + RM_SOE_IFR_BBX_DATA_GET, +}; + +enum +{ + RM_SOE_IFR_BBX_GET_NONE, + RM_SOE_IFR_BBX_GET_SXID, + RM_SOE_IFR_BBX_GET_SYS_INFO, + RM_SOE_IFR_BBX_GET_TIME_INFO, + RM_SOE_IFR_BBX_GET_TEMP_DATA, + RM_SOE_IFR_BBX_GET_TEMP_SAMPLES, }; typedef struct @@ -75,6 +86,14 @@ typedef struct RM_FLCN_U64 dmaHandle; } RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS; +typedef struct +{ + NvU8 cmdType; + NvU32 sizeInBytes; + RM_FLCN_U64 dmaHandle; + NvU8 dataType; +} RM_SOE_IFR_CMD_BBX_GET_DATA_PARAMS; + typedef union { NvU8 cmdType; @@ -82,6 +101,7 @@ typedef union RM_SOE_IFR_CMD_BBX_INIT_PARAMS bbxInit; RM_SOE_IFR_CMD_BBX_SXID_ADD_PARAMS bbxSxidAdd; RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS bbxSxidGet; + RM_SOE_IFR_CMD_BBX_GET_DATA_PARAMS bbxDataGet; } RM_SOE_IFR_CMD; // entry of getSxid @@ -99,4 +119,81 @@ typedef struct RM_SOE_BBX_SXID_ENTRY sxidLast[INFOROM_BBX_OBJ_XID_ENTRIES]; } RM_SOE_BBX_GET_SXID_DATA; +// NVSwitch system version information returning with the command GET_SYS_INFO +typedef struct +{ + NvU32 driverLo; //Driver Version Low 32 bits + NvU16 driverHi; //Driver Version High 16 bits + NvU32 vbiosVersion; //VBIOS Version + NvU8 vbiosVersionOem; //VBIOS OEM Version byte + NvU8 osType; //OS Type (UNIX/WIN/WIN2K/WIN9x/OTHER) + NvU32 osVersion; //OS Version (Build|MINOR|MAJOR) +} RM_SOE_BBX_GET_SYS_INFO_DATA; + +// NVSwitch time information returning with the command GET_TIME_INFO +typedef struct +{ + NvU32 timeStart; //Timestamp (EPOCH) when the driver was loaded on the GPU for the first time + NvU32 timeEnd; //Timestamp (EPOCH) when the data was last flushed + NvU32 timeRun; //Amount of time (in seconds) driver was loaded, and GPU has run + NvU32 time24Hours; //Timestamp (EPOCH) of when the first 24 operational hours is hit + NvU32 time100Hours; //Timestamp (EPOCH) of when the first 100 operational hours is hit +} RM_SOE_BBX_GET_TIME_INFO_DATA; + +#define RM_SOE_BBX_TEMP_DAY_ENTRIES 5 +#define RM_SOE_BBX_TEMP_WEEK_ENTRIES 5 +#define RM_SOE_BBX_TEMP_MNT_ENTRIES 5 +#define RM_SOE_BBX_TEMP_ALL_ENTRIES 5 +#define RM_SOE_BBX_TEMP_SUM_HOUR_ENTRIES 23 +#define RM_SOE_BBX_TEMP_SUM_DAY_ENTRIES 5 +#define RM_SOE_BBX_TEMP_SUM_MNT_ENTRIES 3 +#define RM_SOE_BBX_TEMP_HISTOGRAM_THLD_ENTRIES 20 +#define RM_SOE_BBX_TEMP_HISTOGRAM_TIME_ENTRIES 21 +#define RM_SOE_BBX_TEMP_HOURLY_MAX_ENTRIES 168 +#define RM_SOE_BBX_TEMP_COMPRESS_BUFFER_ENTRIES 1096 +#define RM_SOE_BBX_NUM_COMPRESSION_PERIODS 8 + +// NVSwitch Temperature Entry +typedef struct +{ + NvU16 value; //Temperature (SFXP 9.7 format in Celsius) + NvU32 timestamp; //Timestamp (EPOCH) of when the entry is recorded +} RM_SOE_BBX_TEMP_ENTRY; + +// NVSwitch Temperature Data returning with the command GET_TEMP_DATA +typedef struct +{ + NvU32 tempMaxDayIdx; + RM_SOE_BBX_TEMP_ENTRY tempMaxDay[RM_SOE_BBX_TEMP_DAY_ENTRIES]; + NvU32 tempMaxWeekIdx; + RM_SOE_BBX_TEMP_ENTRY tempMaxWeek[RM_SOE_BBX_TEMP_WEEK_ENTRIES]; + NvU32 tempMaxMntIdx; + RM_SOE_BBX_TEMP_ENTRY tempMaxMnt[RM_SOE_BBX_TEMP_MNT_ENTRIES]; + NvU32 tempMaxAllIdx; + RM_SOE_BBX_TEMP_ENTRY tempMaxAll[RM_SOE_BBX_TEMP_ALL_ENTRIES]; + NvU32 tempMinDayIdx; + RM_SOE_BBX_TEMP_ENTRY tempMinDay[RM_SOE_BBX_TEMP_DAY_ENTRIES]; + NvU32 tempMinWeekIdx; + RM_SOE_BBX_TEMP_ENTRY tempMinWeek[RM_SOE_BBX_TEMP_WEEK_ENTRIES]; + NvU32 tempMinMntIdx; + RM_SOE_BBX_TEMP_ENTRY tempMinMnt[RM_SOE_BBX_TEMP_MNT_ENTRIES]; + NvU32 tempMinAllIdx; + RM_SOE_BBX_TEMP_ENTRY tempMinAll[RM_SOE_BBX_TEMP_ALL_ENTRIES]; + NvU32 tempSumDelta; + NvU32 tempSumHour[RM_SOE_BBX_TEMP_SUM_HOUR_ENTRIES]; + NvU32 tempSumDay[RM_SOE_BBX_TEMP_SUM_DAY_ENTRIES]; + NvU32 tempSumMnt[RM_SOE_BBX_TEMP_SUM_MNT_ENTRIES]; + NvU32 tempHistogramThld[RM_SOE_BBX_TEMP_HISTOGRAM_THLD_ENTRIES]; + NvU32 tempHistogramTime[RM_SOE_BBX_TEMP_HISTOGRAM_TIME_ENTRIES]; + RM_SOE_BBX_TEMP_ENTRY tempHourlyMaxSample[RM_SOE_BBX_TEMP_HOURLY_MAX_ENTRIES]; +} RM_SOE_BBX_GET_TEMP_DATA; + +// NVSwitch Temperature Compressed Samples returning with the command GET_TEMP_SAMPLES +typedef struct +{ + NvU32 compressionPeriodIdx; + NvU32 compressionPeriod[RM_SOE_BBX_NUM_COMPRESSION_PERIODS]; + RM_SOE_BBX_TEMP_ENTRY tempCompressionBuffer[RM_SOE_BBX_TEMP_COMPRESS_BUFFER_ENTRIES]; +} RM_SOE_BBX_GET_TEMP_SAMPLES; + #endif // _SOEIFIFR_H_ diff --git a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h index 7234bb311..bc3567144 100644 --- a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h +++ b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h @@ -830,6 +830,7 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN = 10006, NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007, NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008, + NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE = 10009, NVSWITCH_ERR_HW_HOST_LAST, @@ -2974,6 +2975,197 @@ typedef struct } NVSWITCH_GET_SXIDS_PARAMS; /* + * CTRL_NVSWITCH_GET_SYS_INFO + * + * Control to get the NVSwitch system version information from inforom cache + * + * Parameters: + * driverLo [OUT] + * The driver version low 32 bits. Example: driverLo = 54531 (Driver 545.31) + * driverHi [OUT] + * The driver version high 16 bits + * vbiosVersion [OUT] + * The vbios version number. Example: vbiosVersion=0x96104100 (release 96.10.41.00) + * vbiosVersionOem [OUT] + * The vbios OEM version byte. + * osType [OUT] + * The OS type. Example: osType=0x05 (UNIX) + * osVersion [OUT] + * The OS version number. [BUILD[31:16]|MINOR[15:8]|MAJOR[7:0]] + */ + +typedef struct +{ + NvU32 driverLo; + NvU16 driverHi; + NvU32 vbiosVersion; + NvU8 vbiosVersionOem; + NvU8 osType; + NvU32 osVersion; +} NVSWITCH_GET_SYS_INFO_PARAMS; + +/* + * CTRL_NVSWITCH_GET_TIME_INFO + * + * Control to get the NVSwitch time information from inforom cache + * + * Parameters: + * timeStart [OUT] + * The timestamp (EPOCH) when driver load onto the NVSwitch for the 1st time + * timeEnd [OUT] + * The timestamp (EPOCH) when the data was last flushed + * timeRun [OUT] + * The amount of time (in seconds) driver was loaded/running + * time24Hours [OUT] + * The timestamp (EPOCH) when the first 24 operational hours is hit + * time100Hours [OUT] + * The timestamp (EPOCH) when the first 100 operational hours is hit + */ + +typedef struct +{ + NvU32 timeStart; + NvU32 timeEnd; + NvU32 timeRun; + NvU32 time24Hours; + NvU32 time100Hours; +} NVSWITCH_GET_TIME_INFO_PARAMS; + +#define NVSWITCH_TEMP_DAY_ENTRIES 5 +#define NVSWITCH_TEMP_WEEK_ENTRIES 5 +#define NVSWITCH_TEMP_MNT_ENTRIES 5 +#define NVSWITCH_TEMP_ALL_ENTRIES 5 +#define NVSWITCH_TEMP_SUM_HOUR_ENTRIES 23 +#define NVSWITCH_TEMP_SUM_DAY_ENTRIES 5 +#define NVSWITCH_TEMP_SUM_MNT_ENTRIES 3 +#define NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES 20 +#define NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES 21 +#define NVSWITCH_TEMP_HOURLY_MAX_ENTRIES 168 + +/* + * NVSWITCH_TEMP_ENTRY + * + * This structure represents the NVSwitch TEMP with its timestamp. + * + * value + * This parameter specifies the NVSwitch Temperature + * (SFXP 9.7 format in Celsius). + * + * timestamp + * This parameter specifies the timestamp (EPOCH) of the entry. + */ +typedef struct +{ + NvU16 value; + NvU32 timestamp; +} NVSWITCH_TEMP_ENTRY; + +/* + * CTRL_NVSWITCH_GET_TEMP_DATA + * + * Control to get the NVSwitch device historical temperature information from inforom cache + * + * Parameters: + * tempMaxDayIdx [OUT] + * The current index to the maximum day temperature array + * tempMaxDay[] [OUT] + * The maximum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days + * tempMaxWeekIdx [OUT] + * The current index to the maximum week temperature array + * tempMaxWeek[] [OUT] + * The maximum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks + * tempMaxMntIdx [OUT] + * The current index to the maximum month temperature array + * tempMaxMnt[] [OUT] + * The maximum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months + * tempMaxAllIdx [OUT] + * The current index to the maximum temperature array + * tempMaxAll[] [OUT] + * The maximum temperature array for the device + * tempMinDayIdx [OUT] + * The current index to the minimum day temperature array + * tempMinDay[] [OUT] + * The minimum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days + * tempMinWeekIdx [OUT] + * The current index to the minimum week temperature array + * tempMinWeek[] [OUT] + * The minimum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks + * tempMinMntIdx [OUT] + * The current index to the minimum month temperature array + * tempMinMnt[] [OUT] + * The minimum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months + * tempMinAllIdx [OUT] + * The current index to the minimum temperature array + * tempMinAll[] [OUT] + * The minimum temperature array for the device + * tempSumDelta [OUT] + * The total sum of temperature change in 0.1C granularity + * tempSumHour[] [OUT] + * The moving average of temperature per hour, for last NVSWITCH_TEMP_SUM_HOUR_ENTRIES hours + * tempSumDay[] [OUT] + * The moving average of temperature per day, for last NVSWITCH_TEMP_SUM_DAY_ENTRIES days + * tempSumMnt[] [OUT] + * The moving average of temperature per month, for last NVSWITCH_TEMP_SUM_MNT_ENTRIES months + * tempHistogramThld[] [OUT] + * The histogram of temperature crossing various thresholds (5/10/15/.../95/100) + * tempHistogramTime[] [OUT] + * The histogram of time was in various temperature ranges (0..5/5..10/.../100..) + * tempHourlyMaxSample[] [OUT] + * The maximum hourly temperature array for the device + */ + +typedef struct +{ + NvU32 tempMaxDayIdx; + NVSWITCH_TEMP_ENTRY tempMaxDay[NVSWITCH_TEMP_DAY_ENTRIES]; + NvU32 tempMaxWeekIdx; + NVSWITCH_TEMP_ENTRY tempMaxWeek[NVSWITCH_TEMP_WEEK_ENTRIES]; + NvU32 tempMaxMntIdx; + NVSWITCH_TEMP_ENTRY tempMaxMnt[NVSWITCH_TEMP_MNT_ENTRIES]; + NvU32 tempMaxAllIdx; + NVSWITCH_TEMP_ENTRY tempMaxAll[NVSWITCH_TEMP_ALL_ENTRIES]; + NvU32 tempMinDayIdx; + NVSWITCH_TEMP_ENTRY tempMinDay[NVSWITCH_TEMP_DAY_ENTRIES]; + NvU32 tempMinWeekIdx; + NVSWITCH_TEMP_ENTRY tempMinWeek[NVSWITCH_TEMP_WEEK_ENTRIES]; + NvU32 tempMinMntIdx; + NVSWITCH_TEMP_ENTRY tempMinMnt[NVSWITCH_TEMP_MNT_ENTRIES]; + NvU32 tempMinAllIdx; + NVSWITCH_TEMP_ENTRY tempMinAll[NVSWITCH_TEMP_ALL_ENTRIES]; + NvU32 tempSumDelta; + NvU32 tempSumHour[NVSWITCH_TEMP_SUM_HOUR_ENTRIES]; + NvU32 tempSumDay[NVSWITCH_TEMP_SUM_DAY_ENTRIES]; + NvU32 tempSumMnt[NVSWITCH_TEMP_SUM_MNT_ENTRIES]; + NvU32 tempHistogramThld[NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES]; + NvU32 tempHistogramTime[NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES]; + NVSWITCH_TEMP_ENTRY tempHourlyMaxSample[NVSWITCH_TEMP_HOURLY_MAX_ENTRIES]; +} NVSWITCH_GET_TEMP_DATA_PARAMS; + +#define NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES 1096 +#define NVSWITCH_NUM_COMPRESSION_PERIODS 8 + +/* + * CTRL_NVSWITCH_GET_TEMP_DATA + * + * Control to get the NVSwitch device temperature information from inforom cache + * + * Parameters: + * compressionPeriodIdx [OUT] + * The current index to the sample period array + * compressionPeriod[] [OUT] + * The samples period array (seconds) + * tempCompressionBuffer[] [OUT] + * The temperature array sampling at a specific period in compressionPeriod[] + */ + +typedef struct +{ + NvU32 compressionPeriodIdx; + NvU32 compressionPeriod[NVSWITCH_NUM_COMPRESSION_PERIODS]; + NVSWITCH_TEMP_ENTRY tempCompressionBuffer[NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES]; +} NVSWITCH_GET_TEMP_SAMPLES_PARAMS; + +/* * CTRL_NVSWITCH_GET_FOM_VALUES * This command gives the FOM values to MODS * @@ -3848,6 +4040,10 @@ typedef struct #define CTRL_NVSWITCH_RESERVED_11 0x55 #define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x56 #define CTRL_NVSWITCH_GET_POWER 0x57 +#define CTRL_NVSWITCH_GET_SYS_INFO 0x58 +#define CTRL_NVSWITCH_GET_TIME_INFO 0x59 +#define CTRL_NVSWITCH_GET_TEMP_DATA 0x60 +#define CTRL_NVSWITCH_GET_TEMP_SAMPLES 0x61 #ifdef __cplusplus } diff --git a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h index d1294124c..a9e060147 100644 --- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h @@ -158,6 +158,7 @@ _op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \ _op(NvlStatus, nvswitch_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS * params), _arch) \ + _op(NvlStatus, nvswitch_bbx_get_data, (nvswitch_device *device, NvU8 dataType, void * params), _arch) \ _op(NvlStatus, nvswitch_smbpbi_alloc, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_smbpbi_post_init_hal, (nvswitch_device *device), _arch) \ _op(void, nvswitch_smbpbi_destroy_hal, (nvswitch_device *device), _arch) \ @@ -213,6 +214,7 @@ _op(void, nvswitch_reset_persistent_link_hw_state, (nvswitch_device *device, NvU32 linkNumber), _arch)\ _op(void, nvswitch_store_topology_information, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(void, nvswitch_init_lpwr_regs, (nvlink_link *link), _arch) \ + _op(void, nvswitch_program_l1_scratch_reg, (nvswitch_device *device, NvU32 linkNumber), _arch) \ _op(NvlStatus, nvswitch_set_training_mode, (nvswitch_device *device), _arch) \ _op(NvU32, nvswitch_get_sublink_width, (nvswitch_device *device, NvU32 linkNumber), _arch) \ _op(NvBool, nvswitch_i2c_is_device_access_allowed, (nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead), _arch) \ @@ -234,6 +236,7 @@ _op(NvlStatus, nvswitch_ctrl_therm_read_power, (nvswitch_device *device, NVSWITCH_GET_POWER_PARAMS *info), _arch) \ _op(NvBool, nvswitch_does_link_need_termination_enabled, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvlStatus, nvswitch_link_termination_setup, (nvswitch_device *device, nvlink_link *link), _arch) \ + _op(NvlStatus, nvswitch_check_io_sanity, (nvswitch_device *device), _arch) \ #define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \ _op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \ diff --git a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h index 7ca5dd415..b9323d58e 100644 --- a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -184,6 +184,7 @@ NvlStatus nvswitch_inforom_bbx_add_sxid(nvswitch_device *device, NvU32 data1, NvU32 data2); NvlStatus nvswitch_inforom_bbx_get_sxid(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params); +NvlStatus nvswitch_inforom_bbx_get_data(nvswitch_device *device, NvU8 dataType, void *params); // InfoROM DEM APIs NvlStatus nvswitch_inforom_dem_load(nvswitch_device *device); diff --git a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h index bf12d836f..77b161254 100644 --- a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -169,4 +169,12 @@ nvswitch_bbx_get_sxid_lr10 NVSWITCH_GET_SXIDS_PARAMS * params ); +NvlStatus +nvswitch_bbx_get_data_lr10 +( + nvswitch_device *device, + NvU8 dataType, + void *params +); + #endif //_INFOROM_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/lr10/lr10.h b/src/common/nvswitch/kernel/inc/lr10/lr10.h index f95812284..c08071f86 100644 --- a/src/common/nvswitch/kernel/inc/lr10/lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/lr10.h @@ -583,9 +583,12 @@ typedef struct NvBool bDisabledRemoteEndLinkMaskCached; } lr10_device; +#define NVSWITCH_NUM_DEVICES_PER_DELTA_LR10 6 + typedef struct { NvU32 switchPhysicalId; - NvU64 linkMask; + NvU64 accessLinkMask; + NvU64 trunkLinkMask; } lr10_links_connected_to_disabled_remote_end; #define NVSWITCH_GET_CHIP_DEVICE_LR10(_device) \ @@ -649,6 +652,7 @@ void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 void nvswitch_reset_persistent_link_hw_state_lr10(nvswitch_device *device, NvU32 linkNumber); void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link); void nvswitch_init_lpwr_regs_lr10(nvlink_link *link); +void nvswitch_program_l1_scratch_reg_lr10(nvswitch_device *device, NvU32 linkNumber); NvlStatus nvswitch_set_training_mode_lr10(nvswitch_device *device); NvBool nvswitch_i2c_is_device_access_allowed_lr10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); NvU32 nvswitch_get_sublink_width_lr10(nvswitch_device *device,NvU32 linkNumber); diff --git a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h index 7ce0e5c73..627dd128b 100644 --- a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -154,4 +154,11 @@ nvswitch_bbx_get_sxid_ls10 NVSWITCH_GET_SXIDS_PARAMS * params ); +NvlStatus +nvswitch_bbx_get_data_ls10 +( + nvswitch_device *device, + NvU8 dataType, + void *params +); #endif //_INFOROM_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/ls10.h b/src/common/nvswitch/kernel/inc/ls10/ls10.h index 431ca8476..6b8f64b95 100644 --- a/src/common/nvswitch/kernel/inc/ls10/ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/ls10.h @@ -529,10 +529,20 @@ typedef struct { NvBool bLinkErrorsCallBackEnabled; NvBool bLinkStateCallBackEnabled; - NvBool bResetAndDrainRetry; + NvU64 lastRetrainTime; + NvU64 lastLinkUpTime; +} NVLINK_LINK_ERROR_REPORTING_STATE; +typedef struct +{ NVLINK_LINK_ERROR_INFO_ERR_MASKS fatalIntrMask; NVLINK_LINK_ERROR_INFO_ERR_MASKS nonFatalIntrMask; +} NVLINK_LINK_ERROR_REPORTING_DATA; + +typedef struct +{ + NVLINK_LINK_ERROR_REPORTING_STATE state; + NVLINK_LINK_ERROR_REPORTING_DATA data; } NVLINK_LINK_ERROR_REPORTING; typedef struct @@ -834,7 +844,6 @@ typedef const struct #define nvswitch_setup_link_loopback_mode_ls10 nvswitch_setup_link_loopback_mode_lr10 #define nvswitch_link_lane_reversed_ls10 nvswitch_link_lane_reversed_lr10 -#define nvswitch_request_tl_link_state_ls10 nvswitch_request_tl_link_state_lr10 #define nvswitch_i2c_get_port_info_ls10 nvswitch_i2c_get_port_info_lr10 #define nvswitch_i2c_set_hw_speed_mode_ls10 nvswitch_i2c_set_hw_speed_mode_lr10 @@ -929,6 +938,7 @@ void nvswitch_corelib_clear_link_state_lr10(nvlink_link *link); NvlStatus nvswitch_corelib_set_dl_link_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); NvlStatus nvswitch_corelib_set_tx_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); void nvswitch_init_lpwr_regs_ls10(nvlink_link *link); +void nvswitch_program_l1_scratch_reg_ls10(nvswitch_device *device, NvU32 linkNumber); NvlStatus nvswitch_minion_service_falcon_interrupts_ls10(nvswitch_device *device, NvU32 instance); @@ -986,6 +996,7 @@ NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 lin void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); NvlStatus nvswitch_ctrl_get_board_part_number_ls10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p); void nvswitch_create_deferred_link_state_check_task_ls10(nvswitch_device *device, NvU32 nvlipt_instance, NvU32 link); +NvlStatus nvswitch_request_tl_link_state_ls10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync); // // SU generated functions diff --git a/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h b/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h index e698a3631..c2468bee1 100644 --- a/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -46,6 +46,9 @@ typedef enum _MINION_STATUS MINION_ALARM_BUSY = 80, } MINION_STATUS; + #define LINKSTATUS_RESET 0x0 + #define LINKSTATUS_UNINIT 0x1 + #define LINKSTATUS_LANESHUTDOWN 0x13 #define LINKSTATUS_EMERGENCY_SHUTDOWN 0x29 - #define LINKSTATUS_INITPHASE1 0x24 + #define LINKSTATUS_ACTIVE_PENDING 0x25 #endif // _MINION_NVLINK_DEFINES_PUBLIC_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index 53f6e8204..73a877bd4 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -751,7 +751,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, 0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01, - 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a09f8, + 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, 0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, 0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0, 0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00, @@ -1370,7 +1370,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03, 0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801, - 0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00, + 0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00, 0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111, 0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d, 0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28, @@ -1420,7 +1420,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894, 0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999, 0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff, - 0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c, + 0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c, 0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c, 0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0, 0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x979b9cb7, 0x7359186e, 0x8b211603, 0x878da8fe, - 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x269562e0, 0x626d8a06, 0xc3df044b, 0x11ecee8e, + 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x6073f3d9, 0x573ea3ef, 0xf0764322, 0xf8dacef7, + 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0xe0830635, 0xb9c7326b, 0x27f96395, 0x7078f754, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index 5c7f53352..ee028ec7a 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -751,7 +751,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, 0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01, - 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a09f8, + 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, 0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, 0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0, 0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00, @@ -1370,7 +1370,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03, 0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801, - 0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00, + 0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00, 0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111, 0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d, 0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28, @@ -1420,7 +1420,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894, 0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999, 0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff, - 0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c, + 0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c, 0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c, 0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0, 0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x979b9cb7, 0x7359186e, 0x8b211603, 0x878da8fe, - 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x269562e0, 0x626d8a06, 0xc3df044b, 0x11ecee8e, + 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x6073f3d9, 0x573ea3ef, 0xf0764322, 0xf8dacef7, + 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0xe0830635, 0xb9c7326b, 0x27f96395, 0x7078f754, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c b/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c index a92d9ee14..f4432dd40 100644 --- a/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c +++ b/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -130,3 +130,21 @@ nvswitch_inforom_bbx_get_sxid return status; } +NvlStatus +nvswitch_inforom_bbx_get_data +( + nvswitch_device *device, + NvU8 dataType, + void *params +) +{ + NvlStatus status; + + status = device->hal.nvswitch_bbx_get_data(device, dataType, params); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: (type=%d) failed, status=%d\n", __FUNCTION__, dataType, status); + } + + return status; +} diff --git a/src/common/nvswitch/kernel/lr10/inforom_lr10.c b/src/common/nvswitch/kernel/lr10/inforom_lr10.c index c7d3c0e29..8f4c20dce 100644 --- a/src/common/nvswitch/kernel/lr10/inforom_lr10.c +++ b/src/common/nvswitch/kernel/lr10/inforom_lr10.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,7 @@ #include "nvVer.h" #include "regkey_nvswitch.h" #include "inforom/inforom_nvl_v3_nvswitch.h" +#include "soe/soeififr.h" // // TODO: Split individual object hals to their own respective files @@ -1280,3 +1281,14 @@ nvswitch_bbx_get_sxid_lr10 return -NVL_ERR_NOT_SUPPORTED; } +NvlStatus +nvswitch_bbx_get_data_lr10 +( + nvswitch_device *device, + NvU8 dataType, + void *params +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + diff --git a/src/common/nvswitch/kernel/lr10/link_lr10.c b/src/common/nvswitch/kernel/lr10/link_lr10.c index 042933a8c..9456a8639 100644 --- a/src/common/nvswitch/kernel/lr10/link_lr10.c +++ b/src/common/nvswitch/kernel/lr10/link_lr10.c @@ -43,40 +43,68 @@ #include "nvswitch/lr10/dev_nvlipt_ip.h" #include "nvswitch/lr10/dev_nport_ip.h" -#define NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK 8 // This must be incremented if any entries are added to the array below +#define NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK 12 // This must be incremented if any entries are added to the array below lr10_links_connected_to_disabled_remote_end nvswitchDisconnetedRemoteLinkMasks[] = { { - 0x8, // switchPhysicalId - 0x56A000500 //linkMask + 0x8, // switchPhysicalId + 0x56A000500, // accessLinkMask + 0xFF00FF // trunkLinkMask }, { - 0x9, // switchPhysicalId - 0x509009900 //linkMask + 0x9, // switchPhysicalId + 0x509009900, // accessLinkMask + 0xFF00FF // trunkLinkMask }, { - 0xb, // switchPhysicalId - 0x56A000600 //linkMask + 0xa, // switchPhysicalId + 0x0, // accessLinkMask + 0xFF00FF // trunkLinkMask }, { - 0xc, // switchPhysicalId - 0x4A9009400 //linkMask + 0xb, // switchPhysicalId + 0x56A000600, // accessLinkMask + 0xFF00FF // trunkLinkMask }, { - 0x18, // switchPhysicalId - 0x56A000500 //linkMask + 0xc, // switchPhysicalId + 0x4A9009400, // accessLinkMask + 0xFF00FF // trunkLinkMask }, { - 0x19, // switchPhysicalId - 0x509009900 //linkMask + 0xd, // switchPhysicalId + 0x0, // accessLinkMask + 0xFF00FF // trunkLinkMask }, { - 0x1b, // switchPhysicalId - 0x56A000600 //linkMask + 0x18, // switchPhysicalId + 0x56A000500, // accessLinkMask + 0xFF00FF // trunkLinkMask }, { - 0x1c, // switchPhysicalId - 0x4A9009400 //linkMask + 0x19, // switchPhysicalId + 0x509009900, // accessLinkMask + 0xFF00FF // trunkLinkMask + }, + { + 0x1a, // switchPhysicalId + 0x0, // accessLinkMask + 0xFF00FF // trunkLinkMask + }, + { + 0x1b, // switchPhysicalId + 0x56A000600, // accessLinkMask + 0xFF00FF // trunkLinkMask + }, + { + 0x1c, // switchPhysicalId + 0x4A9009400, // accessLinkMask + 0xFF00FF // trunkLinkMask + }, + { + 0x1d, // switchPhysicalId + 0x0, // accessLinkMask + 0xFF00FF // trunkLinkMask }, }; ct_assert(sizeof(nvswitchDisconnetedRemoteLinkMasks)/sizeof(lr10_links_connected_to_disabled_remote_end) == NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK); @@ -538,6 +566,11 @@ nvswitch_init_lpwr_regs_lr10 NvU8 softwareDesired, hardwareDisable; NvBool bLpEnable; + if (nvswitch_is_link_in_reset(device, link)) + { + return; + } + if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) { return; @@ -653,6 +686,15 @@ nvswitch_init_lpwr_regs_lr10 tempRegVal); } +void +nvswitch_program_l1_scratch_reg_lr10 +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + // Not Implemented for LR10 +} void nvswitch_init_buffer_ready_lr10 @@ -841,7 +883,6 @@ nvswitch_corelib_set_dl_link_mode_lr10 if (nvswitch_does_link_need_termination_enabled(device, link)) { - if (mode == NVLINK_LINKSTATE_INITPHASE1) { status = nvswitch_link_termination_setup(device, link); @@ -2372,6 +2413,8 @@ nvswitch_load_link_disable_settings_lr10 NvU32 val; NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL; NVSWITCH_BIOS_NVLINK_CONFIG *bios_config; + NvlStatus status; + lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); bios_config = nvswitch_get_bios_nvlink_config(device); if ((bios_config == NULL) || (bios_config->bit_address == 0)) @@ -2412,15 +2455,16 @@ nvswitch_load_link_disable_settings_lr10 __FUNCTION__, link->linkNumber); return; } - val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, _LINK_DISABLE, - _DISABLED, val); - NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, - NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, val); - // Set link to invalid and unregister from corelib - device->link[link->linkNumber].valid = NV_FALSE; - nvlink_lib_unregister_link(link); - nvswitch_destroy_link(link); + status = nvswitch_link_termination_setup(device, link); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to enable termination on link #%d\n", __FUNCTION__, link->linkNumber); + return; + } + // add link to disabledRemoteEndLinkMask + chip_device->disabledRemoteEndLinkMask |= NVBIT64(link->linkNumber); return; } @@ -2488,6 +2532,8 @@ nvswitch_does_link_need_termination_enabled_lr10 NvU32 i; NvU32 physicalId; lr10_device *chip_device; + NvU32 numNvswitches; + NvlStatus status; physicalId = nvswitch_read_physical_id(device); chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); @@ -2510,16 +2556,30 @@ nvswitch_does_link_need_termination_enabled_lr10 chip_device->disabledRemoteEndLinkMask = 0; if (nvlink_lib_is_registerd_device_with_reduced_config()) { - for (i = 0; i < NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK; ++i) - { - if (nvswitchDisconnetedRemoteLinkMasks[i].switchPhysicalId == physicalId) + for (i = 0; i < NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK; ++i) { - chip_device->disabledRemoteEndLinkMask = - nvswitchDisconnetedRemoteLinkMasks[i].linkMask; - break; + if (nvswitchDisconnetedRemoteLinkMasks[i].switchPhysicalId == physicalId) + { + chip_device->disabledRemoteEndLinkMask |= + nvswitchDisconnetedRemoteLinkMasks[i].accessLinkMask; + + status = nvlink_lib_return_device_count_by_type(NVLINK_DEVICE_TYPE_NVSWITCH, &numNvswitches); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get nvswitch device count!\n", __FUNCTION__); + break; + } + + if (numNvswitches <= NVSWITCH_NUM_DEVICES_PER_DELTA_LR10) + { + chip_device->disabledRemoteEndLinkMask |= + nvswitchDisconnetedRemoteLinkMasks[i].trunkLinkMask; + } + break; + } } } - } chip_device->bDisabledRemoteEndLinkMaskCached = NV_TRUE; } diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index 1323ea28d..1c1d07b1c 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -3656,6 +3656,15 @@ nvswitch_initialize_device_state_lr10 goto nvswitch_initialize_device_state_exit; } + retval = nvswitch_check_io_sanity(device); + if (NVL_SUCCESS != retval) + { + NVSWITCH_PRINT(device, ERROR, + "%s: IO sanity test failed\n", + __FUNCTION__); + goto nvswitch_initialize_device_state_exit; + } + NVSWITCH_PRINT(device, SETUP, "%s: MMIO discovery\n", __FUNCTION__); @@ -7850,6 +7859,15 @@ nvswitch_ctrl_get_nvlink_error_threshold_lr10 return -NVL_ERR_NOT_SUPPORTED; } +NvlStatus +nvswitch_check_io_sanity_lr10 +( + nvswitch_device *device +) +{ + return NVL_SUCCESS; +} + // // This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL // macro in haldef_nvswitch.h diff --git a/src/common/nvswitch/kernel/ls10/inforom_ls10.c b/src/common/nvswitch/kernel/ls10/inforom_ls10.c index 588500af2..56c898d6a 100644 --- a/src/common/nvswitch/kernel/ls10/inforom_ls10.c +++ b/src/common/nvswitch/kernel/ls10/inforom_ls10.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -863,3 +863,174 @@ nvswitch_bbx_get_sxid_ls10_free_and_exit: return status; } + +NvlStatus +nvswitch_bbx_get_data_ls10 +( + nvswitch_device *device, + NvU8 dataType, + void *params +) +{ + NvlStatus status; + void *pDmaBuf; + NvU64 dmaHandle; + FLCN *pFlcn; + RM_FLCN_CMD_SOE bbxCmd; + NvU32 cmdSeqDesc; + NVSWITCH_TIMEOUT timeout; + NvU32 transferSize; + + if (!nvswitch_is_inforom_supported_ls10(device)) + { + NVSWITCH_PRINT(device, ERROR, "%s: InfoROM is not supported\n", __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (params == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: params is NULL\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + switch (dataType) + { + case RM_SOE_IFR_BBX_GET_SYS_INFO: + transferSize = sizeof(NVSWITCH_GET_SYS_INFO_PARAMS); + break; + + case RM_SOE_IFR_BBX_GET_TIME_INFO: + transferSize = sizeof(NVSWITCH_GET_TIME_INFO_PARAMS); + break; + + case RM_SOE_IFR_BBX_GET_TEMP_DATA: + transferSize = sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS); + break; + + case RM_SOE_IFR_BBX_GET_TEMP_SAMPLES: + transferSize = sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS); + break; + default: + NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType); + return -NVL_BAD_ARGS; + break; + } + + status = nvswitch_os_alloc_contig_memory(device->os_handle, &pDmaBuf, transferSize, + (device->dma_addr_width == 32)); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to allocate contig memory. rc:%d\n", __FUNCTION__, status); + return status; + } + + status = nvswitch_os_map_dma_region(device->os_handle, pDmaBuf, &dmaHandle, + transferSize, NVSWITCH_DMA_DIR_TO_SYSMEM); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to map DMA region. rc:%d\n", __FUNCTION__, status); + goto nvswitch_bbx_get_data_ls10_free_and_exit; + } + + nvswitch_os_memset(pDmaBuf, 0, transferSize); + + pFlcn = device->pSoe->pFlcn; + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + + nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd)); + bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; + bbxCmd.hdr.size = sizeof(bbxCmd); + bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_DATA_GET; + bbxCmd.cmd.ifr.bbxDataGet.sizeInBytes = transferSize; + bbxCmd.cmd.ifr.bbxDataGet.dataType = dataType; + RM_FLCN_U64_PACK(&bbxCmd.cmd.ifr.bbxDataGet.dmaHandle, &dmaHandle); + + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&bbxCmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: BX_GET_DATA type=%d failed. rc:%d\n", + __FUNCTION__, dataType, status); + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + + status = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle, + transferSize, + NVSWITCH_DMA_DIR_TO_SYSMEM); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to sync DMA region. rc:%d\n", __FUNCTION__, status); + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + + if (dataType == RM_SOE_IFR_BBX_GET_SYS_INFO) + { + NVSWITCH_GET_SYS_INFO_PARAMS bbxSysInfoData = {0}; + + nvswitch_os_memcpy((NvU8 *)&bbxSysInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS)); + nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxSysInfoData, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS)); + } + else if (dataType == RM_SOE_IFR_BBX_GET_TIME_INFO) + { + NVSWITCH_GET_TIME_INFO_PARAMS bbxTimeInfoData = {0}; + + nvswitch_os_memcpy((NvU8 *)&bbxTimeInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS)); + nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxTimeInfoData, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS)); + } + else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_DATA) + { + NVSWITCH_GET_TEMP_DATA_PARAMS *pBbxTempData = NULL; + + pBbxTempData = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS)); + if (pBbxTempData == NULL) + { + NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType); + status = -NVL_NO_MEM; + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + + nvswitch_os_memset(pBbxTempData, 0, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS)); + + nvswitch_os_memcpy((NvU8 *)pBbxTempData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS)); + nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempData, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS)); + + nvswitch_os_free(pBbxTempData); + } + else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_SAMPLES) + { + NVSWITCH_GET_TEMP_SAMPLES_PARAMS *pBbxTempSamples = NULL; + + pBbxTempSamples = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS)); + if (pBbxTempSamples == NULL) + { + NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType); + status = -NVL_NO_MEM; + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + + nvswitch_os_memset(pBbxTempSamples, 0, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS)); + + nvswitch_os_memcpy((NvU8 *)pBbxTempSamples, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS)); + nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempSamples, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS)); + + nvswitch_os_free(pBbxTempSamples); + } + else + { + NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType); + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + +nvswitch_bbx_get_data_ls10_unmap_and_exit: + nvswitch_os_unmap_dma_region(device->os_handle, pDmaBuf, dmaHandle, + transferSize, NVSWITCH_DMA_DIR_FROM_SYSMEM); +nvswitch_bbx_get_data_ls10_free_and_exit: + nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize); + + return status; +} diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c index 3bc899983..bcdc3de0e 100644 --- a/src/common/nvswitch/kernel/ls10/intr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -5525,7 +5525,7 @@ _nvswitch_emit_link_errors_nvldl_fatal_link_ls10 INFOROM_NVLINK_ERROR_EVENT error_event; // Only enabled link errors are deffered - pending = chip_device->deferredLinkErrors[link].fatalIntrMask.dl; + pending = chip_device->deferredLinkErrors[link].data.fatalIntrMask.dl; report.raw_pending = pending; report.raw_enable = pending; report.mask = report.raw_enable; @@ -5565,13 +5565,13 @@ _nvswitch_emit_link_errors_minion_fatal_ls10 NvU32 localLinkIdx = NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); NvU32 bit = BIT(localLinkIdx); - if (!chip_device->deferredLinkErrors[link].fatalIntrMask.minionLinkIntr.bPending) + if (!chip_device->deferredLinkErrors[link].data.fatalIntrMask.minionLinkIntr.bPending) { return; } // Grab the cached interrupt data - regData = chip_device->deferredLinkErrors[link].fatalIntrMask.minionLinkIntr.regData; + regData = chip_device->deferredLinkErrors[link].data.fatalIntrMask.minionLinkIntr.regData; // get all possible interrupting links associated with this minion report.raw_enable = link; @@ -5628,7 +5628,7 @@ _nvswitch_emit_link_errors_minion_nonfatal_ls10 NvU32 localLinkIdx = NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); NvU32 bit = BIT(localLinkIdx); - if (!chip_device->deferredLinkErrors[link].nonFatalIntrMask.minionLinkIntr.bPending) + if (!chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.minionLinkIntr.bPending) { return; } @@ -5637,7 +5637,7 @@ _nvswitch_emit_link_errors_minion_nonfatal_ls10 regData = NVSWITCH_MINION_RD32_LS10(device, nvlipt_instance, _MINION, _MINION_INTR_STALL_EN); // Grab the cached interrupt data - regData = chip_device->deferredLinkErrors[link].nonFatalIntrMask.minionLinkIntr.regData; + regData = chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.minionLinkIntr.regData; // get all possible interrupting links associated with this minion report.raw_enable = link; @@ -5675,7 +5675,7 @@ _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10 NvU32 pending, bit, reg; // Only enabled link errors are deffered - pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl; + pending = chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.dl; report.raw_pending = pending; report.raw_enable = pending; report.mask = report.raw_enable; @@ -5723,8 +5723,8 @@ _nvswitch_emit_link_errors_nvltlc_rx_lnk_nonfatal_1_ls10 NvU32 injected; // Only enabled link errors are deffered - pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1; - injected = chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1Injected; + pending = chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.tlcRx1; + injected = chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.tlcRx1Injected; report.raw_pending = pending; report.raw_enable = pending; report.mask = report.raw_enable; @@ -5760,7 +5760,7 @@ _nvswitch_emit_link_errors_nvlipt_lnk_nonfatal_ls10 INFOROM_NVLINK_ERROR_EVENT error_event; // Only enabled link errors are deffered - pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.liptLnk; + pending = chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.liptLnk; report.raw_pending = pending; report.raw_enable = pending; report.mask = report.raw_enable; @@ -5805,11 +5805,11 @@ _nvswitch_clear_deferred_link_errors_ls10 ) { ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); - NVLINK_LINK_ERROR_REPORTING *pLinkErrors; + NVLINK_LINK_ERROR_REPORTING_DATA *pLinkErrorsData; - pLinkErrors = &chip_device->deferredLinkErrors[link]; + pLinkErrorsData = &chip_device->deferredLinkErrors[link].data; - nvswitch_os_memset(pLinkErrors, 0, sizeof(NVLINK_LINK_ERROR_REPORTING)); + nvswitch_os_memset(pLinkErrorsData, 0, sizeof(NVLINK_LINK_ERROR_REPORTING_DATA)); } static void @@ -5824,36 +5824,47 @@ _nvswitch_deferred_link_state_check_ls10 NvU32 nvlipt_instance = pErrorReportParams->nvlipt_instance; NvU32 link = pErrorReportParams->link; ls10_device *chip_device; - nvlink_link *pLink; - NvU64 linkState; + NvU64 lastLinkUpTime; + NvU64 lastRetrainTime; + NvU64 current_time = nvswitch_os_get_platform_time(); chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); - pLink = nvswitch_get_link(device, pErrorReportParams->link); + lastLinkUpTime = chip_device->deferredLinkErrors[link].state.lastLinkUpTime; + lastRetrainTime = chip_device->deferredLinkErrors[link].state.lastRetrainTime; - // If is there a retry for reset_and_drain then re-create the state check for the current link - if (chip_device->deferredLinkErrors[link].bResetAndDrainRetry == NV_TRUE) - { - if (pErrorReportParams) - { - nvswitch_os_free(pErrorReportParams); - } + // Sanity Check + NVSWITCH_ASSERT(nvswitch_is_link_valid(device, link)); - chip_device->deferredLinkErrors[link].bLinkErrorsCallBackEnabled = NV_FALSE; - chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_FALSE; - nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); + nvswitch_os_free(pErrorReportParams); + pErrorReportParams = NULL; + chip_device->deferredLinkErrors[link].state.bLinkStateCallBackEnabled = NV_FALSE; + + // Link came up after last retrain + if (lastLinkUpTime >= lastRetrainTime) + { return; } - if ((pLink == NULL) || - (device->hal.nvswitch_corelib_get_dl_link_mode(pLink, &linkState) != NVL_SUCCESS) || - ((linkState != NVLINK_LINKSTATE_HS) && (linkState != NVLINK_LINKSTATE_SLEEP))) + // + // If the last time this link was up was before the last + // reset_and_drain execution and not enough time has past since the last + // retrain then schedule another callback. + // + if (lastLinkUpTime < lastRetrainTime) { - _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); + if ((current_time - lastRetrainTime) < NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS) + { + nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); + return; + } } + // + // Otherwise, the link hasn't retrained within the timeout so emit the + // deferred errors. + // + _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); _nvswitch_clear_deferred_link_errors_ls10(device, link); - nvswitch_os_free(pErrorReportParams); - chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled = NV_FALSE; } void @@ -5868,7 +5879,7 @@ nvswitch_create_deferred_link_state_check_task_ls10 NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams; NvlStatus status; - if (chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled) + if (chip_device->deferredLinkErrors[link].state.bLinkStateCallBackEnabled) { return; } @@ -5889,7 +5900,7 @@ nvswitch_create_deferred_link_state_check_task_ls10 if (status == NVL_SUCCESS) { - chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled = NV_TRUE; + chip_device->deferredLinkErrors[link].state.bLinkStateCallBackEnabled = NV_TRUE; } else { @@ -5916,25 +5927,29 @@ _nvswitch_deferred_link_errors_check_ls10 ls10_device *chip_device; NvU32 pending; + nvswitch_os_free(pErrorReportParams); + pErrorReportParams = NULL; + chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + chip_device->deferredLinkErrors[link].state.bLinkErrorsCallBackEnabled = NV_FALSE; - pending = chip_device->deferredLinkErrors[link].fatalIntrMask.dl; - if (FLD_TEST_DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1U, pending) || - FLD_TEST_DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1U, pending) ) - { - nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); - } - else - { - _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); - _nvswitch_clear_deferred_link_errors_ls10(device, link); - } + pending = chip_device->deferredLinkErrors[link].data.fatalIntrMask.dl; - if (pErrorReportParams) - { - nvswitch_os_free(pErrorReportParams); - } - chip_device->deferredLinkErrors[link].bLinkErrorsCallBackEnabled = NV_FALSE; + // A link fault was observed which means we also did the retrain and + // scheduled a state check task. We can exit. + if (FLD_TEST_DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1U, pending)) + return; + + if (FLD_TEST_DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1U, pending)) + return; + + // + // No link fault, emit the deferred errors. + // It is assumed that this callback runs long before a link could have been + // retrained and hit errors again. + // + _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); + _nvswitch_clear_deferred_link_errors_ls10(device, link); } static void @@ -5949,13 +5964,11 @@ _nvswitch_create_deferred_link_errors_task_ls10 NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams; NvlStatus status; - if (chip_device->deferredLinkErrors[link].bLinkErrorsCallBackEnabled) + if (chip_device->deferredLinkErrors[link].state.bLinkErrorsCallBackEnabled) { return; } - chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_FALSE; - status = NVL_ERR_GENERIC; pErrorReportParams = nvswitch_os_malloc(sizeof(NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS)); if(pErrorReportParams != NULL) @@ -5972,7 +5985,7 @@ _nvswitch_create_deferred_link_errors_task_ls10 if (status == NVL_SUCCESS) { - chip_device->deferredLinkErrors[link].bLinkErrorsCallBackEnabled = NV_TRUE; + chip_device->deferredLinkErrors[link].state.bLinkErrorsCallBackEnabled = NV_TRUE; } else { @@ -6026,7 +6039,7 @@ _nvswitch_service_nvldl_nonfatal_link_ls10 bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 1); if (nvswitch_test_flags(pending, bit)) { - chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl |= bit; + chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.dl |= bit; _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); nvswitch_clear_flags(&unhandled, bit); } @@ -6049,7 +6062,7 @@ _nvswitch_service_nvldl_nonfatal_link_ls10 if (nvswitch_test_flags(pending, bit)) { - chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl |= bit; + chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.dl |= bit; _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); nvswitch_clear_flags(&unhandled, bit); @@ -6344,8 +6357,8 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_1_ls10 bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _HEARTBEAT_TIMEOUT_ERR, 1); if (nvswitch_test_flags(pending, bit)) { - chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1 |= bit; - chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1Injected |= injected; + chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.tlcRx1 |= bit; + chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.tlcRx1Injected |= injected; _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); if (FLD_TEST_DRF_NUM(_NVLTLC_RX_LNK, _ERR_REPORT_INJECT_1, _HEARTBEAT_TIMEOUT_ERR, 0x0, injected)) @@ -6628,8 +6641,10 @@ _nvswitch_service_nvlipt_lnk_status_ls10 NvU32 pending, enabled, unhandled, bit; NvU64 mode; nvlink_link *link; - link = nvswitch_get_link(device, link_id); + ls10_device *chip_device; + link = nvswitch_get_link(device, link_id); + chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); pending = NVSWITCH_LINK_RD32(device, link_id, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS); enabled = NVSWITCH_LINK_RD32(device, link_id, NVLIPT_LNK, _NVLIPT_LNK, _INTR_INT1_EN); pending &= enabled; @@ -6669,7 +6684,13 @@ _nvswitch_service_nvlipt_lnk_status_ls10 // nvswitch_corelib_training_complete_ls10(link); nvswitch_init_buffer_ready(device, link, NV_TRUE); - link->bRxDetected = NV_TRUE; + link->bRxDetected = NV_TRUE; + + // + // Clear out any cached interrupts for the link and update the last link up timestamp + // + _nvswitch_clear_deferred_link_errors_ls10(device, link_id); + chip_device->deferredLinkErrors[link_id].state.lastLinkUpTime = nvswitch_os_get_platform_time(); } else if (mode == NVLINK_LINKSTATE_FAULT) { @@ -6706,8 +6727,6 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 ) { ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); - nvlink_link *link_info = nvswitch_get_link(device, link); - NvU32 lnkStateRequest, linkState; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; @@ -6743,27 +6762,10 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 if (nvswitch_test_flags(pending, bit)) { // - // Read back LINK_STATE_REQUESTS and TOP_LINK_STATE registers - // If request == ACTIVE and TOP_LINK_STATE == FAULT there is a pending - // fault on training so re-run reset_and_drain - // Mark that the defered link error mechanism as seeing a reset_and_train re-try so - // the deferred task needs to re-create itself instead of continuing with the linkstate - // checks + // based off of HW's assertion. FAILEDMINIONREQUEST always trails a DL fault. So no need to + // do reset_and_drain here // - linkState = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber, NVLDL, - _NVLDL, _TOP_LINK_STATE); - - lnkStateRequest = NVSWITCH_LINK_RD32_LS10(device, link, - NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_REQUEST); - - if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, _ACTIVE, lnkStateRequest) && - linkState == NV_NVLDL_TOP_LINK_STATE_STATE_FAULT) - { - chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_TRUE; - device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link)); - } - - chip_device->deferredLinkErrors[link].nonFatalIntrMask.liptLnk |= bit; + chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.liptLnk |= bit; _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); nvswitch_clear_flags(&unhandled, bit); } @@ -7001,9 +7003,9 @@ _nvswitch_service_nvlw_nonfatal_ls10 return NVL_SUCCESS; } - status[0] = _nvswitch_service_nvldl_nonfatal_ls10(device, instance, intrLinkMask); - status[1] = _nvswitch_service_nvltlc_nonfatal_ls10(device, instance, intrLinkMask); - status[2] = _nvswitch_service_nvlipt_link_nonfatal_ls10(device, instance, intrLinkMask); + status[0] = _nvswitch_service_nvlipt_link_nonfatal_ls10(device, instance, intrLinkMask); + status[1] = _nvswitch_service_nvldl_nonfatal_ls10(device, instance, intrLinkMask); + status[2] = _nvswitch_service_nvltlc_nonfatal_ls10(device, instance, intrLinkMask); if ((status[0] != NVL_SUCCESS) && (status[0] != -NVL_NOT_FOUND) && (status[1] != NVL_SUCCESS) && (status[1] != -NVL_NOT_FOUND) && @@ -7373,23 +7375,21 @@ nvswitch_lib_service_interrupts_ls10 // 2. Clear leaf interrupt // 3. Run leaf specific interrupt handler // - val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_FATAL); - val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_FATAL, _MASK, val); + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_NON_FATAL); + val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_NON_FATAL, _MASK, val); if (val != 0) { - NVSWITCH_PRINT(device, INFO, "%s: NVLW FATAL interrupts pending = 0x%x\n", + NVSWITCH_PRINT(device, INFO, "%s: NVLW NON_FATAL interrupts pending = 0x%x\n", __FUNCTION__, val); - - NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX), val); - - for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_FATAL_MASK); i++) + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX), val); + for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_MASK); i++) { if (val & NVBIT(i)) { - status = _nvswitch_service_nvlw_fatal_ls10(device, i); + status = _nvswitch_service_nvlw_nonfatal_ls10(device, i); if (status != NVL_SUCCESS) { - NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] FATAL interrupt handling status = %d\n", + NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] NON_FATAL interrupt handling status = %d\n", __FUNCTION__, i, status); return_status = status; } @@ -7397,21 +7397,23 @@ nvswitch_lib_service_interrupts_ls10 } } - val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_NON_FATAL); - val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_NON_FATAL, _MASK, val); + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_FATAL); + val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_FATAL, _MASK, val); if (val != 0) { - NVSWITCH_PRINT(device, INFO, "%s: NVLW NON_FATAL interrupts pending = 0x%x\n", + NVSWITCH_PRINT(device, INFO, "%s: NVLW FATAL interrupts pending = 0x%x\n", __FUNCTION__, val); - NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX), val); - for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_MASK); i++) + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX), val); + + for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_FATAL_MASK); i++) { if (val & NVBIT(i)) { - status = _nvswitch_service_nvlw_nonfatal_ls10(device, i); + status = _nvswitch_service_nvlw_fatal_ls10(device, i); if (status != NVL_SUCCESS) { - NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] NON_FATAL interrupt handling status = %d\n", + NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] FATAL interrupt handling status = %d\n", __FUNCTION__, i, status); return_status = status; } @@ -7757,16 +7759,16 @@ nvswitch_service_nvldl_fatal_link_ls10 if (nvswitch_test_flags(pending, bit)) { { - dlDeferredIntrLinkMask |= bit; + dlDeferredIntrLinkMask |= bit; - // - // Since reset and drain will reset the link, including clearing - // pending interrupts, skip the clear write below. There are cases - // where link clocks will not be on after reset and drain so there - // maybe PRI errors on writing to the register - // - bRequireResetAndDrain = NV_TRUE; - } + // + // Since reset and drain will reset the link, including clearing + // pending interrupts, skip the clear write below. There are cases + // where link clocks will not be on after reset and drain so there + // maybe PRI errors on writing to the register + // + bRequireResetAndDrain = NV_TRUE; + } nvswitch_clear_flags(&unhandled, bit); } @@ -7774,41 +7776,25 @@ nvswitch_service_nvldl_fatal_link_ls10 if (nvswitch_test_flags(pending, bit)) { { - dlDeferredIntrLinkMask |= bit; + dlDeferredIntrLinkMask |= bit; - // - // Since reset and drain will reset the link, including clearing - // pending interrupts, skip the clear write below. There are cases - // where link clocks will not be on after reset and drain so there - // maybe PRI errors on writing to the register - // - bRequireResetAndDrain = NV_TRUE; - } + // + // Since reset and drain will reset the link, including clearing + // pending interrupts, skip the clear write below. There are cases + // where link clocks will not be on after reset and drain so there + // maybe PRI errors on writing to the register + // + bRequireResetAndDrain = NV_TRUE; + } nvswitch_clear_flags(&unhandled, bit); } if (bRequireResetAndDrain) { - // - // If there is a link state callback enabled for this link then - // we hit a consecutive FAULT_UP error. set bResetAndDrainRetry - // so the current callback on completion can create a new - // callback to retry the link state check to account for the added - // delay caused by taking a 2nd fault and having to re-train - // - // If there is no callback enabled then set the error mask - // and create the link errors deferred task. - // - if (chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled) - { - chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_TRUE; - } - else - { - chip_device->deferredLinkErrors[link].fatalIntrMask.dl = dlDeferredIntrLinkMask; - _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); - } + chip_device->deferredLinkErrors[link].data.fatalIntrMask.dl |= dlDeferredIntrLinkMask; device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link)); + chip_device->deferredLinkErrors[link].state.lastRetrainTime = nvswitch_os_get_platform_time(); + nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -7916,7 +7902,7 @@ nvswitch_service_minion_link_ls10 case NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT: case NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL: case NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT: - chip_device->deferredLinkErrors[link].fatalIntrMask.minionLinkIntr = + chip_device->deferredLinkErrors[link].data.fatalIntrMask.minionLinkIntr = minionLinkIntr; _nvswitch_create_deferred_link_errors_task_ls10(device, instance, link); break; @@ -7928,7 +7914,7 @@ nvswitch_service_minion_link_ls10 case NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ: case NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED: case NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ: - chip_device->deferredLinkErrors[link].nonFatalIntrMask.minionLinkIntr = + chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.minionLinkIntr = minionLinkIntr; _nvswitch_create_deferred_link_errors_task_ls10(device, instance, link); case NV_MINION_NVLINK_LINK_INTR_CODE_NOTIFY: diff --git a/src/common/nvswitch/kernel/ls10/link_ls10.c b/src/common/nvswitch/kernel/ls10/link_ls10.c index bdcae93fa..0a3320d4e 100644 --- a/src/common/nvswitch/kernel/ls10/link_ls10.c +++ b/src/common/nvswitch/kernel/ls10/link_ls10.c @@ -99,6 +99,30 @@ _nvswitch_configure_reserved_throughput_counters } void +nvswitch_program_l1_scratch_reg_ls10 +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + NvU32 scrRegVal; + NvU32 tempRegVal; + + // Read L1 register and store initial/VBIOS L1 Threshold Value in Scratch register + tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD); + + scrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _SCRATCH_WARM); + + // Update the scratch register value only if it has not been written to before + if (scrRegVal == NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT) + { + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _SCRATCH_WARM, tempRegVal); + } +} + +#define BUG_3797211_LS10_VBIOS_VERSION 0x9610410000 + +void nvswitch_init_lpwr_regs_ls10 ( nvlink_link *link @@ -110,33 +134,56 @@ nvswitch_init_lpwr_regs_ls10 NvU32 tempRegVal, lpEntryThreshold; NvU8 softwareDesired; NvBool bLpEnable; + NvU64 biosVersion; if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) { return; } - // bios_config = nvswitch_get_bios_nvlink_config(device); + if (nvswitch_lib_get_bios_version(device, &biosVersion) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, "%s Get VBIOS version failed.\n", + __FUNCTION__); + biosVersion = 0; + } - // IC Enter Threshold - if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) + // bios_config = nvswitch_get_bios_nvlink_config(device); + if (biosVersion >= BUG_3797211_LS10_VBIOS_VERSION) { - // - // TODO: get from bios. Refer Bug 3626523 for more info. - // - // The threshold is measured in 100us unit. So lpEntryThreshold = 1 - // means the threshold is set to 100us in the register. - // - lpEntryThreshold = 1; + // IC Enter Threshold + if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) + { + // + // Do nothing since VBIOS (version 96.10.41.00.00 and above) + // sets the default L1 threshold. + // Refer Bug 3797211 for more info. + // + } + else + { + lpEntryThreshold = device->regkeys.lp_threshold; + tempRegVal = 0; + tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal); + } } else { - lpEntryThreshold = device->regkeys.lp_threshold; - } + // IC Enter Threshold + if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) + { + lpEntryThreshold = 1; + } + else + { + lpEntryThreshold = device->regkeys.lp_threshold; + } - tempRegVal = 0; - tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); - NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal); + tempRegVal = 0; + tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal); + } //LP Entry Enable bLpEnable = NV_TRUE; @@ -1423,7 +1470,7 @@ nvswitch_load_link_disable_settings_ls10 nvswitch_device *device, nvlink_link *link ) -{ +{ NvU32 regVal; // Read state from NVLIPT HW @@ -1432,7 +1479,7 @@ nvswitch_load_link_disable_settings_ls10 if (FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, _DISABLE, regVal)) { - + // Set link to invalid and unregister from corelib device->link[link->linkNumber].valid = NV_FALSE; nvlink_lib_unregister_link(link); @@ -1473,7 +1520,7 @@ nvswitch_execute_unilateral_link_shutdown_ls10 // Status is explicitly ignored here since we are required to soldier-on // in this scenario // - status = nvswitch_request_tl_link_state_lr10(link, + status = nvswitch_request_tl_link_state_ls10(link, NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN, NV_TRUE); if (status == NVL_SUCCESS) @@ -1492,22 +1539,22 @@ nvswitch_execute_unilateral_link_shutdown_ls10 { link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); - if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && - (link_intr_subcode == MINION_ALARM_BUSY)) - { - NVSWITCH_PRINT(device, INFO, - "%s: Retrying shutdown due to Minion DLCMD Fault subcode = 0x%x\n", - __FUNCTION__, link_intr_subcode); - // - // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL - // or MINION_ALARM_BUSY - // - retry_count--; - } - else - { - break; - } + if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && + (link_intr_subcode == MINION_ALARM_BUSY)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Retrying shutdown due to Minion DLCMD Fault subcode = 0x%x\n", + __FUNCTION__, link_intr_subcode); + // + // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL + // or MINION_ALARM_BUSY + // + retry_count--; + } + else + { + break; + } } else { @@ -1542,6 +1589,12 @@ nvswitch_reset_and_train_link_ls10 nvswitch_execute_unilateral_link_shutdown_ls10(link); nvswitch_corelib_clear_link_state_ls10(link); + // + // When a link faults there could be a race between the driver requesting + // reset and MINION processing Emergency Shutdown. Minion will notify if + // such a collision happens and will deny the reset request, so try the + // request up to 3 times + // do { status = nvswitch_request_tl_link_state_ls10(link, @@ -1565,24 +1618,24 @@ nvswitch_reset_and_train_link_ls10 { link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); - if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && - (link_intr_subcode == MINION_ALARM_BUSY)) - { + if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && + (link_intr_subcode == MINION_ALARM_BUSY)) + { - status = nvswitch_request_tl_link_state_ls10(link, - NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, NV_TRUE); + status = nvswitch_request_tl_link_state_ls10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, NV_TRUE); - // - // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL - // or MINION_ALARM_BUSY - // - retry_count--; - } - else - { - break; + // + // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL + // or MINION_ALARM_BUSY + // + retry_count--; + } + else + { + break; + } } - } else { // failed to query minion for the link_intr_subcode so retry @@ -1597,15 +1650,18 @@ nvswitch_reset_and_train_link_ls10 "%s: NvLink Reset has failed for link %d\n", __FUNCTION__, link->linkNumber); - // Re-register links. - status = nvlink_lib_register_link(device->nvlink_device, link); - if (status != NVL_SUCCESS) - { - nvswitch_destroy_link(link); - return status; - } return status; } + + status = nvswitch_launch_ALI_link_training(device, link, NV_FALSE); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NvLink failed to request ACTIVE for link %d\n", + __FUNCTION__, link->linkNumber); + return status; + } + return NVL_SUCCESS; } @@ -1657,6 +1713,76 @@ nvswitch_are_link_clocks_on_ls10 return NV_TRUE; } +NvlStatus +nvswitch_request_tl_link_state_ls10 +( + nvlink_link *link, + NvU32 tlLinkState, + NvBool bSync +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvlStatus status = NVL_SUCCESS; + NvU32 linkStatus; + NvU32 lnkErrStatus; + NvU32 bit; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d invalid\n", + __FUNCTION__, link->linkNumber); + return -NVL_UNBOUND_DEVICE; + } + + // Wait for the TL link state register to report ready + status = nvswitch_wait_for_tl_request_ready_lr10(link); + if (status != NVL_SUCCESS) + { + return status; + } + + // Clear any pending FAILEDMINIONREQUEST status that maybe populated as it is stale now + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _FAILEDMINIONREQUEST, 1); + lnkErrStatus = NVSWITCH_LINK_RD32(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); + if (nvswitch_test_flags(lnkErrStatus, bit)) + { + NVSWITCH_LINK_WR32(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0, + bit); + } + + + // Request state through CTRL_LINK_STATE_REQUEST + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, + DRF_NUM(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, tlLinkState)); + + if (bSync) + { + // Wait for the TL link state register to complete + status = nvswitch_wait_for_tl_request_ready_lr10(link); + if (status != NVL_SUCCESS) + { + return status; + } + + // Check for state requested + linkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_STATUS); + + if (DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, linkStatus) != + tlLinkState) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link state request to state 0x%x for link #%d did not complete!\n", + __FUNCTION__, tlLinkState, link->linkNumber); + return -NVL_ERR_GENERIC; + } + } + + return status; +} + NvBool nvswitch_does_link_need_termination_enabled_ls10 ( diff --git a/src/common/nvswitch/kernel/ls10/ls10.c b/src/common/nvswitch/kernel/ls10/ls10.c index 6faaec093..f43bd7673 100644 --- a/src/common/nvswitch/kernel/ls10/ls10.c +++ b/src/common/nvswitch/kernel/ls10/ls10.c @@ -42,6 +42,7 @@ #include "ls10/gfw_ls10.h" #include "nvswitch/ls10/dev_nvs_top.h" +#include "nvswitch/ls10/ptop_discovery_ip.h" #include "nvswitch/ls10/dev_pri_masterstation_ip.h" #include "nvswitch/ls10/dev_pri_hub_sys_ip.h" #include "nvswitch/ls10/dev_nvlw_ip.h" @@ -1353,7 +1354,53 @@ nvswitch_init_warm_reset_ls10 ) { NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); - } +} + +// +// Helper funcction to query MINION to see if DL clocks are on +// return NV_TRUE if the clocks are on +// NV_FALSE if the clocks are off +static +NvBool +_nvswitch_are_dl_clocks_on +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + NvU32 link_state; + NvU32 stat_data; + NvlStatus status = NVL_SUCCESS; + nvlink_link * link= nvswitch_get_link(device, linkNumber); + + if (link == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: invalid link %d\n", + __FUNCTION__, linkNumber); + return NV_FALSE; + } + + status = nvswitch_minion_get_dl_status(device, linkNumber, + NV_NVLSTAT_UC01, 0, &stat_data); + if (status != NVL_SUCCESS) + { + return NV_FALSE; + } + + link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data); + switch(link_state) + { + case LINKSTATUS_RESET: + case LINKSTATUS_UNINIT: + return NV_FALSE; + case LINKSTATUS_LANESHUTDOWN: + case LINKSTATUS_ACTIVE_PENDING: + return nvswitch_are_link_clocks_on_ls10(device, link, + NVSWITCH_PER_LINK_CLOCK_SET(RXCLK) | NVSWITCH_PER_LINK_CLOCK_SET(TXCLK)); + } + + return NV_TRUE; +} // // Implement reset and drain sequence for ls10 @@ -1586,10 +1633,10 @@ nvswitch_reset_and_drain_links_ls10 nvswitch_soe_restore_nport_state_ls10(device, link); // Step 7.0 : Re-program the routing table for DBEs - + // Step 8.0 : Reset NVLW and NPORT interrupt state _nvswitch_link_reset_interrupts_ls10(device, link); - + // Re-register links. status = nvlink_lib_register_link(device->nvlink_device, link_info); if (status != NVL_SUCCESS) @@ -1625,21 +1672,9 @@ nvswitch_reset_and_drain_links_ls10 do { bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + bAreDlClocksOn = _nvswitch_are_dl_clocks_on(device, link); - status = nvswitch_minion_get_dl_status(device, link_info->linkNumber, - NV_NVLSTAT_UC01, 0, &stat_data); - - if (status != NVL_SUCCESS) - { - continue; - } - - link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data); - - bAreDlClocksOn = (link_state != LINKSTATUS_INITPHASE1) ? - NV_TRUE:NV_FALSE; - - if (bAreDlClocksOn == NV_TRUE) + if (bAreDlClocksOn) { break; } @@ -5806,6 +5841,104 @@ nvswitch_ctrl_get_nvlink_error_threshold_ls10 } NvlStatus +nvswitch_check_io_sanity_ls10 +( + nvswitch_device *device +) +{ + NvBool keepPolling; + NVSWITCH_TIMEOUT timeout; + NvU32 val; + NvBool error = NV_FALSE; + NvU32 sxid; + const char *sxid_desc = NULL; + + // + // NOTE: MMIO discovery has not been performed so only constant BAR0 offset + // addressing can be performed. + // + + // BAR0 offset 0 should always contain valid data -- unless it doesn't + val = NVSWITCH_OFF_RD32(device, 0); + if (val == 0) + { + error = NV_TRUE; + sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE; + sxid_desc = "Firmware recovery mode"; + } + else if ((val == 0xFFFFFFFF) || ((val & 0xFFFF0000) == 0xBADF0000)) + { + error = NV_TRUE; + sxid = NVSWITCH_ERR_HW_HOST_IO_FAILURE; + sxid_desc = "IO failure"; + } + else if (!IS_FMODEL(device)) + { + // check if FSP successfully started + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); + if (FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val)) + { + break; + } + + nvswitch_os_sleep(1); + } + while (keepPolling); + if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val)) + { + error = NV_TRUE; + sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE; + sxid_desc = "Firmware initialization failure"; + } + } + + if (error) + { + NVSWITCH_RAW_ERROR_LOG_TYPE report = { 0, { 0 } }; + NVSWITCH_RAW_ERROR_LOG_TYPE report_saw = {0, { 0 }}; + NvU32 report_idx = 0; + NvU32 i; + + val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); + report.data[report_idx++] = val; + NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n", + __FUNCTION__, val); + + for (i = 0; i <= 15; i++) + { + val = NVSWITCH_OFF_RD32(device, + NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 + NV_NVLSAW_SW_SCRATCH(i)); + report_saw.data[i] = val; + NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n", + __FUNCTION__, i, val); + } + + for (i = 0; i < NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1; i++) + { + val = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i)); + report.data[report_idx++] = val; + NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n", + __FUNCTION__, i, val); + } + + // Include useful scratch information for triage + NVSWITCH_PRINT_SXID_NO_BBX(device, sxid, + "Fatal, %s (0x%x/0x%x, 0x%x, 0x%x, 0x%x/0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", sxid_desc, + report.data[0], report.data[1], report.data[2], report.data[3], report.data[4], + report_saw.data[0], report_saw.data[1], report_saw.data[12], report_saw.data[14], report_saw.data[15]); + + return -NVL_INITIALIZATION_TOTAL_FAILURE; + } + + return NVL_SUCCESS; +} + +NvlStatus nvswitch_read_vbios_link_entries_ls10 ( nvswitch_device *device, diff --git a/src/common/nvswitch/kernel/nvswitch.c b/src/common/nvswitch/kernel/nvswitch.c index 02b68c1fc..93c576219 100644 --- a/src/common/nvswitch/kernel/nvswitch.c +++ b/src/common/nvswitch/kernel/nvswitch.c @@ -30,6 +30,7 @@ #include "flcn/haldefs_flcnable_nvswitch.h" #include "flcn/flcn_nvswitch.h" #include "soe/soe_nvswitch.h" +#include "soe/soeififr.h" #include "nvVer.h" #include "nvlink_inband_msg.h" @@ -1345,7 +1346,6 @@ nvswitch_lib_initialize_device NvU8 link_num; nvlink_link *link = NULL; NvBool is_blacklisted_by_os = NV_FALSE; - NvU64 mode; if (!NVSWITCH_IS_DEVICE_ACCESSIBLE(device)) { @@ -1508,18 +1508,19 @@ nvswitch_lib_initialize_device nvswitch_reset_persistent_link_hw_state(device, link_num); - if(_nvswitch_corelib_get_dl_link_mode(link, &mode) != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, "%s: nvlipt_lnk_status: Failed to check link mode! LinkId %d\n", - __FUNCTION__, link_num); - } - else if(mode == NVLINK_LINKSTATE_FAULT) - { - NVSWITCH_PRINT(device, INFO, "%s: retraining LinkId %d\n", - __FUNCTION__, link_num); - nvswitch_reset_and_train_link(device, link); - } + // + // During Nvswitch initialization, the default L1 thresholds are programmed by the + // BIOS from the BIOS tables. Save these L1 Threshold Values in scratch registers + // for use when resetting the thresholds to default. + // + nvswitch_program_l1_scratch_reg(device, link_num); + // + // WAR : Initializing the L1 threshold registers at this point as a WAR for + // Bug 3963639 where it was discussed that the L1 threshold register should have + // the default value for all available links and not just for active links. + // + nvswitch_init_lpwr_regs(link); } retval = nvswitch_set_training_mode(device); @@ -1623,6 +1624,10 @@ nvswitch_lib_post_init_device ) { NvlStatus retval; + NvlStatus status; + NvU32 link_num; + NvU64 mode; + nvlink_link *link; if (!NVSWITCH_IS_DEVICE_INITIALIZED(device)) { @@ -1634,7 +1639,7 @@ nvswitch_lib_post_init_device { return retval; } - + if (nvswitch_is_bios_supported(device)) { retval = nvswitch_bios_get_image(device); @@ -1670,6 +1675,41 @@ nvswitch_lib_post_init_device (void)nvswitch_launch_ALI(device); } + // + // There is an edge case where a hypervisor may not send same number + // of reset to switch and GPUs, so try to re-train links in fault + // if possible + // + for (link_num=0; link_num < nvswitch_get_num_links(device); link_num++) + { + // Sanity check + if (!nvswitch_is_link_valid(device, link_num)) + { + continue; + } + + status = nvlink_lib_get_link(device->nvlink_device, link_num, &link); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to get link for LinkId %d\n", + __FUNCTION__, link_num); + continue; + } + + // If the link is in fault then re-train + if(_nvswitch_corelib_get_dl_link_mode(link, &mode) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvlipt_lnk_status: Failed to check link mode! LinkId %d\n", + __FUNCTION__, link_num); + } + else if(mode == NVLINK_LINKSTATE_FAULT) + { + NVSWITCH_PRINT(device, INFO, "%s: retraining LinkId %d\n", + __FUNCTION__, link_num); + nvswitch_reset_and_train_link(device, link); + } + } + return NVL_SUCCESS; } @@ -3437,6 +3477,46 @@ _nvswitch_ctrl_get_inforom_bbx_sxid } static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_sys_info +( + nvswitch_device *device, + NVSWITCH_GET_SYS_INFO_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_SYS_INFO, (void *)params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_time_info +( + nvswitch_device *device, + NVSWITCH_GET_TIME_INFO_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TIME_INFO, (void *)params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_temp_data +( + nvswitch_device *device, + NVSWITCH_GET_TEMP_DATA_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_DATA, (void *)params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_temp_samples +( + nvswitch_device *device, + NVSWITCH_GET_TEMP_SAMPLES_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_SAMPLES, (void *)params); +} + +static NvlStatus _nvswitch_ctrl_get_nvlink_lp_counters ( nvswitch_device *device, @@ -4617,6 +4697,25 @@ nvswitch_init_lpwr_regs device->hal.nvswitch_init_lpwr_regs(link); } +void +nvswitch_program_l1_scratch_reg +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + device->hal.nvswitch_program_l1_scratch_reg(device, linkNumber); +} + +NvlStatus +nvswitch_check_io_sanity +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_check_io_sanity(device); +} + NvlStatus nvswitch_launch_ALI ( @@ -5132,6 +5231,26 @@ nvswitch_lib_ctrl NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_POWER, _nvswitch_ctrl_therm_read_power, NVSWITCH_GET_POWER_PARAMS); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_SYS_INFO, + _nvswitch_ctrl_get_inforom_bbx_sys_info, + NVSWITCH_GET_SYS_INFO_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_TIME_INFO, + _nvswitch_ctrl_get_inforom_bbx_time_info, + NVSWITCH_GET_TIME_INFO_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_TEMP_DATA, + _nvswitch_ctrl_get_inforom_bbx_temp_data, + NVSWITCH_GET_TEMP_DATA_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_TEMP_SAMPLES, + _nvswitch_ctrl_get_inforom_bbx_temp_samples, + NVSWITCH_GET_TEMP_SAMPLES_PARAMS, + osPrivate, flags); default: nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd); diff --git a/src/common/sdk/nvidia/inc/class/cl90e7.h b/src/common/sdk/nvidia/inc/class/cl90e7.h new file mode 100644 index 000000000..3219f131d --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl90e7.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90e7_h_ +#define _cl90e7_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define GF100_SUBDEVICE_INFOROM (0x000090e7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90e7_h + diff --git a/src/common/sdk/nvidia/inc/class/clcba2.h b/src/common/sdk/nvidia/inc/class/clcba2.h index 86936384e..adfeaed33 100644 --- a/src/common/sdk/nvidia/inc/class/clcba2.h +++ b/src/common/sdk/nvidia/inc/class/clcba2.h @@ -118,6 +118,7 @@ typedef volatile struct _clcba2_tag0 { // Class definitions #define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024) +#define NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES (1024*1024*1024) // Errors #define NVCBA2_ERROR_NONE (0x00000000) @@ -149,6 +150,7 @@ typedef volatile struct _clcba2_tag0 { #define NVCBA2_ERROR_SCRUBBER_INVALD_ADDRESS (0x0000001a) #define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b) #define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c) +#define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED (0x0000001d) #ifdef __cplusplus }; /* extern "C" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h index f68cd2912..b1767070d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h @@ -227,7 +227,36 @@ typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS { NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE]; } NV0080_CTRL_FB_GET_CAPS_V2_PARAMS; +/** + * NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY + * + * When clients allocate video memory specifying _DEFAULT (0) for + * NVOS32_ATTR_PHYSICALITY, RM will usually allocate contiguous memory. + * Clients can change that behavior with this command so that _DEFAULT maps to + * another value. + * + * The expectation is that clients currently implicitly rely on the default, + * but can be incrementally updated to explicitly specify _CONTIGUOUS where + * necessary and change the default for their allocations to _NONCONTIGUOUS or + * _ALLOW_NONCONTIGUOUS. + * + * In the future RM may be updated to globally default to _NONCONTIGUOUS or + * _ALLOW_NONCONTIGUOUS, and at that point this can be removed. + */ +#define NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY (0x801308) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS { + NvU32 value; +} NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS; +typedef enum NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY { + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3, +} NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY; /* _ctrl0080fb_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h index a41e40f5a..ab4bd4df4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h @@ -887,10 +887,6 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS { * This parameter is set by the client to indicate the * gpuId of the GPU to which the display to be optimized * is attached. - * display - * This parameter is not used by RM currently. - * Clients can ignore this parameter. Note that this - * parameter will be removed in future. * output * This parameter is set by the client to indicate the * output resource type of the display to be optimized. @@ -1033,6 +1029,12 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS { * optimal pixel clock to use with the adjusted mode, * in units of Hz. * + * + * bOptimized[out] + * This is set to NV_TRUE if the timings were successfully optimized, and + * NV_FALSE otherwise. + * + * * Progressive Raster Structure * * hSyncEnd hTotal @@ -1145,28 +1147,29 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS { #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U) typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS { - NvU32 gpuId; - NvU32 display; - NvU32 output; - NvU32 protocol; - NvU32 structure; - NvU32 adjust; - NvU32 hDeltaStep; - NvU32 hDeltaMax; - NvU32 vDeltaStep; - NvU32 vDeltaMax; - NvU32 hSyncEnd; - NvU32 hBlankEnd; - NvU32 hBlankStart; - NvU32 hTotal; - NvU32 vSyncEnd; - NvU32 vBlankEnd; - NvU32 vBlankStart; - NvU32 vInterlacedBlankEnd; - NvU32 vInterlacedBlankStart; - NvU32 vTotal; - NvU32 refreshX10K; - NvU32 pixelClockHz; + NvU32 gpuId; + NvU32 output; + NvU32 protocol; + NvU32 structure; + NvU32 adjust; + NvU32 hDeltaStep; + NvU32 hDeltaMax; + NvU32 vDeltaStep; + NvU32 vDeltaMax; + NvU32 hSyncEnd; + NvU32 hBlankEnd; + NvU32 hBlankStart; + NvU32 hTotal; + NvU32 vSyncEnd; + NvU32 vBlankEnd; + NvU32 vBlankStart; + NvU32 vInterlacedBlankEnd; + NvU32 vInterlacedBlankStart; + NvU32 vTotal; + NvU32 refreshX10K; + NvU32 pixelClockHz; + + NvBool bOptimized; } NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS; /* output values */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h new file mode 100644 index 000000000..f3ea79e77 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include <nvtypes.h> + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e7.finn +// + +#include "nvfixedtypes.h" +#include "ctrl/ctrlxxxx.h" +/* GF100_SUBDEVICE_INFOROM control commands and parameters */ + +#define NV90E7_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90E7, NV90E7_CTRL_##cat, idx) + +/* Command categories (6 bits) */ +#define NV90E7_CTRL_RESERVED (0x00) +#define NV90E7_CTRL_BBX (0x01) + + + +/* + * NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME + * + * This command is used to query the last BBX flush timestamp and duration. If BBX has not yet + * been flushed, the status returned is NV_ERR_NOT_READY. + * + * timestamp + * This parameter specifies the start timestamp of the last BBX flush. + * + * durationUs + * This parameter specifies the duration (us) of the last BBX flush. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_READY + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME (0x90e70113) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID" */ + +#define NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU32 durationUs; +} NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS; + + + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h index 74bab8e6d..187fe2042 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -556,4 +556,36 @@ typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS { NVB0CC_CTRL_HES_TYPE type; } NVB0CC_CTRL_RELEASE_HES_PARAMS; +/*! + * NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST + * + * Disable the Dynamic MMA clock boost during profiler lifetime. + * + */ +#define NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST (0xb0cc0117) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS { + /*! + * [in]: En/Disable Dynamic MMA Boost. True = disable Boost; False = re-enable Boost. + */ + NvBool disable; +} NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS + * + * Request the Dynamic MMA clock boost feature enablement status. + * + */ +#define NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS (0xb0cc0118) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS { + /*! + * [out]: Dynamic MMA Boost status: true = boost enabled/available; False = Boost disabled/unavailable. + */ + NvBool enabled; +} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS; + /* _ctrlb0ccprofiler_h_ */ diff --git a/src/common/sdk/nvidia/inc/g_finn_rm_api.h b/src/common/sdk/nvidia/inc/g_finn_rm_api.h index 7f26fd544..588f2137c 100644 --- a/src/common/sdk/nvidia/inc/g_finn_rm_api.h +++ b/src/common/sdk/nvidia/inc/g_finn_rm_api.h @@ -558,8 +558,6 @@ typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER; typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED; #define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX; -#define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR; #define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U) typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED; diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index a04ecd4f0..ed4d63072 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -121,7 +121,9 @@ #define NVLINK_FLA_PRIV_ERR (137) #define ROBUST_CHANNEL_DLA_ERROR (138) #define ROBUST_CHANNEL_FAST_PATH_ERROR (139) -#define ROBUST_CHANNEL_LAST_ERROR (ROBUST_CHANNEL_FAST_PATH_ERROR) +#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140) +#define GPU_INIT_ERROR (143) +#define ROBUST_CHANNEL_LAST_ERROR (GPU_INIT_ERROR) // Indexed CE reference diff --git a/src/common/shared/inc/nvdevid.h b/src/common/shared/inc/nvdevid.h index 08a32c3f5..355c423b4 100644 --- a/src/common/shared/inc/nvdevid.h +++ b/src/common/shared/inc/nvdevid.h @@ -446,9 +446,13 @@ #define FOXCONN_EINSTEIN_64_DEVID 0xA1C1 #define FOXCONN_EINSTEIN_64_SSDEVID 0x7270 -// Lenovo Tomcat Workstation +// Lenovo Tomcat/Falcon/Hornet Workstations #define LENOVO_TOMCAT_DEVID 0x1B81 #define LENOVO_TOMCAT_SSDEVID 0x104e +#define LENOVO_FALCON_DEVID 0x7A8A +#define LENOVO_FALCON_SSDEVID 0x1055 +#define LENOVO_HORNET_DEVID 0x7A8A +#define LENOVO_HORNET_SSDEVID 0x1056 // NVIDIA C51 #define NVIDIA_C51_DEVICE_ID_MIN 0x2F0 @@ -626,6 +630,7 @@ enum { , CS_INTEL_1B81 , CS_INTEL_18DC , CS_INTEL_7A04 +, CS_AMPERE_AMPEREONE , CS_MAX_PCIE }; diff --git a/src/common/uproc/os/common/include/libos_v3_crashcat.h b/src/common/uproc/os/common/include/libos_v3_crashcat.h new file mode 100644 index 000000000..1aafd2ed1 --- /dev/null +++ b/src/common/uproc/os/common/include/libos_v3_crashcat.h @@ -0,0 +1,174 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef LIBOS_V3_CRASH_CAT_H +#define LIBOS_V3_CRASH_CAT_H + +#include "nv-crashcat.h" +#include "nv-crashcat-decoder.h" + +// libosv3 implements the CrashCat V1 protocol with the following implementation-defined bits + +typedef enum +{ + LibosPanicReasonUnspecified = 0x00, + LibosPanicReasonUnhandledState = 0x01, + LibosPanicReasonInvalidConfiguration = 0x02, + LibosPanicReasonFatalHardwareError = 0x03, + LibosPanicReasonInsufficientResources = 0x04, + LibosPanicReasonTimeout = 0x05, + LibosPanicReasonEnvCallFailed = 0x06, + LibosPanicReasonAsanMemoryError = 0x08, + LibosPanicReasonProgrammingError = 0x0a, + LibosPanicReasonAssertionFailed = 0x0b, + LibosPanicReasonTrapKernelPanic = 0x0c, + LibosPanicReasonTrapInstruction = 0x0d, + LibosPanicReasonCount +} LibosPanicReason; + +typedef enum{ + LibosKernelModuleInit = 0x00, + LibosKernelModuleIpi = 0x01, + LibosKernelModuleLoader = 0x02, + LibosKernelModulePartition = 0x03, + LibosKernelModuleSbi = 0x04, + LibosKernelModulePagetable = 0x05, + LibosKernelModuleAddressSpace = 0x06, + LibosKernelModuleIdentity = 0x07, + LibosKernelModuleObjectPool = 0x08, + LibosKernelModulePageState = 0x09, + LibosKernelModuleMemoryPool = 0x10, + LibosKernelModuleBuddyState = 0x11, + LibosKernelModuleServer = 0x12, + LibosKernelModuleDmaDriver = 0x13, + LibosKernelModuleExtIntrDriver = 0x14, + LibosKernelModuleSoftMmuCore = 0x15, + LibosKernelModulePagestream = 0x16, + LibosKernelModuleTask = 0x17, + LibosKernelModuleGdmaDriver = 0x18, + LibosKernelModuleCacheDriver = 0x19, + LibosKernelModuleMinTree = 0x20, + LibosKernelModuleList = 0x21, + LibosKernelModuleSpinlock = 0x22, + LibosKernelModuleScheduler = 0x23, + LibosKernelModulePort = 0x24, + LibosKernelModuleGlobalPort = 0x25, + LibosKernelModuleProxyPort = 0x26, + LibosKernelModuleTimer = 0x27, +} LibosKernelModule; + +// NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE (bits 63:0) - "LIBOS3.1" +#define NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE_LIBOS3 (0x4C49424F53332E31ull) + +// NV_CRASHCAT_REPORT_V1_REPORTER_ID_IMPL_DEF (bits 63:18) +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID 31:24 +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_RESERVED 63:32 +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID_UNSPECIFIED (0xFF) + +static NV_INLINE +void crashcatReportV1SetReporterLibos3TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id) +{ + pReport->reporterId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS3_TASK_ID, + task_id, pReport->reporterId); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterLibos3TaskId(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS3_TASK_ID, pReport->reporterId); +} + +// NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION (bits 31:0) +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_CL 23:0 +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_MINOR 27:24 +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_MAJOR 31:28 + +static NV_INLINE +void crashcatReportV1SetReporterVersionLibos3(NvCrashCatReport_V1 *pReport, NvU32 cl) +{ + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_MAJOR, 3, pReport->reporterData); + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_MINOR, 1, pReport->reporterData); + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_CL, cl, pReport->reporterData); +} + +static NV_INLINE +NvU32 crashcatReportV1ReporterVersionLibos3Cl(NvCrashCatReport_V1 *pReport) +{ + return DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_CL, + crashcatReportV1ReporterVersion(pReport)); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterVersionLibos3Minor(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_MINOR, + crashcatReportV1ReporterVersion(pReport)); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterVersionLibos3Major(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_MAJOR, + crashcatReportV1ReporterVersion(pReport)); +} + +// NV_CRASHCAT_REPORT_V1_SOURCE_ID_IMPL_DEF (63:18) +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID 31:24 +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_RESERVED 63:32 +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID_UNSPECIFIED (0xFF) + +static NV_INLINE +void crashcatReportV1SetSourceLibos3TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id) +{ + pReport->sourceId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS3_TASK_ID, task_id, + pReport->sourceId); +} + +static NV_INLINE +NvU8 crashcatReportV1SourceLibos3TaskId(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS3_TASK_ID, pReport->sourceId); +} + +// NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_IMPL_DEF (63:32) +#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS3_REASON 39:32 +#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS3_RESERVED 63:40 + +static NV_INLINE +void crashcatReportV1SetSourceCauseLibos3Reason(NvCrashCatReport_V1 *pReport, + LibosPanicReason reason) +{ + pReport->sourceCause = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS3_REASON, + reason, pReport->sourceCause); +} + +static NV_INLINE +LibosPanicReason crashcatReportV1SourceCauseLibos3Reason(NvCrashCatReport_V1 *pReport) +{ + return (LibosPanicReason)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS3_REASON, + pReport->sourceCause); +} + +#endif // LIBOS_V3_CRASH_CAT_H diff --git a/src/common/uproc/os/common/include/nv-crashcat-decoder.h b/src/common/uproc/os/common/include/nv-crashcat-decoder.h index ed1aa0685..121dc4b08 100644 --- a/src/common/uproc/os/common/include/nv-crashcat-decoder.h +++ b/src/common/uproc/os/common/include/nv-crashcat-decoder.h @@ -95,7 +95,7 @@ NV_CRASHCAT_PACKET_FORMAT_VERSION crashcatPacketHeaderFormatVersion(NvCrashCatPa static NV_INLINE NvLength crashcatPacketHeaderPayloadSize(NvCrashCatPacketHeader hdr) { - NvU8 unitShift; + NvU8 unitShift = 0; NV_CRASHCAT_MEM_UNIT_SIZE unitSize = (NV_CRASHCAT_MEM_UNIT_SIZE)DRF_VAL64(_CRASHCAT, _PACKET_HEADER, _PAYLOAD_UNIT_SIZE, hdr); switch (unitSize) @@ -104,7 +104,6 @@ NvLength crashcatPacketHeaderPayloadSize(NvCrashCatPacketHeader hdr) case NV_CRASHCAT_MEM_UNIT_SIZE_1KB: unitShift = 10; break; case NV_CRASHCAT_MEM_UNIT_SIZE_4KB: unitShift = 12; break; case NV_CRASHCAT_MEM_UNIT_SIZE_64KB: unitShift = 16; break; - default: return 0; } // Increment size, since the size in the header is size - 1 (payload of 0 size is not encodable) diff --git a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c index 5f6e18c67..3eb2964c5 100644 --- a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c @@ -477,10 +477,10 @@ static int libos_printf_a( # if defined(NVRM) if (logDecode->curLineBufPtr == logDecode->lineBuffer) { - // Prefix every line with NVRM GPUn Ucode-task: filename(lineNumber): + // Prefix every line with NVRM: GPUn Ucode-task: filename(lineNumber): snprintf( logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, - "NVRM GPU%u %s-%s: %s(%u): ", pRec->log->gpuInstance, + NV_PRINTF_ADD_PREFIX("GPU%u %s-%s: %s(%u): "), pRec->log->gpuInstance, logDecode->sourceName, pRec->log->taskPrefix, filename, pRec->meta->lineNumber); logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); } diff --git a/src/nvidia-modeset/include/nvkms-evo.h b/src/nvidia-modeset/include/nvkms-evo.h index 218de01e8..37742914f 100644 --- a/src/nvidia-modeset/include/nvkms-evo.h +++ b/src/nvidia-modeset/include/nvkms-evo.h @@ -182,6 +182,8 @@ NvBool nvDowngradeColorSpaceAndBpc( NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, const NvBool b2Heads1Or, NVDscInfoEvoRec *pDscInfo, const struct NvKmsModeValidationParams *pParams); diff --git a/src/nvidia-modeset/include/nvkms-headsurface-priv.h b/src/nvidia-modeset/include/nvkms-headsurface-priv.h index 854c1d5aa..d799466cc 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface-priv.h +++ b/src/nvidia-modeset/include/nvkms-headsurface-priv.h @@ -481,6 +481,7 @@ static inline void HsIncrementNextIndex( } static inline void HsChangeSurfaceFlipRefCount( + NVDevEvoPtr pDevEvo, NVSurfaceEvoPtr pSurfaceEvo, NvBool increase) { @@ -488,7 +489,7 @@ static inline void HsChangeSurfaceFlipRefCount( if (increase) { nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); } else { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } } } diff --git a/src/nvidia-modeset/include/nvkms-private.h b/src/nvidia-modeset/include/nvkms-private.h index c337819e0..0728fbb92 100644 --- a/src/nvidia-modeset/include/nvkms-private.h +++ b/src/nvidia-modeset/include/nvkms-private.h @@ -68,8 +68,6 @@ NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDev( struct NvKmsPerOpenDev *pOpenDev); const NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDevConst( const struct NvKmsPerOpenDev *pOpenDev); -NVDevEvoPtr nvGetDevEvoFromOpenDev( - const struct NvKmsPerOpenDev *pOpenDev); void nvKmsServiceNonStallInterrupt(void *dataPtr, NvU32 dataU32); diff --git a/src/nvidia-modeset/include/nvkms-surface.h b/src/nvidia-modeset/include/nvkms-surface.h index 0a05242cd..181986e91 100644 --- a/src/nvidia-modeset/include/nvkms-surface.h +++ b/src/nvidia-modeset/include/nvkms-surface.h @@ -47,7 +47,8 @@ void nvEvoIncrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo); void nvEvoDecrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo); void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo); -void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo); +void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo); NvBool nvEvoSurfaceRefCntsTooLarge(const NVSurfaceEvoRec *pSurfaceEvo); diff --git a/src/nvidia-modeset/include/nvkms-types.h b/src/nvidia-modeset/include/nvkms-types.h index 9c83434bb..c5c1433ff 100644 --- a/src/nvidia-modeset/include/nvkms-types.h +++ b/src/nvidia-modeset/include/nvkms-types.h @@ -1221,6 +1221,29 @@ typedef struct _NVEvoDevRec { } apiHead[NVKMS_MAX_HEADS_PER_DISP]; } NVDevEvoRec; +static inline NvBool nvEvoIsConsoleActive(const NVDevEvoRec *pDevEvo) +{ + /* + * If (pDevEvo->modesetOwner == NULL) that means either the vbios + * console or the NVKMS console might be active. + */ + if (pDevEvo->modesetOwner == NULL) { + return TRUE; + } + + /* + * If (pDevEvo->modesetOwner != NULL) but + * pDevEvo->modesetOwnerChanged is TRUE, that means the modeset + * ownership is grabbed by the external client but it hasn't + * performed any modeset and the console is still active. + */ + if ((pDevEvo->modesetOwner != NULL) && pDevEvo->modesetOwnerChanged) { + return TRUE; + } + + return FALSE; +} + /* * The NVHwModeTimingsEvo structure stores all the values necessary to * perform a modeset with EVO diff --git a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h index 16b89c1ca..44ff02d80 100644 --- a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h +++ b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h @@ -99,6 +99,7 @@ typedef struct { NvBool nvkms_output_rounding_fix(void); NvBool nvkms_disable_vrr_memclk_switch(void); +NvBool nvkms_opportunistic_display_sync(void); void nvkms_call_rm (void *ops); void* nvkms_alloc (size_t size, diff --git a/src/nvidia-modeset/src/nvkms-cursor.c b/src/nvidia-modeset/src/nvkms-cursor.c index a766c4667..316d7d22d 100644 --- a/src/nvidia-modeset/src/nvkms-cursor.c +++ b/src/nvidia-modeset/src/nvkms-cursor.c @@ -118,7 +118,7 @@ SetCursorImageOneHead(NVDispEvoPtr pDispEvo, } if (pSurfaceEvoOld) { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvoOld); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvoOld); } pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo = pSurfaceEvoNew; diff --git a/src/nvidia-modeset/src/nvkms-difr.c b/src/nvidia-modeset/src/nvkms-difr.c index 100d0cc3b..0993e13dc 100644 --- a/src/nvidia-modeset/src/nvkms-difr.c +++ b/src/nvidia-modeset/src/nvkms-difr.c @@ -274,8 +274,12 @@ NvU32 nvDIFRPrefetchSurfaces(NVDIFRStateEvoPtr pDifr, size_t l2CacheSize) NvU32 i; NvU32 status; - /* If DIFR is disabled it's because we know we were or will be flipping. */ - if (pDifr->hwDisabled) { + /* + * If DIFR is disabled it's because we know we were or will be flipping, or + * if console is active then the scanout surfaces will get updated by the + * OS console driver without any knowledge of NVKMS. + */ + if (pDifr->hwDisabled || nvEvoIsConsoleActive(pDevEvo)) { return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; } diff --git a/src/nvidia-modeset/src/nvkms-evo.c b/src/nvidia-modeset/src/nvkms-evo.c index 536e958c3..df66461ee 100644 --- a/src/nvidia-modeset/src/nvkms-evo.c +++ b/src/nvidia-modeset/src/nvkms-evo.c @@ -734,6 +734,9 @@ static void TweakTimingsForGsync(const NVDpyEvoRec *pDpyEvo, return; } + nvEvoLogInfoString(pInfoString, + "Adjusting Mode Timings for Quadro Sync Compatibility"); + ret = nvRmApiControl(nvEvoGlobal.clientHandle, pDispEvo->pFrameLockEvo->device, NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING, @@ -744,12 +747,13 @@ static void TweakTimingsForGsync(const NVDpyEvoRec *pDpyEvo, nvAssert(!"Failed to convert to Quadro Sync safe timing"); /* do not apply the timings returned by RM if the call failed */ return; + } else if (!gsyncOptTimingParams.bOptimized) { + nvEvoLogInfoString(pInfoString, " Timings Unchanged."); + return; } nvConstructNvModeTimingsFromHwModeTimings(pTimings, &modeTimings); - nvEvoLogInfoString(pInfoString, - "Adjusting Mode Timings for Quadro Sync Compatibility"); nvEvoLogInfoString(pInfoString, " Old Timings:"); nvEvoLogModeValidationModeTimings(pInfoString, &modeTimings); @@ -1429,7 +1433,13 @@ static void UnlockRasterLockGroup(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo = topo->pDispEvoOrder[i]; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 sd = pDispEvo->displayOwner; - NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; + NVEvoSubDevPtr pEvoSubDev; + + if (pDevEvo->gpus == NULL) { + continue; + } + + pEvoSubDev = &pDevEvo->gpus[sd]; /* Initialize the assembly state */ SyncEvoLockState(); @@ -1665,7 +1675,8 @@ void nvEvoLockStateSetMergeMode(NVDispEvoPtr pDispEvo) /* * FinishModesetOneTopology() - Set up raster lock between GPUs, if applicable, - * for one RasterLockTopology. Called in a loop from nvFinishModesetEvo(). + * unless disabled via kernel module parameter, for one RasterLockTopology. + * Called in a loop from nvFinishModesetEvo(). */ static void FinishModesetOneTopology(RasterLockTopology *topo) @@ -1682,6 +1693,11 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) NVDevEvoPtr pDevEvoFlipLockGroup = NULL; NvBool mergeModeInUse = FALSE; + if (!nvkms_opportunistic_display_sync()) { + /* If opportunistic display sync is disabled, do not attempt rasterlock. */ + return; + } + /* * First, look for devices with VRR enabled. If we find any, go into the * special VRR framelock mode. @@ -5263,13 +5279,6 @@ NvBool nvConstructHwModeTimingsImpCheckEvo( NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS); NvU32 ret; - /* bypass this checking if the user disabled IMP */ - - if ((pParams->overrides & - NVKMS_MODE_VALIDATION_NO_EXTENDED_GPU_CAPABILITIES_CHECK) != 0) { - return TRUE; - } - activeRmId = nvRmAllocDisplayId(pConnectorEvo->pDispEvo, nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId)); if (activeRmId == 0x0) { @@ -5294,11 +5303,18 @@ NvBool nvConstructHwModeTimingsImpCheckEvo( timingsParams[head].pUsage = &timings[head].viewPort.guaranteedUsage; } - ret = nvValidateImpOneDispDowngrade(pConnectorEvo->pDispEvo, timingsParams, - requireBootClocks, - NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE, - /* downgradePossibleHeadsBitMask */ - (NVBIT(NVKMS_MAX_HEADS_PER_DISP) - 1UL)); + /* bypass this checking if the user disabled IMP */ + if ((pParams->overrides & + NVKMS_MODE_VALIDATION_NO_EXTENDED_GPU_CAPABILITIES_CHECK) != 0) { + ret = TRUE; + } else { + ret = nvValidateImpOneDispDowngrade(pConnectorEvo->pDispEvo, timingsParams, + requireBootClocks, + NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE, + /* downgradePossibleHeadsBitMask */ + (NVBIT(NVKMS_MAX_HEADS_PER_DISP) - 1UL)); + } + if (ret) { *pNumHeads = numHeads; } else { @@ -6193,13 +6209,15 @@ NvBool nvDowngradeColorSpaceAndBpc( NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, const NvBool b2Heads1Or, NVDscInfoEvoRec *pDscInfo, const struct NvKmsModeValidationParams *pParams) { NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; - enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; - enum NvKmsDpyAttributeColorBpcValue colorBpc; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = *pColorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc = *pColorBpc; enum NvKmsDpyAttributeColorRangeValue colorRange; const NVColorFormatInfoRec supportedColorFormats = nvGetColorFormatInfo(pDpyEvo); @@ -6214,14 +6232,6 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, return TRUE; } - if (pTimings->yuv420Mode != NV_YUV420_MODE_NONE) { - colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; - colorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; - } else if (!nvGetDefaultColorSpace(&supportedColorFormats, &colorSpace, - &colorBpc)) { - return FALSE; - } - if (colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) { colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; } else { @@ -6247,6 +6257,8 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, return FALSE; } + *pColorSpace = colorSpace; + *pColorBpc = colorBpc; return TRUE; } diff --git a/src/nvidia-modeset/src/nvkms-headsurface-config.c b/src/nvidia-modeset/src/nvkms-headsurface-config.c index 6238a503f..50e4613ec 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-config.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-config.c @@ -1069,23 +1069,11 @@ void nvHsConfigInitSwapGroup( NVHsChannelConfig *pChannelConfig = &pHsConfigOneHead->channelConfig; /* - * If (pDevEvo->modesetOwner == NULL) that means either the vbios - * console or the NVKMS console might be active, the console - * surface may not be set up to be the source of headSurface - * operations, and NVKMS may be unloaded, so we can't have the - * display rely on headSurface. + * The console surface may not be set up to be the source of + * headSurface operations, and NVKMS may be unloaded, so we can't + * have the display rely on headSurface. */ - if (pDevEvo->modesetOwner == NULL) { - continue; - } - - /* - * If (pDevEvo->modesetOwner != NULL) but - * pDevEvo->modesetOwnerChanged is TRUE, that means the modeset - * ownership is grabbed by the external client but it hasn't - * performed any modeset and the console is still active. - */ - if ((pDevEvo->modesetOwner != NULL) && pDevEvo->modesetOwnerChanged) { + if (nvEvoIsConsoleActive(pDevEvo)) { continue; } @@ -1837,16 +1825,21 @@ static void HsConfigInitFlipQueue( } static void HsConfigUpdateSurfaceRefCount( + NVDevEvoPtr pDevEvo, const NVHsChannelConfig *pChannelConfig, NvBool increase) { - HsChangeSurfaceFlipRefCount(pChannelConfig->warpMesh.pSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->warpMesh.pSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->pBlendTexSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->pBlendTexSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->pOffsetTexSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->pOffsetTexSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->cursor.pSurfaceEvo, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->cursor.pSurfaceEvo, increase); } /*! @@ -2258,6 +2251,7 @@ void nvHsConfigStart( */ if (pHsConfigOneHead->pHsChannel != NULL) { HsConfigUpdateSurfaceRefCount( + pDevEvo, &pHsConfigOneHead->channelConfig, TRUE /* increase */); } @@ -2268,6 +2262,7 @@ void nvHsConfigStart( */ if (pDispEvo->pHsChannel[apiHead] != NULL) { HsConfigUpdateSurfaceRefCount( + pDevEvo, &pDispEvo->pHsChannel[apiHead]->config, FALSE /* increase */); } diff --git a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c index c3a843cde..51254f05e 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c @@ -169,6 +169,8 @@ static void HsIoctlSetCursorImage( NVHsChannelEvoRec *pHsChannel, NVSurfaceEvoRec *pSurfaceEvo) { + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + /* * Increment the refcnt of the new surface, and * decrement the refcnt of the old surface. @@ -178,10 +180,10 @@ static void HsIoctlSetCursorImage( */ HsChangeSurfaceFlipRefCount( - pSurfaceEvo, TRUE /* increase */); + pDevEvo, pSurfaceEvo, TRUE /* increase */); HsChangeSurfaceFlipRefCount( - pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); + pDevEvo, pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); pHsChannel->config.cursor.pSurfaceEvo = pSurfaceEvo; diff --git a/src/nvidia-modeset/src/nvkms-headsurface.c b/src/nvidia-modeset/src/nvkms-headsurface.c index be7fcf7bc..a459a6649 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface.c +++ b/src/nvidia-modeset/src/nvkms-headsurface.c @@ -549,21 +549,22 @@ static NvBool HsFlipQueueEntryIsReady( * Update the reference count of all the surfaces described in the pFlipState. */ static void HsUpdateFlipQueueEntrySurfaceRefCount( + NVDevEvoPtr pDevEvo, const NVHsLayerRequestedFlipState *pFlipState, NvBool increase) { HsChangeSurfaceFlipRefCount( - pFlipState->pSurfaceEvo[NVKMS_LEFT], increase); + pDevEvo, pFlipState->pSurfaceEvo[NVKMS_LEFT], increase); HsChangeSurfaceFlipRefCount( - pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase); + pDevEvo, pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase); if (!pFlipState->syncObject.usingSyncpt) { HsChangeSurfaceFlipRefCount( - pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); + pDevEvo, pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); HsChangeSurfaceFlipRefCount( - pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); + pDevEvo, pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); } } @@ -602,7 +603,7 @@ static void HsReleaseFlipQueueEntry( * HeadSurface no longer needs to read from the surfaces in pFlipState; * decrement their reference counts. */ - HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE); + HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE); } /*! @@ -684,6 +685,7 @@ void nvHsPushFlipQueueEntry( const NvU8 layer, const NVHsLayerRequestedFlipState *pFlipState) { + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; NVHsChannelFlipQueueEntry *pEntry = nvCalloc(1, sizeof(*pEntry)); @@ -700,7 +702,7 @@ void nvHsPushFlipQueueEntry( /* Increment the ref counts on the surfaces in the flip queue entry. */ - HsUpdateFlipQueueEntrySurfaceRefCount(&pEntry->hwState, TRUE); + HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, &pEntry->hwState, TRUE); /* "Fast forward" through existing flip queue entries that are ready. */ @@ -722,7 +724,7 @@ void nvHsPushFlipQueueEntry( * If this function returns TRUE, it is the caller's responsibility to * eventually call * - * HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE) + * HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE) * * for the returned pFlipState. * diff --git a/src/nvidia-modeset/src/nvkms-hw-flip.c b/src/nvidia-modeset/src/nvkms-hw-flip.c index 1496a0981..f45da600c 100644 --- a/src/nvidia-modeset/src/nvkms-hw-flip.c +++ b/src/nvidia-modeset/src/nvkms-hw-flip.c @@ -1796,7 +1796,7 @@ static void ChangeSurfaceFlipRefCount( if (increase) { nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); } else { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } } } diff --git a/src/nvidia-modeset/src/nvkms-modepool.c b/src/nvidia-modeset/src/nvkms-modepool.c index d8209c1e1..35e7546bd 100644 --- a/src/nvidia-modeset/src/nvkms-modepool.c +++ b/src/nvidia-modeset/src/nvkms-modepool.c @@ -1645,6 +1645,10 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, NvU32 head; NvBool ret = FALSE; + const NVColorFormatInfoRec supportedColorFormats = nvGetColorFormatInfo(pDpyEvo); + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + if (modeName[0] == '\0') { nvBuildModeName(pModeTimings->hVisible, pModeTimings->vVisible, localModeName, sizeof(localModeName)); @@ -1701,6 +1705,16 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, b2Heads1Or = nvEvoUse2Heads1OR(pDpyEvo, pTimingsEvo, pParams); + if (pTimingsEvo->yuv420Mode != NV_YUV420_MODE_NONE) { + colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; + colorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } else if (!nvGetDefaultColorSpace(&supportedColorFormats, &colorSpace, + &colorBpc)) { + LogModeValidationEnd(pDispEvo, pInfoString, + "Failed to get default color space and Bpc"); + goto done; + } + if (nvDpyIsHdmiEvo(pDpyEvo)) { if (!nvHdmiFrlQueryConfig(pDpyEvo, &pKmsMode->timings, @@ -1714,8 +1728,8 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, goto done; } } else { - if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, b2Heads1Or, pDscInfo, - pParams)) { + if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, &colorSpace, &colorBpc, + b2Heads1Or, pDscInfo, pParams)) { LogModeValidationEnd(pDispEvo, pInfoString, "DP Bandwidth check failed"); goto done; @@ -1734,28 +1748,20 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, /* Run the raster timings through IMP checking. */ - { - const NVColorFormatInfoRec colorFormats = - nvGetColorFormatInfo(pDpyEvo); - enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; - enum NvKmsDpyAttributeColorBpcValue colorBpc; - - if (!nvGetDefaultColorSpace(&colorFormats, &colorSpace, &colorBpc) || - !nvConstructHwModeTimingsImpCheckEvo(pDpyEvo->pConnectorEvo, - pTimingsEvo, - (pDscInfo->type != - NV_DSC_INFO_EVO_TYPE_DISABLED), - b2Heads1Or, - colorSpace, - colorBpc, - pParams, - impOutTimings, - &impOutNumHeads, - pInfoString)) { - LogModeValidationEnd(pDispEvo, pInfoString, - "GPU extended capability check failed"); - goto done; - } + if (!nvConstructHwModeTimingsImpCheckEvo(pDpyEvo->pConnectorEvo, + pTimingsEvo, + (pDscInfo->type != + NV_DSC_INFO_EVO_TYPE_DISABLED), + b2Heads1Or, + colorSpace, + colorBpc, + pParams, + impOutTimings, + &impOutNumHeads, + pInfoString)) { + LogModeValidationEnd(pDispEvo, pInfoString, + "GPU extended capability check failed"); + goto done; } nvAssert(impOutNumHeads > 0); diff --git a/src/nvidia-modeset/src/nvkms-surface.c b/src/nvidia-modeset/src/nvkms-surface.c index 38298a327..bc8ac003f 100644 --- a/src/nvidia-modeset/src/nvkms-surface.c +++ b/src/nvidia-modeset/src/nvkms-surface.c @@ -958,7 +958,7 @@ void nvEvoFreeClientSurfaces(NVDevEvoPtr pDevEvo, nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); if (isOwner) { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } else { nvEvoDecrementSurfaceStructRefCnt(pSurfaceEvo); } @@ -1003,7 +1003,7 @@ void nvEvoUnregisterSurface(NVDevEvoPtr pDevEvo, /* Remove the handle from the calling client's namespace. */ nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } void nvEvoReleaseSurface(NVDevEvoPtr pDevEvo, @@ -1041,15 +1041,13 @@ void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) pSurfaceEvo->structRefCnt++; } -void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) +void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo) { nvAssert(pSurfaceEvo->rmRefCnt >= 1); pSurfaceEvo->rmRefCnt--; if (pSurfaceEvo->rmRefCnt == 0) { - NVDevEvoPtr pDevEvo = - nvGetDevEvoFromOpenDev(pSurfaceEvo->owner.pOpenDev); - /* * Don't sync if this surface was registered as not requiring display * hardware access, to WAR timeouts that result from OGL unregistering @@ -1224,7 +1222,7 @@ void nvEvoUnregisterDeferredRequestFifo( pDeferredRequestFifo->fifo, 0); - nvEvoDecrementSurfaceRefCnts(pDeferredRequestFifo->pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pDeferredRequestFifo->pSurfaceEvo); nvFree(pDeferredRequestFifo); } diff --git a/src/nvidia-modeset/src/nvkms.c b/src/nvidia-modeset/src/nvkms.c index d597be7b6..793362710 100644 --- a/src/nvidia-modeset/src/nvkms.c +++ b/src/nvidia-modeset/src/nvkms.c @@ -5917,13 +5917,6 @@ NvBool nvSurfaceEvoInAnyOpens(const NVSurfaceEvoRec *pSurfaceEvo) } #endif -NVDevEvoPtr nvGetDevEvoFromOpenDev( - const struct NvKmsPerOpenDev *pOpenDev) -{ - nvAssert(pOpenDev != NULL); - return pOpenDev->pDevEvo; -} - const struct NvKmsFlipPermissions *nvGetFlipPermissionsFromOpenDev( const struct NvKmsPerOpenDev *pOpenDev) { diff --git a/src/nvidia/arch/nvalloc/common/inc/nvcst.h b/src/nvidia/arch/nvalloc/common/inc/nvcst.h index b26e83e9f..8dd18d684 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvcst.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvcst.h @@ -89,6 +89,7 @@ CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc) CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc) CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc) CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc) +CHIPSET_SETUP_FUNC(Ampere_AmpereOne_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_TH500_setupFunc) @@ -186,6 +187,7 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, + {PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, {PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL}, {PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc}, @@ -264,6 +266,14 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_HYGON, 0x790E, CS_HYGON_C86, "Hygon-C86-7151", NULL}, {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX, "Marvell Octeon CN96xx", ARMV8_generic_setupFunc}, {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX, "Marvell Octeon CN98xx", ARMV8_generic_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, /////////////////////////////////////////////////////////////////////////////////////////////////// @@ -362,6 +372,14 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx {PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian + {PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne // last element must have chipset CS_UNKNOWN (zero) {0, 0, CS_UNKNOWN} diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-priv.h b/src/nvidia/arch/nvalloc/unix/include/nv-priv.h index 92b46eb62..48560539f 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-priv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-priv.h @@ -358,6 +358,7 @@ typedef struct */ NvU64 s0ix_gcoff_max_fb_size; + NvU32 pmc_boot_1; NvU32 pmc_boot_42; } nv_priv_t; diff --git a/src/nvidia/arch/nvalloc/unix/include/nv.h b/src/nvidia/arch/nvalloc/unix/include/nv.h index 3a71d7e40..c8fad3c29 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv.h @@ -924,6 +924,7 @@ NV_STATUS NV_API_CALL rm_ioctl (nvidia_stack_t *, nv_state_t * NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *); void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t); NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *); diff --git a/src/nvidia/arch/nvalloc/unix/include/os-interface.h b/src/nvidia/arch/nvalloc/unix/include/os-interface.h index 52699ac19..5249e124e 100644 --- a/src/nvidia/arch/nvalloc/unix/include/os-interface.h +++ b/src/nvidia/arch/nvalloc/unix/include/os-interface.h @@ -207,9 +207,13 @@ enum os_pci_req_atomics_type { OS_INTF_PCIE_REQ_ATOMICS_128BIT }; NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); +NV_STATUS NV_API_CALL os_get_numa_node_memory_usage (NvS32, NvU64 *, NvU64 *); NV_STATUS NV_API_CALL os_numa_add_gpu_memory (void *, NvU64, NvU64, NvU32 *); NV_STATUS NV_API_CALL os_numa_remove_gpu_memory (void *, NvU64, NvU64, NvU32); NV_STATUS NV_API_CALL os_offline_page_at_address(NvU64 address); +void* NV_API_CALL os_get_pid_info(void); +void NV_API_CALL os_put_pid_info(void *pid_info); +NV_STATUS NV_API_CALL os_find_ns_pid(void *pid_info, NvU32 *ns_pid); extern NvU32 os_page_size; extern NvU64 os_page_mask; diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c index bb03eac64..6ebb9568a 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os.c +++ b/src/nvidia/arch/nvalloc/unix/src/os.c @@ -404,36 +404,33 @@ static NV_STATUS setNumaPrivData NV_STATUS rmStatus = NV_OK; void *pAllocPrivate = NULL; NvU64 *addrArray = NULL; - NvU64 numOsPages = pMemDesc->PageCount; + NvU64 numPages = pMemDesc->PageCount; + NvU64 i; - addrArray = pMemDesc->_pteArray; - - if (NV_RM_PAGE_SIZE < os_page_size) + addrArray = portMemAllocNonPaged(numPages * sizeof(NvU64)); + if (addrArray == NULL) { - NvU64 numPages; - NvU64 i; + return NV_ERR_NO_MEMORY; + } - numPages = pMemDesc->PageCount; - addrArray = portMemAllocNonPaged(numPages * sizeof(NvU64)); - if (addrArray == NULL) - { - return NV_ERR_NO_MEMORY; - } + portMemCopy((void*)addrArray, + (numPages * sizeof(NvU64)), + (void*)memdescGetPteArray(pMemDesc, AT_CPU), + (numPages * sizeof(NvU64))); - portMemCopy((void*)addrArray, - (numPages * sizeof(NvU64)), (void*)pMemDesc->_pteArray, - (numPages * sizeof(NvU64))); + if (NV_RM_PAGE_SIZE < os_page_size) + { RmDeflateRmToOsPageArray(addrArray, numPages); - numOsPages = NV_RM_PAGES_TO_OS_PAGES(numPages); + numPages = NV_RM_PAGES_TO_OS_PAGES(numPages); + } - for (i = 0; i < numOsPages; i++) - { - // Update GPA to system physical address - addrArray[i] += pKernelMemorySystem->coherentCpuFbBase; - } + for (i = 0; i < numPages; i++) + { + // Update GPA to system physical address + addrArray[i] += pKernelMemorySystem->coherentCpuFbBase; } - rmStatus = nv_register_phys_pages(nv, addrArray, numOsPages, NV_MEMORY_CACHED, &pAllocPrivate); + rmStatus = nv_register_phys_pages(nv, addrArray, numPages, NV_MEMORY_CACHED, &pAllocPrivate); if (rmStatus != NV_OK) { goto errors; @@ -442,10 +439,7 @@ static NV_STATUS setNumaPrivData memdescSetMemData(pMemDesc, pAllocPrivate, NULL); errors: - if (NV_RM_PAGE_SIZE < os_page_size) - { - portMemFree(addrArray); - } + portMemFree(addrArray); return rmStatus; } @@ -684,6 +678,21 @@ NV_STATUS osGetCurrentThread(OS_THREAD_HANDLE *pThreadId) return rmStatus; } +void* osGetPidInfo(void) +{ + return os_get_pid_info(); +} + +void osPutPidInfo(void *pOsPidInfo) +{ + os_put_pid_info(pOsPidInfo); +} + +NV_STATUS osFindNsPid(void *pOsPidInfo, NvU32 *pNsPid) +{ + return os_find_ns_pid(pOsPidInfo, pNsPid); +} + NV_STATUS osAttachToProcess(void** ppProcessInfo, NvU32 ProcessId) { // @@ -5372,6 +5381,28 @@ osReleaseGpuOsInfo } /*! + * @brief Get free, total memory of a NUMA node by NUMA node ID from kernel. + * + * @param[in] numaId NUMA node ID. + * @param[out] free_memory_bytes free memory in bytes. + * @param[out] total_memory_bytes total memory in bytes. + * + */ +void +osGetNumaMemoryUsage +( + NvS32 numaId, + NvU64 *free_memory_bytes, + NvU64 *total_memory_bytes +) +{ + NV_STATUS status = os_get_numa_node_memory_usage(numaId, + free_memory_bytes, + total_memory_bytes); + NV_ASSERT(status == NV_OK); +} + +/*! * @brief Add GPU memory as a NUMA node. * * @param[in/out] pOsGpuInfo OS specific GPU information pointer diff --git a/src/nvidia/arch/nvalloc/unix/src/osinit.c b/src/nvidia/arch/nvalloc/unix/src/osinit.c index 8022c6c34..7f9cef7a0 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osinit.c +++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c @@ -1160,6 +1160,7 @@ NvBool RmInitPrivateState( nv_priv_t *nvp; NvU32 gpuId; NvU32 pmc_boot_0 = 0; + NvU32 pmc_boot_1 = 0; NvU32 pmc_boot_42 = 0; NV_SET_NV_PRIV(pNv, NULL); @@ -1177,6 +1178,7 @@ NvBool RmInitPrivateState( } pmc_boot_0 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_0); + pmc_boot_1 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_1); pmc_boot_42 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_42); os_unmap_kernel_space(pNv->regs->map_u, os_page_size); @@ -1216,6 +1218,7 @@ NvBool RmInitPrivateState( os_mem_set(nvp, 0, sizeof(*nvp)); nvp->status = NV_ERR_INVALID_STATE; nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_1 = pmc_boot_1; nvp->pmc_boot_42 = pmc_boot_42; NV_SET_NV_PRIV(pNv, nvp); @@ -1234,7 +1237,7 @@ void RmClearPrivateState( nv_i2c_adapter_entry_t i2c_adapters[MAX_I2C_ADAPTERS]; nv_dynamic_power_t dynamicPowerCopy; NvU32 x = 0; - NvU32 pmc_boot_0, pmc_boot_42; + NvU32 pmc_boot_0, pmc_boot_1, pmc_boot_42; // // Do not clear private state after GPU resets, it is used while @@ -1252,6 +1255,7 @@ void RmClearPrivateState( pRegistryCopy = nvp->pRegistry; dynamicPowerCopy = nvp->dynamic_power; pmc_boot_0 = nvp->pmc_boot_0; + pmc_boot_1 = nvp->pmc_boot_1; pmc_boot_42 = nvp->pmc_boot_42; for (x = 0; x < MAX_I2C_ADAPTERS; x++) @@ -1267,6 +1271,7 @@ void RmClearPrivateState( nvp->pRegistry = pRegistryCopy; nvp->dynamic_power = dynamicPowerCopy; nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_1 = pmc_boot_1; nvp->pmc_boot_42 = pmc_boot_42; for (x = 0; x < MAX_I2C_ADAPTERS; x++) diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c index 56a2103cb..9f1369b1c 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c @@ -706,3 +706,27 @@ NV_STATUS rm_gpu_handle_mmu_faults( return status; } +NvBool NV_API_CALL rm_is_msix_allowed( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *pNvp = NV_GET_NV_PRIV(nv); + THREAD_STATE_NODE threadState; + void *fp; + NvBool ret = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + ret = gpumgrIsDeviceMsixAllowed(nv->regs->cpu_address, + pNvp->pmc_boot_1, pNvp->pmc_boot_42); + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return ret; +} diff --git a/src/nvidia/exports_link_command.txt b/src/nvidia/exports_link_command.txt index 182b73239..ff4bff48a 100644 --- a/src/nvidia/exports_link_command.txt +++ b/src/nvidia/exports_link_command.txt @@ -23,6 +23,7 @@ --undefined=rm_isr --undefined=rm_isr_bh --undefined=rm_isr_bh_unlocked +--undefined=rm_is_msix_allowed --undefined=rm_perform_version_check --undefined=rm_power_management --undefined=rm_stop_user_channels diff --git a/src/nvidia/generated/g_allclasses.h b/src/nvidia/generated/g_allclasses.h index 1ab9f5c3c..65c1d132f 100644 --- a/src/nvidia/generated/g_allclasses.h +++ b/src/nvidia/generated/g_allclasses.h @@ -116,6 +116,7 @@ #include <class/clb0cc.h> // MAXWELL_PROFILER #include <class/clb2cc.h> // MAXWELL_PROFILER_DEVICE #include <class/cl90e6.h> // GF100_SUBDEVICE_MASTER +#include <class/cl90e7.h> // GF100_SUBDEVICE_INFOROM #include <class/cl9096.h> // GF100_ZBC_CLEAR #include <class/cl9072.h> // GF100_DISP_SW #include <class/cl9074.h> // GF100_TIMED_SEMAPHORE_SW @@ -585,6 +586,10 @@ #define GF100_SUBDEVICE_MASTER (0x000090e6) #endif +#ifndef GF100_SUBDEVICE_INFOROM +#define GF100_SUBDEVICE_INFOROM (0x000090e7) +#endif + #ifndef GF100_ZBC_CLEAR #define GF100_ZBC_CLEAR (0x00009096) #endif diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c index 92f908f11..19653d8c6 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c @@ -35,22690 +35,22690 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 368640 -// COMPRESSED SIZE (bytes): 362878 +// COMPRESSED SIZE (bytes): 362876 // static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data[] = { - 0x9c, 0x57, 0xc3, 0x62, 0x28, 0x0a, 0x74, 0x8c, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0xcd, 0x1b, 0xdb, 0xb6, 0x9d, 0xf4, 0xfd, 0x40, 0xbb, 0xe8, 0xac, 0xcf, - 0xec, 0xce, 0x88, 0xe2, 0x29, 0xb7, 0x98, 0xd8, 0x79, 0xfc, 0x04, 0x41, 0xa1, 0xe3, 0x80, 0x30, - 0x6d, 0xc3, 0xbd, 0xe7, 0x6d, 0x6e, 0x3b, 0xb9, 0x77, 0xc7, 0xaf, 0x1e, 0x81, 0xc0, 0x0a, 0x63, - 0xa9, 0xc6, 0x51, 0x27, 0x16, 0x8a, 0x35, 0x93, 0x46, 0x29, 0xe0, 0xfe, 0x95, 0xc5, 0xb1, 0xe6, - 0x79, 0x8f, 0x4c, 0x32, 0xf2, 0x6d, 0x3c, 0xae, 0x5a, 0xc7, 0xe2, 0xc4, 0x4a, 0x64, 0x7b, 0x4b, - 0x75, 0x3c, 0x28, 0x3a, 0xb8, 0x87, 0x5d, 0x7d, 0x7d, 0x16, 0x24, 0xc1, 0x71, 0x08, 0xfe, 0x4e, - 0x82, 0x77, 0x56, 0x83, 0x9c, 0xb3, 0xf8, 0x52, 0x0a, 0x11, 0x88, 0x9c, 0x3a, 0x5f, 0x0f, 0xa5, - 0x0e, 0xda, 0x0b, 0x85, 0xd8, 0x5f, 0xe5, 0xb9, 0xcf, 0x38, 0xf0, 0x24, 0x44, 0x35, 0x0b, 0x7a, - 0xfb, 0x45, 0xcf, 0x20, 0x52, 0xd8, 0x3e, 0x87, 0x48, 0x79, 0xe0, 0x54, 0x90, 0x72, 0x36, 0x7a, - 0x90, 0x70, 0x53, 0x62, 0x06, 0xcb, 0x4d, 0x5f, 0x0f, 0xa4, 0x73, 0x99, 0x45, 0x12, 0x9e, 0x81, - 0x15, 0xf5, 0x0b, 0x65, 0x81, 0xfa, 0xa4, 0x7f, 0x00, 0x31, 0x7d, 0x87, 0x26, 0x20, 0xea, 0x6d, - 0x07, 0x23, 0xd1, 0x09, 0x62, 0xbf, 0x4e, 0xc3, 0xbe, 0xa5, 0x5e, 0x96, 0x03, 0xa1, 0xc3, 0xc7, - 0x55, 0xfb, 0x75, 0xee, 0xd6, 0x69, 0x64, 0x43, 0x94, 0x13, 0xaf, 0x3d, 0xbb, 0xa0, 0x7b, 0x39, - 0x2e, 0xf4, 0x6b, 0x2c, 0xd3, 0xf2, 0x1b, 0x9c, 0x7b, 0x5f, 0x52, 0xf6, 0xe6, 0x2f, 0x2f, 0x6e, - 0x62, 0xf7, 0xa7, 0xd1, 0xe3, 0x8b, 0xe5, 0xcf, 0x77, 0x47, 0x15, 0x7c, 0x45, 0x53, 0x0d, 0x63, - 0x1b, 0x65, 0xbf, 0x12, 0x3c, 0x47, 0x29, 0x41, 0xb9, 0x4a, 0x23, 0xd6, 0xc6, 0xcb, 0x9b, 0x6c, - 0x58, 0x28, 0x44, 0x8a, 0xc3, 0x87, 0x61, 0x92, 0x3d, 0xbb, 0xee, 0x88, 0xc5, 0xf8, 0x66, 0xe1, - 0xb2, 0x14, 0xab, 0x4d, 0x29, 0x9e, 0x51, 0x26, 0x40, 0x2f, 0x02, 0x6a, 0xf5, 0x82, 0x59, 0x20, - 0x54, 0xeb, 0x77, 0xb6, 0x0f, 0xed, 0x38, 0x73, 0x5d, 0x90, 0x6d, 0x73, 0xe6, 0xad, 0x80, 0xc6, - 0xb0, 0x0d, 0x01, 0x5a, 0x30, 0xac, 0x1e, 0xda, 0xb4, 0xbc, 0xa5, 0x8c, 0x18, 0x05, 0xd8, 0x2d, - 0x2d, 0xf0, 0x51, 0x96, 0xb5, 0x5a, 0x32, 0x5a, 0x09, 0xfd, 0x7a, 0xa9, 0x45, 0x3f, 0x11, 0x14, - 0x12, 0xfa, 0x3b, 0xd1, 0xf5, 0x88, 0x9c, 0x2a, 0x31, 0x86, 0x44, 0x85, 0x4c, 0x92, 0xf8, 0x05, - 0x4a, 0x92, 0xc8, 0xcb, 0xcb, 0xd5, 0x32, 0x2a, 0x5f, 0x93, 0x4b, 0xd6, 0x75, 0xbe, 0xfa, 0x36, - 0x43, 0xe7, 0x86, 0x01, 0x2b, 0xda, 0x80, 0x6d, 0x5e, 0xfa, 0x32, 0x98, 0xe2, 0x55, 0x87, 0x4c, - 0x92, 0x79, 0x84, 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0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -22729,7 +22729,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_storage #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 368640, // uncompressed data size (bytes) - 362878, // compressed data size (bytes) + 362876, // compressed data size (bytes) kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c index 0e7bcf927..d262a5d91 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c @@ -34,1812 +34,1901 @@ // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 28813 +// DATA SIZE (bytes): 36864 +// COMPRESSED SIZE (bytes): 30240 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data[] = { - 0xed, 0xf7, 0x53, 0xb4, 0x6d, 0x4d, 0xd6, 0x2d, 0x8a, 0x4e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0x5c, 0xd3, 0xc6, 0x9a, 0xb6, 0x6d, 0xdb, 0xb6, 0x71, 0x32, 0xff, 0x2f, - 0xf7, 0xde, 0xe7, 0x9c, 0x72, 0xdf, 0xee, 0x7d, 0xbb, 0x59, 0x4b, 0x19, 0x51, 0x23, 0x1a, 0x23, - 0x5a, 0xeb, 0x3d, 0xc6, 0x18, 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0x0d, 0xfe, 0x5b, 0x07, 0x06, 0xff, 0x3f, 0xf5, 0xff, 0x1d, 0x2f, 0xe8, 0xff, + 0x1a, 0x4f, 0xf0, 0x3f, 0xe2, 0x06, 0xfa, 0x1f, 0x76, 0xfe, 0x1f, 0x04, 0x40, 0xa0, 0x9f, 0x9f, + 0x1f, 0x60, 0xa2, 0x9f, 0x7f, 0xf0, 0xff, 0x6f, 0xf3, 0x10, 0x20, 0x88, 0xff, 0x21, 0x02, 0x16, + 0x90, 0xa0, 0xff, 0x62, 0x00, 0xa8, 0xff, 0x92, 0x09, 0x0c, 0xd0, 0xfe, 0xd6, 0x5f, 0x03, 0xfe, + 0x66, 0x11, 0x80, 0xbf, 0x59, 0xe0, 0x1f, 0x26, 0xa9, 0xc0, 0xff, 0x2f, 0xa6, 0xf8, 0x87, 0x0b, + 0xfe, 0x41, 0xb3, 0x01, 0x16, 0x3b, 0x61, 0x1d, 0xd7, 0x26, 0x00, 0xe8, 0xdf, 0xe3, 0x40, 0xfe, + 0x61, 0x9a, 0xff, 0xee, 0xff, 0xe3, 0xcf, 0x01, 0xf5, 0x6f, 0x76, 0xf9, 0x87, 0x3d, 0xfe, 0xe1, + 0xff, 0x15, 0x98, 0xc8, 0xdf, 0xf5, 0x05, 0x01, 0xf8, 0x77, 0xfd, 0xfd, 0xbf, 0xad, 0x3f, 0xe1, + 0x9f, 0xdf, 0x5f, 0x70, 0xf8, 0x9f, 0xb5, 0xf4, 0x2f, 0xfe, 0xc5, 0xbf, 0xf8, 0x17, 0xff, 0xe2, + 0x5f, 0xfc, 0x8b, 0xff, 0x9b, 0xf0, 0x7f, 0x01, 0xae, 0xaa, 0xb4, 0x20, 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1849,8 +1938,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 32768, // uncompressed data size (bytes) - 28813, // compressed data size (bytes) + 36864, // uncompressed data size (bytes) + 30240, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1868,13 +1957,13 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 43 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x86, 0x08, 0x16, 0x20, 0x2e, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x95, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, - 0x88, 0x20, 0x00, 0x06, 0x3c, 0x73, 0x3c, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x06, 0x20, 0xe2, 0x00, 0xe2, 0x0e, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, + 0x03, 0x8a, 0x1d, 0x80, 0xd8, 0x03, 0x88, 0x35, 0x19, 0x18, 0x18, 0xb1, 0xa9, 0x9b, 0x00, 0x11, + 0x04, 0x00, 0x6d, 0xde, 0x74, 0xe4, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1885,7 +1974,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 43, // compressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1902,1812 +1991,1901 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt; // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 28812 +// DATA SIZE (bytes): 36864 +// COMPRESSED SIZE (bytes): 30239 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data[] = { - 0xed, 0xf7, 0x53, 0xb4, 0x70, 0xbb, 0xd6, 0x2d, 0x00, 0x2e, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0xfa, - 0x96, 0x6d, 0xdb, 0xb6, 0xf5, 0x2d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb5, 0xff, 0xbb, - 0xcf, 0xbd, 0xb7, 0xaa, 0x5a, 0xbd, 0x55, 0xbd, 0xd5, 0xe9, 0xad, 0xcd, 0xf4, 0x64, 0x64, 0x20, - 0xc9, 0x98, 0x99, 0x33, 0x39, 0xbb, 0xb1, 0xa3, 0x4f, 0xe1, 0xbe, 0xb7, 0x03, 0x83, 0x3f, 0x00, - 0x6d, 0x76, 0x68, 0xf1, 0xbb, 0x1c, 0x29, 0xe2, 0xc3, 0x74, 0x08, 0xde, 0xdc, 0xef, 0xd7, 0x9d, - 0x4a, 0x30, 0x2f, 0xb0, 0xed, 0x62, 0x38, 0x6a, 0x92, 0x97, 0x56, 0x34, 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0xfe, 0x87, 0x08, 0x58, 0x40, + 0x02, 0xff, 0x8b, 0x01, 0xa0, 0xfe, 0x4b, 0x26, 0x30, 0x40, 0xfb, 0x5b, 0x7f, 0xf5, 0xff, 0x9b, + 0x45, 0x00, 0xfe, 0x66, 0x81, 0x7f, 0x98, 0xa4, 0x1c, 0xff, 0xbf, 0x98, 0xe2, 0x1f, 0xce, 0xff, + 0x07, 0x4d, 0x06, 0x58, 0xec, 0x84, 0xb5, 0x5c, 0x5b, 0x00, 0xa0, 0x7f, 0xcf, 0x03, 0xf9, 0x87, + 0x69, 0xfe, 0xdb, 0xfe, 0x27, 0x9f, 0x3d, 0xea, 0xdf, 0xec, 0xfc, 0x0f, 0xbb, 0xff, 0xc3, 0xff, + 0xab, 0x30, 0x91, 0xbf, 0xfb, 0x0b, 0x02, 0xf0, 0xef, 0xfe, 0xfb, 0x7f, 0x5b, 0x7f, 0xfc, 0x3f, + 0xbf, 0xbf, 0x60, 0xff, 0x3f, 0x7b, 0xe9, 0x5f, 0xfc, 0x8b, 0x7f, 0xf1, 0x2f, 0xfe, 0xc5, 0xbf, + 0xf8, 0x17, 0xff, 0x37, 0xe1, 0xff, 0x02, 0x26, 0x6a, 0xed, 0xd5, 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3717,8 +3895,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 32768, // uncompressed data size (bytes) - 28812, // compressed data size (bytes) + 36864, // uncompressed data size (bytes) + 30239, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3736,13 +3914,13 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 43 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x86, 0x08, 0x16, 0x20, 0x2e, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x95, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, - 0x88, 0x20, 0x00, 0x06, 0x3c, 0x73, 0x3c, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x06, 0x20, 0xe2, 0x00, 0xe2, 0x0e, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, + 0x03, 0x8a, 0x1d, 0x80, 0xd8, 0x03, 0x88, 0x35, 0x19, 0x18, 0x18, 0xb1, 0xa9, 0x9b, 0x00, 0x11, + 0x04, 0x00, 0x6d, 0xde, 0x74, 0xe4, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3753,7 +3931,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 43, // compressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c index 1dc435371..51650a4dc 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c @@ -34,1043 +34,1132 @@ // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20480 -// COMPRESSED SIZE (bytes): 16512 +// DATA SIZE (bytes): 24576 +// COMPRESSED SIZE (bytes): 17932 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data[] = { - 0xed, 0xb7, 0x53, 0x94, 0x6d, 0x49, 0xbb, 0x05, 0x98, 0xb6, 0x6d, 0xdb, 0xb6, 0x9d, 0x79, 0xd2, - 0xb6, 0x4f, 0xda, 0xb6, 0x6d, 0xdb, 0xb6, 0x8d, 0x93, 0xb6, 0x6d, 0xdb, 0xb6, 0xba, 0xfe, 0x5b, - 0x75, 0xef, 0xed, 0xee, 0xd1, 0x6f, 0xdd, 0x6f, 0x5d, 0x73, 0x8c, 0x1d, 0x33, 0xe2, 0xd3, 0x8c, - 0x88, 0x6f, 0xaf, 0xb5, 0xc7, 0xce, 0x73, 0x70, 0xfb, 0x49, 0x23, 0x37, 0x85, 0x64, 0x9e, 0x0a, - 0x10, 0x55, 0xf4, 0x02, 0xbf, 0x24, 0x80, 0x18, 0xc2, 0x01, 0xa1, 0x1d, 0x7a, 0x3c, 0x8f, 0x02, - 0xf5, 0x10, 0xf6, 0x11, 0x01, 0xe0, 0x93, 0xd6, 0xd2, 0x4c, 0xf0, 0xdf, 0xc4, 0x10, 0x48, 0xec, - 0x45, 0x2a, 0xd3, 0xa0, 0xbc, 0xb0, 0x88, 0x63, 0x91, 0x5d, 0x89, 0x36, 0x08, 0x0a, 0xac, 0xe2, - 0x23, 0x5f, 0x61, 0x9a, 0x11, 0xea, 0x10, 0xa5, 0xe0, 0x4e, 0x7f, 0x7a, 0x46, 0x40, 0x0a, 0x9f, - 0x64, 0x91, 0x37, 0xb9, 0x91, 0x4e, 0xd2, 0xdd, 0x3c, 0xca, 0x2f, 0x4e, 0x01, 0x88, 0x7a, 0x1b, - 0x9a, 0x05, 0x7e, 0x0d, 0xa2, 0xb1, 0xdb, 0x4a, 0xc0, 0x63, 0xf4, 0x16, 0xae, 0xed, 0x97, 0x24, - 0x91, 0x01, 0xb2, 0x31, 0x59, 0xbe, 0xb7, 0x28, 0xd4, 0x3a, 0x74, 0xbd, 0x07, 0x95, 0x79, 0x91, - 0x86, 0x48, 0x85, 0x23, 0x34, 0x80, 0x43, 0xf5, 0x2d, 0x4f, 0x0a, 0xfe, 0x83, 0x60, 0x6e, 0x3c, - 0xed, 0x10, 0xc9, 0xf6, 0x91, 0x10, 0xec, 0x5f, 0x09, 0xe1, 0xf0, 0x24, 0x9c, 0xa7, 0x07, 0x89, - 0x14, 0x98, 0x6a, 0x64, 0xa1, 0x0f, 0xbc, 0x7f, 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defined(BINDATA_INCLUDE_DATA) @@ -1080,8 +1169,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20480, // uncompressed data size (bytes) - 16512, // compressed data size (bytes) + 24576, // uncompressed data size (bytes) + 17932, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1103,9 +1192,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x00, 0x02, 0x07, 0x06, 0x86, 0x08, 0x16, 0x20, 0x76, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0xaa, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x05, 0x40, - 0x04, 0x01, 0xce, 0xa8, 0x04, 0xe4, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x00, 0x06, 0x86, 0x06, 0x0e, 0x20, 0x8e, 0x60, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0x9a, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x25, 0x40, + 0x04, 0x01, 0xd4, 0x4b, 0xa9, 0xea, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1133,1044 +1222,1132 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_storage_pvt; // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20480 -// COMPRESSED SIZE (bytes): 16514 +// DATA SIZE (bytes): 24576 +// COMPRESSED SIZE (bytes): 17934 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data[] = { - 0xed, 0xb7, 0x53, 0x94, 0x65, 0x4b, 0xbb, 0x05, 0xb8, 0xd3, 0xae, 0xb4, 0x6d, 0xdb, 0x36, 0x2a, - 0x6d, 0xdb, 0x36, 0x2a, 0x6d, 0xdb, 0x99, 0x95, 0xb6, 0x6d, 0xdb, 0xb6, 0x2b, 0x6d, 0xdb, 0x99, - 0x7d, 0xfe, 0x7b, 0xce, 0xbd, 0xb7, 0xbb, 0x47, 0xbf, 0x75, 0xbf, 0xf5, 0x99, 0x63, 0xec, 0x98, - 0x11, 0x9f, 0x66, 0x44, 0x7c, 0x6b, 0xad, 0x31, 0x76, 0x27, 0xcc, 0x52, 0x7e, 0x83, 0x7f, 0xb7, - 0x62, 0x86, 0x74, 0xca, 0x11, 0xe2, 0xa0, 0x54, 0x69, 0xbb, 0xbb, 0x25, 0x3b, 0x72, 0xe9, 0x98, - 0x9b, 0xf5, 0x20, 0x92, 0x7c, 0x55, 0xa6, 0xd4, 0xfa, 0xc6, 0x68, 0xd3, 0xb8, 0x4f, 0x4c, 0x92, - 0xb1, 0xb7, 0x65, 0xd9, 0xbe, 0x5e, 0x71, 0xcc, 0x15, 0x39, 0xf4, 0x85, 0x9b, 0x9a, 0xe0, 0xa0, - 0x57, 0x63, 0x8d, 0xe3, 0xef, 0xd0, 0x45, 0x9f, 0xc5, 0x4d, 0xea, 0xc8, 0xc8, 0xf6, 0x25, 0xc2, - 0xd8, 0x18, 0xa7, 0xe5, 0x9a, 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0x95, 0x12, 0xfe, 0x8b, 0xa9, 0xfe, 0x70, + 0xee, 0x1f, 0xd4, 0x19, 0xe2, 0x70, 0x12, 0x57, 0xf1, 0xac, 0x01, 0x20, 0x7e, 0xcf, 0x03, 0xff, + 0xc3, 0x74, 0xff, 0xb6, 0xff, 0xe4, 0xb3, 0x47, 0xff, 0xcd, 0xce, 0x7f, 0xd8, 0xfd, 0x0f, 0xff, + 0x57, 0x61, 0x68, 0xbf, 0xfb, 0x0b, 0x1a, 0xe4, 0x77, 0xff, 0xfd, 0xdf, 0xd6, 0x6f, 0xf8, 0xe7, + 0xf7, 0x17, 0xec, 0xff, 0xb3, 0x97, 0xfe, 0xc1, 0x3f, 0xf8, 0x07, 0xff, 0xe0, 0x1f, 0xfc, 0x83, + 0x7f, 0xf0, 0xbf, 0x09, 0xff, 0x0b, 0x48, 0xe1, 0x8a, 0xe3, 0x00, 0x60, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2180,8 +2357,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20480, // uncompressed data size (bytes) - 16514, // compressed data size (bytes) + 24576, // uncompressed data size (bytes) + 17934, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2203,9 +2380,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x00, 0x02, 0x07, 0x06, 0x86, 0x08, 0x16, 0x20, 0x76, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0xaa, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x05, 0x40, - 0x04, 0x01, 0xce, 0xa8, 0x04, 0xe4, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x00, 0x06, 0x86, 0x06, 0x0e, 0x20, 0x8e, 0x60, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0x9a, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x25, 0x40, + 0x04, 0x01, 0xd4, 0x4b, 0xa9, 0xea, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c index d0f3acf2a..2aac589d6 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c @@ -35,10326 +35,10326 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 167936 -// COMPRESSED SIZE (bytes): 165043 +// COMPRESSED SIZE (bytes): 165046 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data[] = { - 0xec, 0x97, 0x43, 0x92, 0x28, 0x0a, 0x80, 0x20, 0xcb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xae, 0x57, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf3, 0xe7, 0x02, 0xb3, 0x9a, 0x88, - 0xde, 0x74, 0x5e, 0x21, 0x37, 0x99, 0x00, 0x00, 0xff, 0xcb, 0xff, 0x24, 0x95, 0x66, 0x31, 0x4c, - 0x51, 0xd0, 0xde, 0x80, 0x97, 0xf3, 0x74, 0x1b, 0xd8, 0x1f, 0x8c, 0xe5, 0xe7, 0xc7, 0x01, 0xbd, - 0x17, 0x42, 0x82, 0x40, 0xa8, 0x01, 0xb0, 0x39, 0x1c, 0x91, 0xe9, 0x8b, 0xe9, 0x68, 0xb3, 0x5e, - 0x24, 0x34, 0x4a, 0xea, 0x5e, 0x6b, 0x6d, 0xa6, 0x4f, 0xc9, 0x66, 0x3a, 0xfc, 0xf2, 0xb6, 0xda, - 0x14, 0x49, 0xdc, 0x05, 0xa0, 0x89, 0x38, 0x61, 0x5a, 0xc8, 0xbb, 0xa6, 0x93, 0xbc, 0x46, 0x72, - 0x3c, 0x2a, 0xe4, 0x73, 0xfb, 0xc1, 0x94, 0x21, 0x8a, 0xe1, 0x4a, 0x95, 0xa3, 0xbc, 0x73, 0x0b, - 0x52, 0xc9, 0x23, 0x8e, 0xe1, 0xb4, 0xb7, 0x20, 0x31, 0x2a, 0x3e, 0x97, 0xad, 0x33, 0x92, 0x13, - 0x26, 0x3b, 0x69, 0xbe, 0xec, 0xde, 0xe4, 0xb9, 0xd1, 0x98, 0x1e, 0x32, 0xf1, 0x8a, 0xc1, 0xc4, - 0x22, 0x2b, 0x2d, 0xf7, 0x4d, 0xf3, 0x30, 0x76, 0x29, 0xaf, 0xfe, 0x1d, 0xde, 0xf1, 0xcc, 0x74, - 0xc0, 0xbb, 0x1d, 0x89, 0x83, 0x32, 0xb4, 0x8a, 0xe9, 0x14, 0xf7, 0x8a, 0xe3, 0xf4, 0xd2, 0x80, - 0xda, 0x6b, 0xc5, 0x90, 0xc6, 0xe2, 0x35, 0x3c, 0xcb, 0x60, 0xc6, 0x32, 0xab, 0xee, 0x58, 0x3d, - 0xc3, 0xbf, 0x6f, 0xe1, 0x43, 0x01, 0xd3, 0x90, 0x4b, 0x68, 0xd7, 0x5a, 0xd6, 0x1b, 0x5f, 0x47, - 0xae, 0x66, 0x3d, 0x63, 0x1a, 0x1f, 0xa7, 0xf0, 0x26, 0x71, 0x73, 0xd7, 0x4e, 0xab, 0xd8, 0x78, - 0x48, 0x18, 0xbf, 0x49, 0x20, 0x31, 0xef, 0xaa, 0x6e, 0x6b, 0xaa, 0x04, 0x63, 0x81, 0xbf, 0x21, - 0xe6, 0x99, 0xaf, 0x12, 0x51, 0x06, 0x6c, 0x58, 0xc2, 0x73, 0x16, 0x49, 0xac, 0x8c, 0x4a, 0x78, - 0xf4, 0x7a, 0xad, 0x38, 0x73, 0x54, 0x56, 0x6b, 0x3a, 0x0e, 0x32, 0xdd, 0x72, 0x01, 0xaf, 0xbe, - 0x86, 0x77, 0xec, 0xc1, 0x79, 0xca, 0xf4, 0xcd, 0x01, 0xe0, 0x13, 0xa4, 0xf5, 0xb9, 0x69, 0x04, - 0x94, 0x68, 0x88, 0x9f, 0x1a, 0xb1, 0xb4, 0x55, 0x4e, 0x3d, 0x10, 0xc4, 0x8f, 0xa4, 0xd8, 0xac, - 0x09, 0x0c, 0x98, 0x26, 0x8c, 0x54, 0x8c, 0x78, 0xa7, 0xc0, 0xbe, 0x5e, 0xde, 0x74, 0x9a, 0xd8, - 0x7a, 0x7a, 0xef, 0xfd, 0xda, 0xf9, 0x84, 0xdf, 0x23, 0xef, 0xda, 0xa9, 0x25, 0x72, 0x82, 0xe1, - 0xdd, 0xb4, 0x66, 0x36, 0xa7, 0x75, 0xc4, 0x59, 0x26, 0xe2, 0xc2, 0x36, 0xfb, 0xfe, 0xba, 0x51, - 0x5a, 0xfd, 0x07, 0x85, 0x4e, 0xad, 0xee, 0xcf, 0x7a, 0x44, 0x15, 0x0d, 0xd5, 0x1c, 0xb6, 0x87, - 0xa6, 0x33, 0x14, 0xd5, 0xe5, 0x14, 0x08, 0xfb, 0x7b, 0x45, 0x50, 0x2d, 0x0d, 0x2e, 0xd0, 0x51, - 0xe2, 0xcd, 0x3f, 0xb4, 0x22, 0xbb, 0x99, 0x8d, 0x48, 0x36, 0x97, 0xab, 0x31, 0xa3, 0x1e, 0x0b, - 0xde, 0xeb, 0xdf, 0xdd, 0x82, 0x5b, 0x58, 0x3d, 0xe7, 0x83, 0xfa, 0x20, 0x42, 0xff, 0xd7, 0xc1, - 0xff, 0xc3, 0x4f, 0x33, 0xb1, 0x59, 0x09, 0xb6, 0x6e, 0xea, 0x2c, 0x68, 0xc6, 0xe6, 0xaa, 0x6f, - 0xe0, 0xb2, 0xdf, 0xff, 0x6f, 0xff, 0xc3, 0x17, 0xd4, 0xf4, 0x3e, 0x46, 0x2f, 0x36, 0xc8, 0x6a, - 0xbe, 0x6d, 0x48, 0xaa, 0x80, 0xc5, 0x3c, 0xa2, 0x75, 0x63, 0x6d, 0x2c, 0x75, 0x3b, 0x77, 0x8c, - 0x02, 0x9a, 0x4c, 0x87, 0x5f, 0xf8, 0x42, 0xf6, 0xa8, 0xf0, 0x39, 0x28, 0xb4, 0x69, 0x36, 0xba, - 0xf7, 0x50, 0xde, 0xa4, 0x65, 0x79, 0x51, 0x75, 0x25, 0x44, 0x44, 0xc8, 0x8f, 0x31, 0xa5, 0x44, - 0x52, 0x34, 0x28, 0x74, 0x67, 0xd6, 0x18, 0x67, 0x12, 0x63, 0xaf, 0x5d, 0xde, 0x9d, 0x16, 0x84, - 0x07, 0x6c, 0xae, 0xb8, 0xcc, 0xc5, 0x86, 0x07, 0x86, 0x06, 0xc6, 0x81, 0xdb, 0x7c, 0x72, 0x4c, - 0x9e, 0x87, 0x95, 0xac, 0xe6, 0x90, 0xd8, 0x05, 0x38, 0x10, 0xde, 0xfb, 0xf2, 0x7a, 0x15, 0xa5, - 0x49, 0x29, 0x94, 0x98, 0xed, 0xb8, 0xfa, 0x96, 0x8d, 0x5a, 0x7c, 0x7c, 0xcc, 0xf9, 0xad, 0x15, - 0x63, 0x68, 0xb7, 0xe2, 0x5c, 0xbc, 0x09, 0x6b, 0x41, 0x67, 0xba, 0x8f, 0x87, 0xe4, 0x83, 0x4e, - 0x99, 0x0a, 0x05, 0x2c, 0xe7, 0xf9, 0x00, 0xe9, 0x1d, 0xb8, 0x5e, 0x1a, 0xc7, 0x34, 0xa9, 0x55, - 0xa4, 0x9b, 0x30, 0x04, 0x25, 0xca, 0xe2, 0x54, 0xcd, 0xb6, 0xda, 0xb3, 0xb5, 0x11, 0xfd, 0xed, - 0x18, 0x50, 0x31, 0x67, 0xb9, 0xfb, 0x83, 0x8e, 0xec, 0x52, 0xb3, 0x37, 0x3b, 0xba, 0xdf, 0x19, - 0xde, 0xf2, 0xe3, 0x0b, 0xc7, 0x18, 0xf0, 0x26, 0x2e, 0x47, 0x9f, 0x3e, 0xc3, 0x3c, 0x11, 0x01, - 0x12, 0x5a, 0x85, 0x29, 0x20, 0x08, 0x4c, 0x13, 0xbb, 0x9b, 0xc3, 0xa6, 0x27, 0x85, 0xb3, 0x36, - 0x98, 0x6c, 0x86, 0x7d, 0xe8, 0x2a, 0x5a, 0x05, 0xe1, 0x7e, 0x2c, 0x79, 0x2b, 0xcb, 0xf1, 0xcc, - 0xbc, 0xc4, 0xa8, 0xbd, 0x2e, 0x84, 0x50, 0xfe, 0x07, 0xcb, 0x65, 0xca, 0xa4, 0x1c, 0x46, 0xd7, - 0xa9, 0x31, 0x81, 0xb0, 0x25, 0x29, 0xb9, 0xa4, 0x92, 0x32, 0xd2, 0xda, 0xc8, 0xfa, 0x65, 0x71, - 0x7b, 0x8c, 0x18, 0x7d, 0xb2, 0xc8, 0x0a, 0x4b, 0x32, 0xf4, 0xf3, 0x20, 0x66, 0x59, 0xaa, 0x56, - 0xfb, 0x4a, 0x50, 0xd4, 0xb1, 0xde, 0xc0, 0x3a, 0x80, 0x11, 0xef, 0xd5, 0x2c, 0xd4, 0x7e, 0xbc, - 0x94, 0x87, 0x6f, 0x17, 0x64, 0xfc, 0x9c, 0xe2, 0xcb, 0x26, 0x9b, 0x16, 0xde, 0x70, 0xbc, 0x7a, - 0x54, 0x45, 0x6a, 0x8c, 0x6f, 0xff, 0x36, 0xd3, 0x70, 0x2f, 0x4a, 0xb9, 0x98, 0xea, 0x6f, 0x9e, - 0x05, 0x6c, 0x7e, 0xb4, 0x0a, 0x22, 0x03, 0x0a, 0x5d, 0x0c, 0x88, 0x68, 0x0b, 0x68, 0x19, 0xdf, - 0xa4, 0x63, 0x8e, 0x55, 0xb3, 0x9e, 0x9a, 0xd4, 0xb6, 0x55, 0xb6, 0x36, 0x30, 0xb0, 0x6a, 0x77, - 0x47, 0x78, 0x9e, 0xc1, 0x6d, 0xe8, 0x0e, 0x09, 0x0f, 0x3c, 0x86, 0x68, 0x84, 0xf8, 0x35, 0xcd, - 0x48, 0xd4, 0xc1, 0x9e, 0x72, 0x0a, 0xb8, 0x67, 0xc9, 0x48, 0x5f, 0x1f, 0x49, 0x6a, 0x61, 0xbc, - 0x0c, 0xaa, 0x50, 0x1a, 0xa2, 0xd3, 0x63, 0x16, 0x47, 0x71, 0xbd, 0x36, 0xc2, 0x8b, 0xf3, 0x88, - 0x4f, 0x33, 0x10, 0x07, 0x23, 0x81, 0xaa, 0xb8, 0x3c, 0xeb, 0x63, 0x55, 0x0c, 0x94, 0x1c, 0x0c, - 0xbb, 0x14, 0x76, 0x53, 0xb8, 0xea, 0x0f, 0x1c, 0x56, 0xf8, 0x2c, 0x9f, 0xaa, 0xe4, 0x94, 0x64, - 0xd6, 0x4a, 0x10, 0x31, 0x3c, 0x67, 0xaf, 0x43, 0xe0, 0x63, 0x3a, 0x80, 0x9e, 0xa6, 0xa8, 0x62, - 0x4b, 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0x92, 0xe1, 0x28, 0xe0, 0x4d, 0x90, 0xab, 0x88, 0xad, + 0xd8, 0x43, 0x6e, 0xe2, 0x6b, 0x6a, 0xa8, 0xb9, 0x05, 0x52, 0xbc, 0x6e, 0x72, 0xe3, 0x63, 0xe6, + 0x05, 0xdd, 0x4c, 0xd3, 0x60, 0xc3, 0x64, 0xf3, 0x68, 0xe9, 0xf1, 0x9d, 0xa8, 0x4c, 0x13, 0x95, + 0x2f, 0x02, 0xbc, 0x7a, 0x12, 0xac, 0x6e, 0x10, 0x0c, 0x7f, 0xd1, 0x44, 0xce, 0x70, 0x0a, 0xe3, + 0x01, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0xff, 0x2b, 0xff, 0x01, 0xf3, 0x9d, + 0x26, 0x24, 0x00, 0x90, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10365,7 +10365,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 167936, // uncompressed data size (bytes) - 165043, // compressed data size (bytes) + 165046, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -10417,10349 +10417,10349 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 167936 -// COMPRESSED SIZE (bytes): 165420 +// COMPRESSED SIZE (bytes): 165419 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data[] = { - 0x9c, 0x97, 0xc3, 0x96, 0x28, 0x0a, 0x94, 0x43, 0xcb, 0xb6, 0x6d, 0xbb, 0xea, 0x96, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xd9, 0xef, 0x07, 0xba, 0x07, 0x9d, - 0x71, 0x06, 0x19, 0x9c, 0x75, 0xb2, 0xd3, 0xd7, 0x4e, 0xb9, 0xce, 0x91, 0x26, 0x64, 0x7a, 0x1d, - 0xca, 0xed, 0xf2, 0x82, 0x93, 0x00, 0x9a, 0xf9, 0xe0, 0xd0, 0x66, 0xd4, 0x58, 0x33, 0x8b, 0x2a, - 0x88, 0xdf, 0x4e, 0x76, 0x85, 0xef, 0x45, 0x85, 0x87, 0xff, 0x40, 0x1f, 0xa6, 0xd9, 0x71, 0xef, - 0x9d, 0x11, 0x86, 0x87, 0x84, 0x5f, 0x42, 0x97, 0x22, 0x20, 0x0a, 0x99, 0x73, 0x85, 0xee, 0xcd, - 0x59, 0x01, 0xa4, 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0xa6, 0xff, + 0x95, 0xff, 0x00, 0x8c, 0xac, 0x41, 0x6d, 0x00, 0x90, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -20770,7 +20770,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 167936, // uncompressed data size (bytes) - 165420, // compressed data size (bytes) + 165419, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c index 4bd57bfeb..ddd5a755d 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c @@ -35,10398 +35,10398 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 166216 -// COMPRESSED SIZE (bytes): 166202 +// COMPRESSED SIZE (bytes): 166207 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_data[] = { - 0x8c, 0x98, 0x43, 0x96, 0x28, 0x80, 0x82, 0x43, 0xcb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x78, 0xa5, 0xfe, 0x8d, 0x05, 0x74, 0x26, 0xc9, - 0x0a, 0x72, 0x72, 0x03, 0x0c, 0x22, 0x01, 0x00, 0x10, 0x09, 0x04, 0xf0, 0x3f, 0xda, 0x04, 0xfc, - 0x5f, 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0xd2, 0x7b, 0x28, 0x26, 0x70, 0x36, 0x87, 0xe8, 0x8a, 0x6a, + 0x70, 0xc3, 0x03, 0xb2, 0x8a, 0xe8, 0x07, 0xc4, 0xc7, 0x17, 0x59, 0x95, 0x65, 0x3d, 0xad, 0xf9, + 0x59, 0xb5, 0xbb, 0xaa, 0x1b, 0x44, 0xcb, 0x47, 0xc1, 0x95, 0xdd, 0xa0, 0x35, 0xa1, 0xc7, 0x54, + 0xb4, 0x16, 0xfb, 0xae, 0xc7, 0xc3, 0xb8, 0xea, 0x46, 0xd9, 0x34, 0xf7, 0xce, 0x52, 0xd7, 0xee, + 0xdd, 0x16, 0x8a, 0xe2, 0x15, 0x8f, 0x4b, 0x51, 0x1f, 0xd9, 0x56, 0xe4, 0xf5, 0x35, 0x10, 0x01, + 0x5b, 0x30, 0xf8, 0x87, 0x65, 0x34, 0xb7, 0xe2, 0x8f, 0x13, 0xa9, 0xfe, 0x55, 0xc0, 0xaf, 0xd5, + 0x33, 0xd3, 0xe7, 0x9b, 0x6c, 0x4e, 0xc6, 0x06, 0x1f, 0xd8, 0xa9, 0x54, 0xc7, 0x78, 0x02, 0x31, + 0x67, 0x4f, 0xfd, 0xb0, 0xbd, 0xd5, 0x90, 0x08, 0xba, 0x47, 0x7e, 0x42, 0x59, 0xf7, 0x71, 0x07, + 0x2c, 0x3e, 0x15, 0xf3, 0xdb, 0x6a, 0x23, 0xc8, 0x92, 0x01, 0xdd, 0x31, 0x31, 0xd7, 0x09, 0x14, + 0x9a, 0xf7, 0x3b, 0xa4, 0x09, 0xfd, 0xb5, 0x34, 0xb3, 0xcb, 0x81, 0x55, 0x43, 0x33, 0x95, 0x5b, + 0x4f, 0x5f, 0x43, 0x76, 0x0a, 0xef, 0x19, 0xd7, 0x6e, 0xf6, 0x79, 0x2c, 0x55, 0xf8, 0x49, 0x4f, + 0x17, 0x2c, 0x31, 0x07, 0xea, 0x6d, 0x40, 0x7f, 0x0b, 0x95, 0x3e, 0x3b, 0x88, 0x0d, 0x8b, 0x98, + 0xa3, 0x24, 0x4f, 0xbc, 0xbe, 0xbe, 0xa3, 0x99, 0x3a, 0x03, 0xe4, 0xc4, 0xcd, 0x19, 0x4a, 0xcf, + 0xd4, 0xfd, 0x76, 0x51, 0xf5, 0x2b, 0x53, 0x3c, 0x7f, 0x98, 0x1d, 0x0c, 0x94, 0xe2, 0x56, 0xdc, + 0xea, 0xf7, 0x81, 0x0a, 0x78, 0xa4, 0x5d, 0xd5, 0x2e, 0x5f, 0x57, 0x38, 0x50, 0xe9, 0xcd, 0x61, + 0x78, 0x19, 0x51, 0xe8, 0x8e, 0x0c, 0xb0, 0x23, 0x0d, 0xd1, 0xc9, 0x05, 0x57, 0x48, 0xfb, 0xe0, + 0x95, 0x4e, 0x07, 0x93, 0xc4, 0x7d, 0x6d, 0xa2, 0x07, 0x52, 0x3a, 0x01, 0xbb, 0x3d, 0x03, 0x51, + 0xc8, 0xb3, 0xda, 0xb4, 0x63, 0xc6, 0x47, 0xde, 0x7b, 0xd0, 0x56, 0xf7, 0x62, 0x27, 0x30, 0x03, + 0x01, 0x96, 0xc1, 0x7a, 0x5e, 0xee, 0x5d, 0xdb, 0x53, 0xe7, 0x5b, 0x0d, 0x1d, 0xb3, 0x23, 0x25, + 0xba, 0x59, 0x62, 0x9d, 0xaa, 0xbd, 0x5a, 0xec, 0x05, 0x16, 0x6e, 0x88, 0x66, 0xa1, 0x9d, 0x86, + 0x95, 0xf4, 0x2d, 0xbb, 0x47, 0xff, 0x02, 0x72, 0xe5, 0x70, 0x31, 0x48, 0x89, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10437,7 +10437,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_stor #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 166216, // uncompressed data size (bytes) - 166202, // compressed data size (bytes) + 166207, // compressed data size (bytes) kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -10459,10 +10459,10 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_stor // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x33, 0x70, 0xb6, 0xfa, 0x32, 0x9f, 0xb8, 0xe3, 0x6a, 0xaa, 0x2b, - 0x47, 0xd3, 0x31, 0x28, 0x07, 0x21, 0x15, 0x0b, 0xf1, 0x56, 0x7b, 0x88, 0x0e, 0x57, 0xc2, 0x6f, - 0x9f, 0x60, 0x96, 0xfa, 0xba, 0xbb, 0xac, 0x60, 0x92, 0x2f, 0x8d, 0x0b, 0x57, 0xca, 0x68, 0x04, - 0x4f, 0xc4, 0xc6, 0xc4, 0x75, 0x19, 0x1b, 0xbf, 0x3f, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0xae, 0xe7, 0xc0, 0x57, 0x8a, 0xcd, 0xfc, 0xb4, 0x1a, 0xbb, 0xb1, + 0x08, 0x12, 0xbe, 0xda, 0x2f, 0xdc, 0xaa, 0x91, 0x61, 0xad, 0x9a, 0x1e, 0x7e, 0x3b, 0x5d, 0x28, + 0x75, 0x48, 0xfa, 0x3c, 0xc4, 0xf8, 0xd7, 0xed, 0xbd, 0xbd, 0x6a, 0x90, 0x12, 0x40, 0x48, 0x19, + 0x03, 0x7a, 0x08, 0x04, 0xee, 0xa9, 0x77, 0xa9, 0x7b, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10495,31 +10495,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_stora // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x30, 0xbd, 0x34, 0xb2, 0x70, 0x25, 0x20, 0x8c, 0x58, 0xb7, 0x65, - 0x4c, 0x15, 0x74, 0xdd, 0x18, 0xcf, 0xff, 0x7b, 0xa3, 0x90, 0x03, 0x08, 0x31, 0xf9, 0xba, 0x5b, - 0x23, 0x32, 0x5a, 0xb8, 0x01, 0xa2, 0x7a, 0x21, 0x8e, 0x2f, 0x2d, 0xba, 0x9e, 0xe8, 0xcb, 0x11, - 0xad, 0x05, 0xe3, 0x4d, 0xd3, 0xaf, 0xcb, 0xbc, 0xec, 0x1b, 0xf5, 0xc1, 0xa1, 0xab, 0x72, 0x3c, - 0xb8, 0x28, 0x5d, 0x76, 0x14, 0x80, 0x4d, 0x84, 0x02, 0x67, 0xc0, 0x31, 0x25, 0xa4, 0x67, 0x22, - 0xef, 0x86, 0x6e, 0x8a, 0x2b, 0x39, 0x3a, 0x8d, 0x01, 0xf6, 0x5c, 0x0c, 0xfb, 0xa8, 0x92, 0x8a, - 0x6e, 0x03, 0xcd, 0x50, 0xe9, 0x8d, 0x5f, 0xaa, 0xbd, 0x7a, 0x36, 0x1b, 0x9c, 0x53, 0x7c, 0x57, - 0x8c, 0xc2, 0xf7, 0xc5, 0x44, 0x3f, 0x59, 0xf4, 0xac, 0x97, 0xfa, 0x8b, 0x2b, 0x3d, 0xc1, 0x3c, - 0x30, 0x7d, 0xf9, 0x3d, 0xeb, 0xda, 0xb2, 0x29, 0x5b, 0xc9, 0x7c, 0xc7, 0x4e, 0x25, 0x9f, 0x19, - 0x2c, 0x82, 0x0f, 0xb2, 0x35, 0x7a, 0x7c, 0x2b, 0x20, 0x7d, 0x3a, 0x72, 0x95, 0x1d, 0xc4, 0xbd, - 0x41, 0x0c, 0x00, 0x25, 0x46, 0x9b, 0xa0, 0x3c, 0x07, 0x4d, 0xd2, 0x3c, 0x58, 0x2c, 0xd3, 0x48, - 0x2f, 0x5f, 0x44, 0x28, 0x13, 0x86, 0xff, 0xf1, 0xae, 0x7d, 0x6e, 0x51, 0x93, 0x50, 0xbc, 0xef, - 0xc9, 0xf5, 0xed, 0xd0, 0xc1, 0x6d, 0x05, 0x0a, 0xea, 0xca, 0x8e, 0x54, 0xf5, 0x08, 0xa4, 0x83, - 0x3a, 0xa6, 0xf7, 0x69, 0xc1, 0x09, 0x60, 0x28, 0xd3, 0x78, 0x99, 0xda, 0x9a, 0x00, 0x3c, 0x87, - 0xa1, 0x40, 0x38, 0xf3, 0xde, 0x67, 0x1e, 0xdb, 0x7b, 0x70, 0x4a, 0x7b, 0x22, 0xc2, 0x52, 0xba, - 0x90, 0x67, 0x57, 0xdd, 0x8d, 0x19, 0xd3, 0x91, 0x90, 0xf9, 0x3f, 0xf3, 0x4b, 0xff, 0xe7, 0x1c, - 0x7b, 0x32, 0x35, 0x6f, 0x1e, 0x77, 0x47, 0x3f, 0xb9, 0xcc, 0x22, 0x28, 0xaf, 0x6c, 0x46, 0x7c, - 0x3f, 0xc8, 0x26, 0x29, 0xab, 0x08, 0x0a, 0xf5, 0xac, 0xa9, 0x0b, 0xea, 0xcf, 0x07, 0xe5, 0xc2, - 0x4e, 0xe3, 0xc4, 0x51, 0xf4, 0x2f, 0x61, 0xa4, 0x4b, 0x37, 0x1b, 0x2d, 0x5d, 0x53, 0x6d, 0x75, - 0x7f, 0xbd, 0x3a, 0x90, 0xf2, 0x39, 0x7b, 0x20, 0x9d, 0x21, 0x8e, 0x02, 0xb6, 0x9b, 0x2e, 0xb1, - 0x72, 0xa3, 0x05, 0x05, 0x13, 0x98, 0x3b, 0x45, 0xac, 0x59, 0x64, 0xf0, 0xc0, 0xb8, 0xb5, 0x61, - 0xba, 0xcb, 0x35, 0x48, 0x58, 0x5f, 0x00, 0xff, 0xfd, 0x39, 0xb3, 0xae, 0xee, 0xd9, 0xe6, 0xbe, - 0xa6, 0x4b, 0xe3, 0xe7, 0x7f, 0x31, 0xf6, 0xc5, 0xbe, 0xfc, 0xe7, 0xb1, 0xa7, 0xc3, 0x1d, 0xbf, - 0x18, 0xd2, 0x19, 0xc4, 0xfd, 0xa0, 0x1e, 0xba, 0x9a, 0x60, 0xaa, 0x55, 0x4b, 0xc0, 0x78, 0x9d, - 0x36, 0x06, 0x09, 0xab, 0xcd, 0xbb, 0x92, 0xab, 0x37, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x1f, 0x98, 0x1e, 0x38, 0x2c, 0x3f, 0xc5, 0xb8, 0xa4, 0xfa, 0xb3, + 0x3f, 0xb0, 0x87, 0xfa, 0x37, 0x7d, 0x09, 0x01, 0xe7, 0xbf, 0x5b, 0xdd, 0x3a, 0x5c, 0xd2, 0x3b, + 0xe6, 0x7d, 0x1e, 0xcc, 0x4a, 0x1c, 0xda, 0x7a, 0xea, 0xc5, 0x07, 0x07, 0xce, 0xd8, 0xd4, 0x48, + 0x7b, 0x68, 0x77, 0xd9, 0xb0, 0xa6, 0xd3, 0xc0, 0xdf, 0xa3, 0x1d, 0xbd, 0x46, 0xa6, 0x79, 0xeb, + 0x82, 0x66, 0x8c, 0xbf, 0x02, 0xf5, 0xf7, 0x87, 0x02, 0x50, 0x65, 0xcc, 0x4e, 0x87, 0xbf, 0x75, + 0xdb, 0x9d, 0x4e, 0xaa, 0xe5, 0x88, 0x79, 0x07, 0x26, 0x44, 0x5c, 0xd6, 0x9c, 0x08, 0x08, 0x04, + 0xe6, 0x17, 0x7b, 0x09, 0xaf, 0x2e, 0xa3, 0x70, 0xcc, 0x68, 0x39, 0xdb, 0xf7, 0x2d, 0x4b, 0xc8, + 0x00, 0x83, 0x92, 0x6a, 0x64, 0xd4, 0xd7, 0xb4, 0x81, 0x4d, 0xfd, 0x62, 0xb8, 0xf4, 0xe2, 0x95, + 0x70, 0x38, 0x36, 0x7a, 0xef, 0xed, 0xc8, 0xb7, 0x8a, 0x50, 0x0e, 0x18, 0x51, 0x14, 0x1d, 0xe7, + 0x24, 0x4f, 0xfd, 0x91, 0x40, 0xbc, 0x83, 0xad, 0xf1, 0x36, 0xc4, 0x49, 0x1c, 0xac, 0xeb, 0x20, + 0x43, 0x4e, 0xfb, 0x1b, 0x47, 0xb8, 0xd4, 0xde, 0x2d, 0xe4, 0x6f, 0x0c, 0x84, 0xc0, 0x87, 0x5c, + 0x3f, 0xeb, 0x57, 0x4a, 0x27, 0x28, 0xf9, 0x45, 0xfa, 0x55, 0x08, 0x7b, 0x4e, 0xff, 0x26, 0x4a, + 0x43, 0x9c, 0x5f, 0xcd, 0x8f, 0x4c, 0x58, 0xcb, 0x40, 0x89, 0x24, 0xc9, 0x11, 0x02, 0x56, 0x59, + 0x63, 0x52, 0x59, 0xc1, 0x79, 0x04, 0x9b, 0xe0, 0xb0, 0x74, 0xce, 0x46, 0x90, 0xb4, 0xa4, 0x6f, + 0x1c, 0xdc, 0x72, 0xaa, 0xbb, 0x4c, 0x99, 0x8a, 0xf4, 0x9e, 0xbc, 0xb5, 0x44, 0x29, 0x9a, 0x42, + 0x04, 0xd1, 0xe8, 0x9c, 0x63, 0xc3, 0xb7, 0xc4, 0xe8, 0x12, 0x04, 0x24, 0xff, 0x78, 0x21, 0x56, + 0x8b, 0x9c, 0x58, 0x18, 0x69, 0x05, 0x02, 0x52, 0x84, 0x9a, 0x69, 0xf5, 0xcd, 0x67, 0xd9, 0xd4, + 0xf0, 0x38, 0x2d, 0xd1, 0xb6, 0x74, 0x13, 0x9a, 0x13, 0xa0, 0xdb, 0x91, 0xc8, 0x41, 0xe6, 0x3f, + 0x37, 0x92, 0x75, 0xcb, 0x6e, 0xac, 0x55, 0x33, 0x91, 0x69, 0xd6, 0x1f, 0x38, 0x43, 0xbc, 0x45, + 0x66, 0xcb, 0xc9, 0xc8, 0x4a, 0x23, 0x0b, 0x7a, 0x29, 0xc4, 0xec, 0x4f, 0x1c, 0xf4, 0x19, 0x05, + 0xa8, 0xed, 0x95, 0xc5, 0x07, 0xf7, 0x83, 0xd5, 0x97, 0x08, 0x78, 0x5b, 0x2e, 0x4f, 0xd5, 0x0d, + 0xeb, 0x61, 0x76, 0x0d, 0x42, 0x54, 0x34, 0xb1, 0x1c, 0x7d, 0x4c, 0x0d, 0xc9, 0x57, 0x31, 0x82, + 0x20, 0x93, 0x40, 0xff, 0xda, 0x5f, 0xa5, 0x7f, 0xc1, 0x1b, 0x5c, 0x09, 0x49, 0xc9, 0x27, 0x4e, + 0xef, 0x4e, 0x3f, 0x13, 0x57, 0xe5, 0xda, 0xe5, 0x57, 0x31, 0x28, 0x3c, 0x19, 0xd9, 0xfd, 0x0e, + 0x85, 0xfd, 0x8b, 0x72, 0x02, 0x56, 0x1d, 0xd5, 0x09, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c index 346f7e4b0..bb1ca307c 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c @@ -35,10326 +35,10326 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 165448 -// COMPRESSED SIZE (bytes): 165052 +// COMPRESSED SIZE (bytes): 165050 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data[] = { - 0x00, 0x3a, 0x80, 0xc5, 0x7f, 0x03, 0x04, 0x48, 0x00, 0x00, 0x86, 0x02, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xd5, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x04, 0x01, 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defined(BINDATA_INCLUDE_DATA) @@ -10365,7 +10365,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 165448, // uncompressed data size (bytes) - 165052, // compressed data size (bytes) + 165050, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -10387,10 +10387,10 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x60, 0xb9, 0x62, 0x09, 0xb1, 0xef, 0xf4, 0xee, 0xec, 0x2e, 0xf9, - 0x0a, 0x1f, 0xc1, 0x16, 0x10, 0xf2, 0x41, 0x06, 0xf5, 0x6b, 0xe5, 0x48, 0x15, 0x95, 0x62, 0xdf, - 0x64, 0x91, 0x61, 0x4e, 0x33, 0xb5, 0xf4, 0xe4, 0x61, 0xaf, 0xc2, 0x0a, 0xaf, 0x92, 0x6a, 0xe4, - 0x63, 0x20, 0x56, 0x12, 0x27, 0xc1, 0xe6, 0xe2, 0x0b, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0xd7, 0xba, 0xa1, 0x84, 0x33, 0xdc, 0x7f, 0x48, 0xd1, 0xd5, 0xab, + 0x38, 0x2c, 0x93, 0xf9, 0xb1, 0x82, 0x4c, 0xb3, 0x41, 0x52, 0xd9, 0xf9, 0xae, 0xdf, 0xf0, 0x57, + 0x00, 0xc5, 0x40, 0x8e, 0xcc, 0x5e, 0x9e, 0xbd, 0x82, 0xf1, 0xa9, 0x21, 0x3e, 0xfe, 0xb1, 0x26, + 0x34, 0x59, 0x9d, 0x5b, 0xd4, 0x11, 0xec, 0xd7, 0x20, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10423,31 +10423,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storag // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x2c, 0x92, 0xee, 0x99, 0x44, 0x6d, 0xc1, 0x10, 0xd4, 0x4c, 0xf7, - 0xfb, 0xe8, 0xa3, 0x56, 0x64, 0x13, 0x42, 0x3f, 0xac, 0xf7, 0x76, 0x80, 0x9d, 0x58, 0x01, 0x9b, - 0xfa, 0x5f, 0x2f, 0xf5, 0x9d, 0x6a, 0x98, 0xce, 0x9e, 0x71, 0x33, 0x0a, 0xe7, 0xea, 0x2c, 0x8f, - 0x34, 0x13, 0x72, 0x7f, 0xcf, 0x2b, 0xfc, 0x61, 0x8d, 0x02, 0xcd, 0x7a, 0xc7, 0x85, 0xd7, 0x05, - 0x48, 0x1f, 0x6b, 0xdf, 0x6a, 0xf5, 0x08, 0xe0, 0x8d, 0x08, 0xc4, 0xf3, 0x0b, 0x64, 0x9b, 0xc4, - 0x40, 0x7a, 0x54, 0x7b, 0xab, 0x81, 0x37, 0xba, 0x87, 0x8c, 0x2b, 0x52, 0x04, 0xcb, 0xe7, 0xd2, - 0x21, 0xe1, 0xa4, 0xbb, 0xb4, 0x77, 0x97, 0x45, 0x3c, 0x62, 0x05, 0xc9, 0x33, 0xe6, 0x7f, 0xeb, - 0xc6, 0x73, 0x8a, 0xa0, 0x8d, 0xe9, 0xc4, 0xd1, 0x7a, 0x9f, 0xcf, 0x8b, 0xc1, 0x8e, 0x38, 0xa0, - 0x08, 0x3c, 0xc6, 0x41, 0x0c, 0x25, 0x0e, 0xef, 0x48, 0xa4, 0x58, 0x36, 0x69, 0x93, 0x34, 0x0f, - 0x9a, 0x38, 0xe9, 0x67, 0xdf, 0x26, 0x99, 0x0d, 0x27, 0xcd, 0xed, 0x47, 0xc7, 0x77, 0x79, 0x34, - 0xd7, 0xc7, 0x48, 0x07, 0x49, 0xd8, 0x81, 0xbe, 0x6f, 0xf4, 0xbb, 0x7d, 0x51, 0xdc, 0xbb, 0x55, - 0x1b, 0xd8, 0x7f, 0x73, 0xc5, 0xb9, 0x5d, 0x4a, 0xbc, 0x0f, 0xd0, 0x0f, 0xf6, 0x90, 0xbb, 0xe2, - 0xa8, 0x91, 0x34, 0x97, 0xf5, 0xec, 0x9e, 0x26, 0xc1, 0xa3, 0x36, 0x64, 0xbc, 0x25, 0x1d, 0x0c, - 0xa5, 0xc5, 0x13, 0x8f, 0x7d, 0x81, 0x03, 0x1e, 0x97, 0x03, 0x42, 0x1f, 0xb3, 0x43, 0xa6, 0x32, - 0xeb, 0xd4, 0x93, 0xdb, 0xb6, 0x60, 0xa1, 0x54, 0xda, 0xd0, 0xae, 0x48, 0x22, 0xce, 0xb6, 0xd3, - 0x87, 0xd2, 0x42, 0x75, 0x03, 0x91, 0x56, 0xc7, 0xeb, 0x0c, 0x0f, 0xe0, 0x42, 0x5a, 0x02, 0xf5, - 0xf8, 0xd2, 0x4d, 0x4c, 0x45, 0x1f, 0x91, 0x8d, 0xdf, 0x19, 0xff, 0xb7, 0x91, 0xec, 0x26, 0xc1, - 0xa8, 0x29, 0xee, 0x05, 0xc6, 0x34, 0x10, 0xef, 0x78, 0x87, 0x8e, 0x4c, 0xff, 0x40, 0x16, 0x96, - 0xc9, 0x78, 0xf6, 0xc2, 0xef, 0x48, 0xd1, 0xc0, 0xe3, 0x5b, 0x2e, 0x3d, 0xc5, 0x3a, 0x41, 0xab, - 0xf4, 0x60, 0xf4, 0x9e, 0xa7, 0xa5, 0x08, 0xec, 0x61, 0xbf, 0x64, 0x57, 0xcd, 0x50, 0x97, 0x77, - 0x5a, 0xfc, 0xb6, 0xfe, 0x88, 0x80, 0x8c, 0xba, 0x31, 0x26, 0x72, 0x4c, 0x51, 0x7d, 0x84, 0xfb, - 0xba, 0x36, 0x34, 0x9d, 0x9e, 0xe0, 0x76, 0x01, 0xc6, 0x97, 0x96, 0x7f, 0x80, 0x42, 0xf8, 0x83, - 0xdc, 0xc8, 0xa5, 0x38, 0x67, 0x1a, 0xb1, 0x31, 0x1a, 0x96, 0xf9, 0x43, 0x74, 0x57, 0xfd, 0xa0, - 0x6a, 0x00, 0x70, 0x80, 0xef, 0x84, 0x89, 0x19, 0xaa, 0x20, 0xb1, 0x59, 0x3e, 0x23, 0xa2, 0x4b, - 0xee, 0xd4, 0x3e, 0xdb, 0x5c, 0xb0, 0x3c, 0x53, 0x46, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x36, 0x69, 0xeb, 0x95, 0x27, 0x1d, 0xbf, 0x32, 0x91, 0xcc, 0x32, + 0x4c, 0x0c, 0x47, 0x33, 0xc8, 0x12, 0xb5, 0xb7, 0x63, 0xec, 0x31, 0xeb, 0x6b, 0xd7, 0x59, 0xaf, + 0xd6, 0xac, 0xa2, 0x0e, 0xa8, 0x37, 0x86, 0xf1, 0xc7, 0xa5, 0x12, 0x7c, 0x29, 0x70, 0x18, 0xab, + 0xad, 0x00, 0x1d, 0x5c, 0x0a, 0x14, 0xba, 0x9f, 0xf1, 0x36, 0x6a, 0x3b, 0x0c, 0x12, 0xbb, 0x93, + 0xc1, 0xe8, 0x43, 0xd0, 0xeb, 0x2e, 0x1b, 0x5a, 0xff, 0x46, 0xfb, 0x4f, 0x76, 0xac, 0x99, 0xd1, + 0x2f, 0xef, 0x36, 0xb7, 0x72, 0x89, 0xb3, 0xba, 0x91, 0x6e, 0xc1, 0x79, 0xf7, 0x86, 0x69, 0x2e, + 0x31, 0x92, 0xc6, 0xc5, 0x3a, 0x2c, 0x1e, 0xa3, 0x30, 0xde, 0x94, 0xfc, 0xcb, 0xb1, 0x98, 0x62, + 0x6f, 0x63, 0x97, 0x45, 0xab, 0x27, 0x44, 0xcf, 0x9a, 0x4d, 0x86, 0x0c, 0xc8, 0x72, 0x5c, 0xbd, + 0xee, 0x9e, 0x5d, 0x3a, 0x49, 0x5a, 0xa3, 0x95, 0x1c, 0x53, 0xed, 0x94, 0x4f, 0x95, 0x76, 0x1c, + 0x2a, 0x74, 0xc0, 0x5a, 0x96, 0x0f, 0x51, 0x20, 0xb4, 0x64, 0x28, 0x1c, 0xe2, 0x23, 0x69, 0xcb, + 0x65, 0x7a, 0x94, 0xa7, 0x85, 0x9d, 0x79, 0x29, 0x07, 0x15, 0xda, 0xe1, 0xd5, 0x96, 0x22, 0x73, + 0x6b, 0xaa, 0x57, 0x4c, 0xe3, 0xdf, 0xdd, 0x6f, 0xec, 0x1b, 0x82, 0xdc, 0x28, 0x93, 0x6f, 0x25, + 0x17, 0x8a, 0x30, 0x7e, 0x60, 0x25, 0x77, 0x0f, 0x8b, 0x41, 0x61, 0xf5, 0xf4, 0x8b, 0x2a, 0x3d, + 0x54, 0x29, 0x69, 0x45, 0xb3, 0x35, 0x2d, 0x30, 0xee, 0xb0, 0xda, 0xcd, 0xd8, 0x45, 0x57, 0x8b, + 0xd6, 0xce, 0x10, 0xd9, 0x85, 0x6a, 0x2a, 0xa6, 0xb0, 0x71, 0x5a, 0xb9, 0x94, 0xb1, 0xf0, 0x1b, + 0x1c, 0xa2, 0x41, 0x8d, 0xf1, 0xc8, 0xbb, 0xe4, 0xa6, 0x82, 0xe4, 0x9d, 0xbd, 0xb5, 0x2a, 0xf1, + 0xfe, 0xaa, 0xf8, 0xf7, 0xd3, 0x51, 0x7b, 0x82, 0x21, 0x19, 0x4f, 0x41, 0x80, 0x46, 0x1c, 0x87, + 0xf7, 0x89, 0xb9, 0xae, 0x1a, 0xe0, 0x8e, 0xf8, 0x3e, 0xf4, 0x97, 0x24, 0x4c, 0x33, 0x03, 0x47, + 0x9e, 0xc5, 0x52, 0x8d, 0x33, 0x16, 0xd2, 0x91, 0xc2, 0x95, 0xdf, 0x25, 0x7c, 0x2f, 0x14, 0x64, + 0xd0, 0x3c, 0xfd, 0x7b, 0x4a, 0x49, 0x8c, 0xc8, 0x39, 0x11, 0xf4, 0xb7, 0x5e, 0x9b, 0xc5, 0xdf, + 0x3a, 0x82, 0x12, 0xe3, 0x3b, 0x24, 0x7b, 0xa9, 0x9a, 0x5a, 0xb5, 0xa9, 0x81, 0xa3, 0xb7, 0xac, + 0x06, 0x22, 0x70, 0xb4, 0x22, 0x8b, 0xef, 0xd9, 0x33, 0x79, 0xac, 0xa7, 0x34, 0xe2, 0xce, 0xaf, + 0x38, 0x78, 0x67, 0xcb, 0x52, 0xe4, 0x8e, 0xc4, 0x9f, 0x63, 0xdf, 0xbb, 0xe7, 0x3d, 0x86, 0x13, + 0x03, 0x12, 0x67, 0x3f, 0x74, 0x2b, 0x65, 0x87, 0x94, 0xa5, 0x7d, 0x1a, 0x55, 0xfe, 0x56, 0xdb, + 0x50, 0xf0, 0xf5, 0x57, 0xb5, 0x7f, 0x94, 0x58, 0xfc, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c index a0ec3651b..48c160790 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c @@ -35,10350 +35,10350 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 165448 -// COMPRESSED SIZE (bytes): 165428 +// COMPRESSED SIZE (bytes): 165430 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data[] = { - 0x8c, 0x99, 0x53, 0x96, 0x28, 0x0a, 0x80, 0x24, 0xcb, 0xb6, 0x6d, 0xdb, 0xbc, 0x65, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x5d, 0x35, 0x6f, 0x66, 0x7a, 0x01, 0x9d, - 0x3f, 0x99, 0x4b, 0x88, 0x38, 0x09, 0x0c, 0x22, 0x0e, 0x00, 0x10, 0x0a, 0x04, 0xf0, 0xff, 0xb2, - 0x02, 0xf8, 0xff, 0xbb, 0x0c, 0x00, 0x00, 0xe4, 0x7f, 0x26, 0x20, 0x05, 0xc0, 0xff, 0x2a, 0xd6, - 0x9d, 0xb7, 0xc0, 0x26, 0x95, 0x15, 0x1b, 0xfb, 0x24, 0x4d, 0x17, 0x5e, 0xd6, 0x39, 0x9c, 0x80, - 0x5e, 0xb5, 0x61, 0xf0, 0xef, 0x47, 0x48, 0xf5, 0x41, 0x9b, 0x63, 0xbe, 0xf5, 0x60, 0x11, 0xdf, - 0x71, 0x3b, 0x27, 0xdc, 0x21, 0x6a, 0x2d, 0x4a, 0x73, 0x97, 0x10, 0xda, 0x71, 0x07, 0x5b, 0x33, - 0xc2, 0x2a, 0x2d, 0xd1, 0x2b, 0xcc, 0x96, 0xb7, 0x7a, 0xf1, 0x3a, 0x7d, 0xfd, 0xcf, 0x03, 0xd5, - 0xfb, 0x1f, 0x2c, 0x0b, 0xd5, 0xfb, 0x31, 0x97, 0xd8, 0x32, 0xe7, 0x6f, 0xee, 0x0e, 0x13, 0x7f, - 0x15, 0x43, 0x4c, 0xdd, 0x49, 0x42, 0xa9, 0xf5, 0xa9, 0x3b, 0xf0, 0x96, 0xa3, 0xfd, 0x8b, 0xb9, - 0xe6, 0xe6, 0xe2, 0xb8, 0xe8, 0x80, 0xf6, 0x12, 0x3d, 0x7d, 0xc1, 0xad, 0x2a, 0x31, 0x87, 0x6a, - 0xb3, 0x2f, 0xc3, 0xa5, 0x6d, 0x77, 0x0f, 0x44, 0x2d, 0xe3, 0x3b, 0x26, 0x89, 0x9c, 0x05, 0x0c, - 0x73, 0xec, 0x83, 0x22, 0x44, 0x78, 0x5c, 0x59, 0xe8, 0xce, 0x45, 0x93, 0xc3, 0xc6, 0xf6, 0x52, - 0x1b, 0x4e, 0x6b, 0x79, 0xe9, 0x10, 0xd8, 0xc0, 0x9c, 0x39, 0x8c, 0x03, 0x42, 0x71, 0xfe, 0xe0, - 0xbe, 0x46, 0xe5, 0xe4, 0xd5, 0x44, 0x59, 0x74, 0xd5, 0xb0, 0x30, 0xe8, 0x2b, 0xea, 0x39, 0x00, - 0xf6, 0x08, 0xb9, 0xef, 0xac, 0xfb, 0x82, 0x08, 0xe5, 0x19, 0xea, 0x89, 0x07, 0x90, 0xd3, 0x85, - 0x88, 0x18, 0x52, 0x6c, 0x45, 0x97, 0x29, 0x7b, 0x4d, 0x0f, 0x0e, 0x6f, 0x35, 0x01, 0x7f, 0xc3, - 0xd2, 0x22, 0x91, 0xe3, 0x33, 0xfd, 0x0b, 0xa9, 0x30, 0x7f, 0x1f, 0x60, 0x1e, 0xab, 0xd8, 0x8f, - 0xd3, 0xe4, 0x51, 0xc3, 0xdf, 0xdc, 0xeb, 0xd8, 0x10, 0x39, 0xb1, 0x8f, 0x17, 0x62, 0x6c, 0x92, - 0x63, 0x41, 0xed, 0x0e, 0x8b, 0x67, 0x00, 0x0e, 0x3f, 0x0e, 0x00, 0xe6, 0x02, 0xb2, 0x96, 0x9f, - 0x62, 0x9d, 0x6d, 0xa9, 0xb1, 0xc0, 0x81, 0x52, 0x60, 0x14, 0x7c, 0x00, 0xa8, 0x0d, 0x1e, 0x06, - 0x8f, 0x17, 0x3b, 0x20, 0xcc, 0x85, 0x8f, 0x42, 0x0c, 0xec, 0x63, 0x59, 0x4f, 0xb1, 0xcc, 0xe3, - 0x6d, 0x34, 0xed, 0xb4, 0xf7, 0xc9, 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0xb4, 0x65, 0xc8, 0xa8, 0x0f, 0x30, 0xeb, 0xe6, 0x0b, 0x40, 0x4a, 0x74, 0x1b, + 0xc3, 0x50, 0x74, 0xb0, 0xa0, 0x30, 0xe5, 0x56, 0x74, 0x5a, 0x0e, 0xc2, 0x58, 0xd2, 0xb4, 0x62, + 0x75, 0x28, 0x21, 0x30, 0xc2, 0xac, 0x9f, 0x67, 0x53, 0x83, 0x2b, 0x28, 0xf9, 0xb6, 0x1d, 0x0d, + 0x16, 0x30, 0xca, 0xe6, 0x97, 0xc7, 0xf0, 0xae, 0x21, 0xe5, 0x6c, 0xb4, 0xb5, 0x32, 0x1a, 0xdb, + 0xcb, 0x1e, 0x46, 0x76, 0x23, 0x68, 0x41, 0xf3, 0xc7, 0x2c, 0xf7, 0x28, 0x5c, 0xf0, 0xe5, 0xd4, + 0x1c, 0xd2, 0x69, 0x59, 0xef, 0xa8, 0x86, 0x90, 0xd2, 0xfb, 0x22, 0xb7, 0x10, 0x81, 0xe2, 0x3d, + 0xe6, 0xda, 0x48, 0x86, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10389,7 +10389,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 165448, // uncompressed data size (bytes) - 165428, // compressed data size (bytes) + 165430, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -10411,10 +10411,10 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x80, 0x7e, 0xcb, 0x2f, 0x5b, 0x40, 0xe7, 0x0f, 0x5a, 0xc9, 0x1e, - 0x72, 0x3e, 0xa9, 0xbc, 0xb7, 0x12, 0x38, 0x94, 0x6e, 0xe4, 0x83, 0x87, 0x9f, 0xa2, 0x36, 0x4e, - 0x37, 0xd0, 0x5b, 0xdb, 0x48, 0x24, 0x75, 0x30, 0xf6, 0x38, 0xc5, 0xa1, 0x73, 0xf5, 0x52, 0xae, - 0xd5, 0x29, 0xe7, 0xb0, 0xce, 0xa7, 0x6b, 0x27, 0xe4, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0x1b, 0x8e, 0xbc, 0x84, 0x90, 0x7c, 0xbe, 0x47, 0x8a, 0xa5, 0xdf, + 0x16, 0x4e, 0xa6, 0x94, 0x0d, 0x2c, 0xf6, 0x4d, 0xab, 0x8b, 0x2b, 0x55, 0x74, 0x24, 0x03, 0xe1, + 0x8b, 0x39, 0xe7, 0xcd, 0x0d, 0x52, 0x3b, 0xd1, 0x10, 0x65, 0x54, 0xad, 0x87, 0xe9, 0x03, 0x6d, + 0x4a, 0xf9, 0x6d, 0x90, 0x75, 0x15, 0x1e, 0x7b, 0x3c, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10447,31 +10447,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x6a, 0xac, 0x8d, 0x4b, 0x4d, 0x33, 0x4e, 0x67, 0x18, 0x87, 0x74, - 0x52, 0xfe, 0x62, 0xa6, 0x16, 0x4d, 0x17, 0xf2, 0xbf, 0x4e, 0x4f, 0xdb, 0xec, 0x17, 0x18, 0x5e, - 0x20, 0xfb, 0xe2, 0x55, 0x55, 0x8f, 0xe5, 0x62, 0x70, 0x38, 0xfd, 0x8d, 0xbc, 0x18, 0x86, 0x86, - 0x21, 0x7e, 0x6e, 0xcf, 0x92, 0xc4, 0x69, 0x99, 0xda, 0x0b, 0x85, 0x3c, 0xf2, 0xaf, 0xca, 0xe5, - 0x86, 0x74, 0xb5, 0x2e, 0xe4, 0x3a, 0xe8, 0x68, 0x98, 0x04, 0x3f, 0x47, 0x57, 0x55, 0x88, 0xbc, - 0x6e, 0x3f, 0xda, 0x4d, 0x12, 0x05, 0x9c, 0x5f, 0x98, 0xde, 0x99, 0x87, 0xdd, 0x02, 0x49, 0x85, - 0xe6, 0x69, 0xf4, 0x4e, 0x7b, 0xaa, 0x44, 0x37, 0x9a, 0x18, 0xd2, 0x6c, 0xbe, 0xbe, 0x3d, 0xc3, - 0x4e, 0x5c, 0x33, 0x4d, 0x4e, 0xf6, 0x14, 0x1f, 0x0c, 0x2e, 0xbd, 0xb3, 0x69, 0x33, 0x8e, 0xb4, - 0x52, 0x7d, 0x10, 0x3b, 0x75, 0xf4, 0xaf, 0xc8, 0x0a, 0x19, 0x36, 0x31, 0xb9, 0xdc, 0xda, 0x98, - 0xa8, 0x88, 0xfc, 0x78, 0x13, 0xdf, 0xda, 0x2a, 0x7c, 0x84, 0xf2, 0xa6, 0xf9, 0xb1, 0x37, 0x61, - 0xa7, 0xc5, 0x80, 0x48, 0xc1, 0xfb, 0xff, 0x79, 0x7c, 0x2a, 0xeb, 0xcc, 0x6b, 0xba, 0x5b, 0xc4, - 0x27, 0x80, 0xe7, 0x90, 0x02, 0xba, 0x96, 0x69, 0x54, 0x3f, 0xfb, 0x39, 0xc8, 0x8b, 0x38, 0x4a, - 0x44, 0x9c, 0xfe, 0x70, 0xd8, 0xa0, 0xa8, 0xa1, 0xb4, 0x98, 0x28, 0x70, 0x75, 0x46, 0xae, 0xad, - 0x04, 0xc2, 0x47, 0x54, 0x39, 0x14, 0x44, 0xa5, 0x87, 0x5f, 0x3a, 0x6e, 0x8c, 0x0d, 0x2d, 0x2b, - 0xf2, 0x3d, 0x53, 0x4a, 0x38, 0xb8, 0xd2, 0x9f, 0x42, 0x52, 0xbe, 0x9a, 0x07, 0x79, 0x93, 0xfe, - 0xd3, 0x27, 0x4c, 0x2a, 0x4a, 0x46, 0xa3, 0xa8, 0x76, 0x66, 0x99, 0x94, 0x47, 0xdb, 0x5f, 0x0d, - 0xb0, 0x74, 0x67, 0x79, 0x08, 0xe3, 0x91, 0xf1, 0x68, 0x3c, 0x1e, 0x12, 0x35, 0x43, 0xbb, 0x02, - 0x9f, 0xe4, 0xbf, 0xbb, 0x0b, 0x22, 0x48, 0x06, 0xe6, 0xe9, 0xbe, 0x74, 0x99, 0xab, 0xb8, 0xd9, - 0x8c, 0x47, 0xf5, 0xcd, 0x4e, 0x2b, 0xcb, 0x5d, 0x73, 0xb1, 0x10, 0x53, 0x8b, 0xaa, 0x43, 0xa1, - 0x51, 0xa6, 0x9b, 0xab, 0x1d, 0xda, 0xc7, 0x01, 0x77, 0xce, 0xb7, 0x17, 0xc1, 0x09, 0xe7, 0xac, - 0xc2, 0x67, 0x4a, 0xf4, 0x64, 0x0b, 0xff, 0x3b, 0x4d, 0x56, 0x04, 0xeb, 0xe4, 0xdd, 0xd1, 0x18, - 0x38, 0x49, 0x97, 0x74, 0x00, 0xaf, 0x64, 0x99, 0xac, 0x99, 0xd1, 0xbd, 0xbb, 0x8f, 0xe2, 0xba, - 0xd5, 0x3d, 0x33, 0xd7, 0x50, 0xa5, 0x73, 0x50, 0xab, 0x6b, 0x19, 0xd5, 0xe1, 0x3e, 0xc2, 0x8d, - 0x1c, 0xf7, 0x17, 0x11, 0xf5, 0x33, 0x35, 0x2d, 0x3a, 0x78, 0x18, 0x8c, 0xa8, 0xe2, 0x0c, 0x69, - 0x41, 0x23, 0x74, 0xa9, 0x3e, 0x2b, 0xfb, 0xf2, 0xb6, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x48, 0xe0, 0xd0, 0x03, 0xa9, 0xb1, 0x16, 0x04, 0x3c, 0xc1, 0x91, + 0xd9, 0x17, 0x47, 0x39, 0xa8, 0x43, 0x15, 0x59, 0x77, 0x8e, 0x3a, 0xdc, 0x69, 0xea, 0x67, 0x89, + 0x35, 0x24, 0xb2, 0xa0, 0x59, 0xe7, 0x85, 0x9c, 0xb9, 0xd3, 0xe6, 0xaa, 0x02, 0x18, 0x19, 0x7e, + 0x0e, 0x91, 0x87, 0x76, 0xca, 0x98, 0x43, 0x17, 0xf8, 0xa4, 0x1a, 0x05, 0x0b, 0x50, 0xb3, 0xaa, + 0xc5, 0x01, 0xf1, 0xbc, 0x64, 0x3b, 0x90, 0xb9, 0x65, 0x67, 0xd0, 0xae, 0xa5, 0xfe, 0x2e, 0x6b, + 0x57, 0xe6, 0x2c, 0x27, 0xaf, 0x20, 0x20, 0xee, 0x54, 0xae, 0xad, 0xb5, 0x8f, 0xee, 0xf8, 0x4f, + 0x8b, 0xf2, 0xfb, 0x69, 0x34, 0x12, 0x7e, 0x12, 0xbc, 0x5e, 0xd9, 0x76, 0x10, 0x00, 0xee, 0xf6, + 0x40, 0x29, 0xb8, 0x8b, 0xc6, 0xdb, 0x67, 0xb1, 0x61, 0x5b, 0xdb, 0x3a, 0x97, 0x54, 0x04, 0xfb, + 0x96, 0x11, 0x29, 0xec, 0xba, 0xff, 0x4c, 0xe2, 0xa5, 0xfe, 0x1f, 0x51, 0x78, 0xc4, 0x19, 0xd2, + 0x8a, 0xc6, 0x1a, 0x25, 0x75, 0x53, 0xf0, 0x93, 0x9c, 0x9d, 0x3c, 0xdf, 0x88, 0xcf, 0xcd, 0x80, + 0xda, 0xb0, 0xcd, 0x51, 0x4a, 0xf5, 0x94, 0xa0, 0x8c, 0x85, 0xde, 0x7a, 0xd1, 0x09, 0xae, 0xab, + 0x93, 0x78, 0x94, 0x35, 0x18, 0xde, 0xfa, 0x73, 0x0e, 0xc0, 0xcb, 0x6e, 0x7e, 0xc5, 0x9a, 0x65, + 0xc2, 0x49, 0x11, 0xfe, 0xd3, 0x3c, 0xa4, 0x5f, 0x9b, 0xb6, 0x62, 0x7f, 0xd1, 0x3b, 0x77, 0xa0, + 0xfd, 0x95, 0x5c, 0x6a, 0xfc, 0xd5, 0xc0, 0xc1, 0x4a, 0x40, 0xfb, 0x92, 0xce, 0x14, 0x27, 0x80, + 0x3c, 0x5d, 0x09, 0x17, 0x5b, 0x30, 0xe1, 0x2e, 0x26, 0xbd, 0xef, 0xc0, 0xd2, 0x38, 0x4c, 0xb8, + 0x50, 0xe1, 0x0b, 0x85, 0xfd, 0x06, 0x96, 0xe4, 0x5e, 0xeb, 0x14, 0x6f, 0xea, 0xc8, 0xbc, 0x50, + 0x4b, 0x73, 0xd9, 0xd5, 0xbe, 0xfe, 0xad, 0x44, 0xbc, 0x9b, 0xc1, 0x97, 0x30, 0x8a, 0xca, 0x6f, + 0x1d, 0x06, 0xcb, 0x0e, 0xc8, 0x18, 0xaa, 0x80, 0xec, 0xe1, 0x47, 0xd1, 0xf6, 0x1f, 0xe1, 0x8f, + 0x0b, 0x9e, 0xf1, 0xef, 0x7e, 0x36, 0x89, 0xe1, 0x64, 0x18, 0xe3, 0x25, 0x56, 0x0d, 0x1c, 0x81, + 0x2a, 0xf5, 0xde, 0x8e, 0x67, 0xb3, 0x9a, 0xb2, 0xfa, 0x14, 0x48, 0x81, 0x8c, 0x77, 0xcb, 0x4f, + 0xc5, 0x64, 0x83, 0x06, 0x96, 0x4d, 0xdd, 0xa8, 0xef, 0x8c, 0x59, 0x78, 0xb6, 0x61, 0x4a, 0xaa, + 0x08, 0x71, 0xcf, 0x26, 0x6b, 0x39, 0x52, 0xb4, 0x63, 0xee, 0xb6, 0x5d, 0x18, 0x92, 0xda, 0xe1, + 0xd0, 0x5b, 0x3c, 0x9e, 0x78, 0x12, 0xe2, 0x52, 0xa0, 0xc9, 0x24, 0x28, 0x18, 0xb7, 0x44, 0xf2, + 0x19, 0xa5, 0x16, 0x51, 0xfe, 0x7b, 0x9e, 0x97, 0xa6, 0xf2, 0x3b, 0xba, 0x1b, 0x6e, 0xa9, 0x1c, + 0x49, 0xd8, 0xa1, 0xc7, 0x0d, 0xbb, 0xd8, 0x9d, 0xf6, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_client_nvoc.h b/src/nvidia/generated/g_client_nvoc.h index a99684f21..59534b5a8 100644 --- a/src/nvidia/generated/g_client_nvoc.h +++ b/src/nvidia/generated/g_client_nvoc.h @@ -140,6 +140,7 @@ struct RmClient { NvU32 Flags; NvU32 ClientDebuggerState; void *pOSInfo; + void *pOsPidInfo; char name[100]; CLI_SYSTEM_EVENT_INFO CliSysEventInfo; PSECURITY_TOKEN pSecurityToken; diff --git a/src/nvidia/generated/g_client_resource_nvoc.c b/src/nvidia/generated/g_client_resource_nvoc.c index 87fbd21dd..ee9784c9e 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.c +++ b/src/nvidia/generated/g_client_resource_nvoc.c @@ -351,12 +351,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [10] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x127u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS), @@ -381,12 +381,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [12] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x12bu, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS), @@ -576,12 +576,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [25] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x13au, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS), @@ -1801,15 +1801,15 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetHwbcInfo__ = &cliresCtrlCmdSystemGetHwbcInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__cliresCtrlCmdSystemGetP2pCaps__ = &cliresCtrlCmdSystemGetP2pCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__cliresCtrlCmdSystemGetP2pCapsV2__ = &cliresCtrlCmdSystemGetP2pCapsV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__cliresCtrlCmdSystemGetP2pCapsMatrix__ = &cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL; #endif diff --git a/src/nvidia/generated/g_crashcat_report_nvoc.c b/src/nvidia/generated/g_crashcat_report_nvoc.c index 76dac11b3..b178b114e 100644 --- a/src/nvidia/generated/g_crashcat_report_nvoc.c +++ b/src/nvidia/generated/g_crashcat_report_nvoc.c @@ -125,23 +125,31 @@ static void __nvoc_init_funcTable_CrashCatReport_1(CrashCatReport *pThis) { PORT_UNREFERENCED_VARIABLE(reportHal_HalVarIdx); // Hal function -- crashcatReportLogReporter - if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* CrashCatReportHal: V1_GENERIC */ + if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* CrashCatReportHal: V1_LIBOS2 */ { - pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_GENERIC; + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_LIBOS2; + } + else if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000004UL) )) /* CrashCatReportHal: V1_LIBOS3 */ + { + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_LIBOS3; } else { - pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_LIBOS2; + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_GENERIC; } // Hal function -- crashcatReportLogSource - if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* CrashCatReportHal: V1_GENERIC */ + if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* CrashCatReportHal: V1_LIBOS2 */ { - pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_GENERIC; + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_LIBOS2; + } + else if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000004UL) )) /* CrashCatReportHal: V1_LIBOS3 */ + { + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_LIBOS3; } else { - pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_LIBOS2; + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_GENERIC; } } diff --git a/src/nvidia/generated/g_crashcat_report_nvoc.h b/src/nvidia/generated/g_crashcat_report_nvoc.h index ac2befbfb..8c144d64d 100644 --- a/src/nvidia/generated/g_crashcat_report_nvoc.h +++ b/src/nvidia/generated/g_crashcat_report_nvoc.h @@ -71,7 +71,8 @@ struct __nvoc_inner_struc_CrashCatReport_1__ { NvCrashCatReport_V1 report; NvCrashCatRiscv64CsrState_V1 riscv64CsrState; NvCrashCatRiscv64GprState_V1 riscv64GprState; - NvCrashCatRiscv64Trace_V1 *pRiscv64Trace; + NvCrashCatRiscv64Trace_V1 *pRiscv64StackTrace; + NvCrashCatRiscv64Trace_V1 *pRiscv64PcTrace; NvCrashCatIo32State_V1 *pIo32State; }; @@ -236,18 +237,18 @@ static inline void crashcatReportLogRiscv64GprState(struct CrashCatReport *arg0) #define crashcatReportLogRiscv64GprState_HAL(arg0) crashcatReportLogRiscv64GprState(arg0) -void crashcatReportLogRiscv64Trace_V1(struct CrashCatReport *arg0); +void crashcatReportLogRiscv64Traces_V1(struct CrashCatReport *arg0); #ifdef __nvoc_crashcat_report_h_disabled -static inline void crashcatReportLogRiscv64Trace(struct CrashCatReport *arg0) { +static inline void crashcatReportLogRiscv64Traces(struct CrashCatReport *arg0) { NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); } #else //__nvoc_crashcat_report_h_disabled -#define crashcatReportLogRiscv64Trace(arg0) crashcatReportLogRiscv64Trace_V1(arg0) +#define crashcatReportLogRiscv64Traces(arg0) crashcatReportLogRiscv64Traces_V1(arg0) #endif //__nvoc_crashcat_report_h_disabled -#define crashcatReportLogRiscv64Trace_HAL(arg0) crashcatReportLogRiscv64Trace(arg0) +#define crashcatReportLogRiscv64Traces_HAL(arg0) crashcatReportLogRiscv64Traces(arg0) void crashcatReportLogIo32State_V1(struct CrashCatReport *arg0); @@ -266,6 +267,8 @@ void crashcatReportLogReporter_V1_GENERIC(struct CrashCatReport *arg0); void crashcatReportLogReporter_V1_LIBOS2(struct CrashCatReport *arg0); +void crashcatReportLogReporter_V1_LIBOS3(struct CrashCatReport *arg0); + static inline void crashcatReportLogReporter_DISPATCH(struct CrashCatReport *arg0) { arg0->__crashcatReportLogReporter__(arg0); } @@ -274,6 +277,8 @@ void crashcatReportLogSource_V1_GENERIC(struct CrashCatReport *arg0); void crashcatReportLogSource_V1_LIBOS2(struct CrashCatReport *arg0); +void crashcatReportLogSource_V1_LIBOS3(struct CrashCatReport *arg0); + static inline void crashcatReportLogSource_DISPATCH(struct CrashCatReport *arg0) { arg0->__crashcatReportLogSource__(arg0); } @@ -347,8 +352,8 @@ void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64GprState)(struct CrashCatRepo #endif //__nvoc_crashcat_report_h_disabled #ifndef __nvoc_crashcat_report_h_disabled -#undef crashcatReportLogRiscv64Trace -void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64Trace)(struct CrashCatReport *arg0); +#undef crashcatReportLogRiscv64Traces +void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64Traces)(struct CrashCatReport *arg0); #endif //__nvoc_crashcat_report_h_disabled #ifndef __nvoc_crashcat_report_h_disabled diff --git a/src/nvidia/generated/g_device_nvoc.c b/src/nvidia/generated/g_device_nvoc.c index 6b9e2989e..1a9cbc5f4 100644 --- a/src/nvidia/generated/g_device_nvoc.c +++ b/src/nvidia/generated/g_device_nvoc.c @@ -590,6 +590,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] #endif }, { /* [26] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*flags=*/ 0x11u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x801308u, + /*paramSize=*/ sizeof(NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdSetDefaultVidmemPhysicality" +#endif + }, + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -604,7 +619,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCaps" #endif }, - { /* [27] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -619,7 +634,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCapsV2" #endif }, - { /* [28] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -634,7 +649,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCaps" #endif }, - { /* [29] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -649,7 +664,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartSelectedChannels" #endif }, - { /* [30] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -664,7 +679,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetEngineContextProperties" #endif }, - { /* [31] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -679,7 +694,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetChannelList" #endif }, - { /* [32] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -694,7 +709,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetLatencyBufferSize" #endif }, - { /* [33] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -709,7 +724,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoSetChannelProperties" #endif }, - { /* [34] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -724,7 +739,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStopRunlist" #endif }, - { /* [35] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -739,7 +754,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartRunlist" #endif }, - { /* [36] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -754,7 +769,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCapsV2" #endif }, - { /* [37] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -769,7 +784,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoIdleChannels" #endif }, - { /* [38] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -784,7 +799,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPteInfo" #endif }, - { /* [39] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -799,7 +814,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaFlush" #endif }, - { /* [40] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -814,7 +829,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaAdvSchedGetVaCaps" #endif }, - { /* [41] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -829,7 +844,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPdeInfo" #endif }, - { /* [42] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -844,7 +859,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPteInfo" #endif }, - { /* [43] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -859,7 +874,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [44] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -874,7 +889,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetCaps" #endif }, - { /* [45] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -889,7 +904,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetVASpaceSize" #endif }, - { /* [46] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -904,7 +919,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUpdatePde2" #endif }, - { /* [47] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -919,7 +934,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaEnablePrivilegedRange" #endif }, - { /* [48] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -934,7 +949,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetDefaultVASpace" #endif }, - { /* [49] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -949,7 +964,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPageDirectory" #endif }, - { /* [50] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -964,7 +979,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUnsetPageDirectory" #endif }, - { /* [51] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -979,7 +994,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdMsencGetCaps" #endif }, - { /* [52] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -994,7 +1009,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBspGetCapsV2" #endif }, - { /* [53] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1009,7 +1024,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTSwitch" #endif }, - { /* [54] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1024,7 +1039,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTGetFBInfo" #endif }, - { /* [55] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1039,7 +1054,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdNvjpgGetCapsV2" #endif }, - { /* [56] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1054,7 +1069,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [57] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1069,7 +1084,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount" #endif }, - { /* [58] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1089,7 +1104,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] const struct NVOC_EXPORT_INFO __nvoc_export_info_Device = { - /*numEntries=*/ 59, + /*numEntries=*/ 60, /*pExportEntries=*/ __nvoc_exported_method_def_Device }; @@ -1234,6 +1249,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdFbGetCapsV2__ = &deviceCtrlCmdFbGetCapsV2_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + pThis->__deviceCtrlCmdSetDefaultVidmemPhysicality__ = &deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__deviceCtrlCmdFifoGetCaps__ = &deviceCtrlCmdFifoGetCaps_IMPL; #endif diff --git a/src/nvidia/generated/g_device_nvoc.h b/src/nvidia/generated/g_device_nvoc.h index 6f58d1f22..638f9efb9 100644 --- a/src/nvidia/generated/g_device_nvoc.h +++ b/src/nvidia/generated/g_device_nvoc.h @@ -109,6 +109,7 @@ struct Device { NV_STATUS (*__deviceCtrlCmdFbGetCompbitStoreInfo__)(struct Device *, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *); NV_STATUS (*__deviceCtrlCmdFbGetCaps__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdFbGetCapsV2__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_V2_PARAMS *); + NV_STATUS (*__deviceCtrlCmdSetDefaultVidmemPhysicality__)(struct Device *, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoGetCaps__)(struct Device *, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoGetCapsV2__)(struct Device *, NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoStartSelectedChannels__)(struct Device *, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *); @@ -182,6 +183,7 @@ struct Device { NvU64 vaLimitInternal; NvU64 vaSize; NvU32 vaMode; + NvU32 defaultVidmemPhysicalityOverride; struct KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; }; @@ -241,6 +243,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCtrlCmdFbGetCompbitStoreInfo(pDevice, pCompbitStoreParams) deviceCtrlCmdFbGetCompbitStoreInfo_DISPATCH(pDevice, pCompbitStoreParams) #define deviceCtrlCmdFbGetCaps(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCaps_DISPATCH(pDevice, pFbCapsParams) #define deviceCtrlCmdFbGetCapsV2(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCapsV2_DISPATCH(pDevice, pFbCapsParams) +#define deviceCtrlCmdSetDefaultVidmemPhysicality(pDevice, pParams) deviceCtrlCmdSetDefaultVidmemPhysicality_DISPATCH(pDevice, pParams) #define deviceCtrlCmdFifoGetCaps(pDevice, pFifoCapsParams) deviceCtrlCmdFifoGetCaps_DISPATCH(pDevice, pFifoCapsParams) #define deviceCtrlCmdFifoGetCapsV2(pDevice, pFifoCapsParams) deviceCtrlCmdFifoGetCapsV2_DISPATCH(pDevice, pFifoCapsParams) #define deviceCtrlCmdFifoStartSelectedChannels(pDevice, pStartSel) deviceCtrlCmdFifoStartSelectedChannels_DISPATCH(pDevice, pStartSel) @@ -465,6 +468,12 @@ static inline NV_STATUS deviceCtrlCmdFbGetCapsV2_DISPATCH(struct Device *pDevice return pDevice->__deviceCtrlCmdFbGetCapsV2__(pDevice, pFbCapsParams); } +NV_STATUS deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL(struct Device *pDevice, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams); + +static inline NV_STATUS deviceCtrlCmdSetDefaultVidmemPhysicality_DISPATCH(struct Device *pDevice, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams) { + return pDevice->__deviceCtrlCmdSetDefaultVidmemPhysicality__(pDevice, pParams); +} + NV_STATUS deviceCtrlCmdFifoGetCaps_IMPL(struct Device *pDevice, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *pFifoCapsParams); static inline NV_STATUS deviceCtrlCmdFifoGetCaps_DISPATCH(struct Device *pDevice, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *pFifoCapsParams) { diff --git a/src/nvidia/generated/g_generic_engine_nvoc.c b/src/nvidia/generated/g_generic_engine_nvoc.c index 8c05ba103..feb297172 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.c +++ b/src/nvidia/generated/g_generic_engine_nvoc.c @@ -229,12 +229,27 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GenericE /*func=*/ "genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask" #endif }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) genapiCtrlCmdBBXGetLastFlushTime_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + /*flags=*/ 0x250u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x90e70113u, + /*paramSize=*/ sizeof(NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GenericEngineApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "genapiCtrlCmdBBXGetLastFlushTime" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_GenericEngineApi = { - /*numEntries=*/ 2, + /*numEntries=*/ 3, /*pExportEntries=*/ __nvoc_exported_method_def_GenericEngineApi }; @@ -285,6 +300,10 @@ static void __nvoc_init_funcTable_GenericEngineApi_1(GenericEngineApi *pThis) { pThis->__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__ = &genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + pThis->__genapiCtrlCmdBBXGetLastFlushTime__ = &genapiCtrlCmdBBXGetLastFlushTime_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_GenericEngineApi_gpuresMap; pThis->__nvoc_base_GpuResource.__gpuresGetMapAddrSpace__ = &__nvoc_thunk_GenericEngineApi_gpuresGetMapAddrSpace; diff --git a/src/nvidia/generated/g_generic_engine_nvoc.h b/src/nvidia/generated/g_generic_engine_nvoc.h index b3ac4bccb..7fdf92e58 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.h +++ b/src/nvidia/generated/g_generic_engine_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,7 @@ extern "C" { #include "gpu/gpu_resource.h" #include "ctrl/ctrl90e6.h" +#include "ctrl/ctrl90e7.h" #include "rmapi/resource.h" // for macro RMCTRL_EXPORT etc. /*! @@ -61,6 +62,7 @@ struct GenericEngineApi { NV_STATUS (*__genapiControl__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__genapiCtrlCmdMasterGetErrorIntrOffsetMask__)(struct GenericEngineApi *, NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS *); NV_STATUS (*__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__)(struct GenericEngineApi *, NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *); + NV_STATUS (*__genapiCtrlCmdBBXGetLastFlushTime__)(struct GenericEngineApi *, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *); NvBool (*__genapiShareCallback__)(struct GenericEngineApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__genapiCheckMemInterUnmap__)(struct GenericEngineApi *, NvBool); NV_STATUS (*__genapiMapTo__)(struct GenericEngineApi *, RS_RES_MAP_TO_PARAMS *); @@ -118,6 +120,7 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi**, Dynamic*, NvU32, #define genapiControl(pGenericEngineApi, pCallContext, pParams) genapiControl_DISPATCH(pGenericEngineApi, pCallContext, pParams) #define genapiCtrlCmdMasterGetErrorIntrOffsetMask(pGenericEngineApi, pParams) genapiCtrlCmdMasterGetErrorIntrOffsetMask_DISPATCH(pGenericEngineApi, pParams) #define genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask(pGenericEngineApi, pParams) genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_DISPATCH(pGenericEngineApi, pParams) +#define genapiCtrlCmdBBXGetLastFlushTime(pGenericEngineApi, pParams) genapiCtrlCmdBBXGetLastFlushTime_DISPATCH(pGenericEngineApi, pParams) #define genapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) genapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define genapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) genapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define genapiMapTo(pResource, pParams) genapiMapTo_DISPATCH(pResource, pParams) @@ -170,6 +173,12 @@ static inline NV_STATUS genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_D return pGenericEngineApi->__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__(pGenericEngineApi, pParams); } +NV_STATUS genapiCtrlCmdBBXGetLastFlushTime_IMPL(struct GenericEngineApi *pGenericEngineApi, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *pParams); + +static inline NV_STATUS genapiCtrlCmdBBXGetLastFlushTime_DISPATCH(struct GenericEngineApi *pGenericEngineApi, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *pParams) { + return pGenericEngineApi->__genapiCtrlCmdBBXGetLastFlushTime__(pGenericEngineApi, pParams); +} + static inline NvBool genapiShareCallback_DISPATCH(struct GenericEngineApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__genapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } diff --git a/src/nvidia/generated/g_gpu_class_list.c b/src/nvidia/generated/g_gpu_class_list.c index e29b5b36f..06d530358 100644 --- a/src/nvidia/generated/g_gpu_class_list.c +++ b/src/nvidia/generated/g_gpu_class_list.c @@ -39,6 +39,7 @@ gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -103,6 +104,7 @@ gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -168,6 +170,7 @@ gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -234,6 +237,7 @@ gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -298,6 +302,7 @@ gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -381,6 +386,7 @@ gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { FERMI_TWOD_A, ENG_GR(0) }, { FERMI_VASPACE_A, ENG_DMA }, { G84_PERFBUFFER, ENG_BUS }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -444,6 +450,7 @@ gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -514,6 +521,7 @@ gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -584,6 +592,7 @@ gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -654,6 +663,7 @@ gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -724,6 +734,7 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -794,6 +805,7 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -872,6 +884,7 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -950,6 +963,7 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1028,6 +1042,7 @@ gpuGetClassDescriptorList_AD106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1106,6 +1121,7 @@ gpuGetClassDescriptorList_AD107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1175,6 +1191,7 @@ gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { FERMI_TWOD_A, ENG_GR(0) }, { FERMI_VASPACE_A, ENG_DMA }, { G84_PERFBUFFER, ENG_BUS }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.h b/src/nvidia/generated/g_gpu_mgr_nvoc.h index 1ed26c67c..590180fc7 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.h @@ -529,6 +529,7 @@ void gpumgrSetGpuRelease(void); NvU8 gpumgrGetGpuBridgeType(void); NvBool gpumgrAreAllGpusInOffloadMode(void); NvBool gpumgrIsSafeToReadGpuInfo(void); +NvBool gpumgrIsDeviceMsixAllowed(RmPhysAddr bar0BaseAddr, NvU32 pmcBoot1, NvU32 pmcBoot42); // // gpumgrIsSubDeviceCountOne diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index 2be874b0a..c7f5b114d 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -492,6 +492,17 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; } + // Hal function -- gpuReadVgpuConfigReg + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_GH100; + } + // default + else + { + pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_46f6a7; + } + // Hal function -- gpuGetIdInfo if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -621,6 +632,17 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; } + // Hal function -- gpuCheckIfFbhubPoisonIntrPending + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__gpuCheckIfFbhubPoisonIntrPending__ = &gpuCheckIfFbhubPoisonIntrPending_GA100; + } + // default + else + { + pThis->__gpuCheckIfFbhubPoisonIntrPending__ = &gpuCheckIfFbhubPoisonIntrPending_491d52; + } + // Hal function -- gpuReadDeviceId if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -721,6 +743,39 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_491d52; } + + // Hal function -- gpuCheckEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__gpuCheckEccCounts__ = &gpuCheckEccCounts_TU102; + } + // default + else + { + pThis->__gpuCheckEccCounts__ = &gpuCheckEccCounts_d44104; + } + + // Hal function -- gpuClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__gpuClearEccCounts__ = &gpuClearEccCounts_TU102; + } + // default + else + { + pThis->__gpuClearEccCounts__ = &gpuClearEccCounts_ac1694; + } + + // Hal function -- gpuWaitForGfwBootComplete + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_TU102; + } + // default + else + { + pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_5baef9; + } } void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 988a2957e..a1435fd63 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -877,6 +877,7 @@ struct OBJGPU { NV_STATUS (*__gpuReadFunctionConfigReg__)(struct OBJGPU *, NvU32, NvU32, NvU32 *); NV_STATUS (*__gpuWriteFunctionConfigReg__)(struct OBJGPU *, NvU32, NvU32, NvU32); NV_STATUS (*__gpuWriteFunctionConfigRegEx__)(struct OBJGPU *, NvU32, NvU32, NvU32, THREAD_STATE_NODE *); + NV_STATUS (*__gpuReadVgpuConfigReg__)(struct OBJGPU *, NvU32, NvU32 *); void (*__gpuGetIdInfo__)(struct OBJGPU *); void (*__gpuHandleSanityCheckRegReadError__)(struct OBJGPU *, NvU32, NvU32); void (*__gpuHandleSecFault__)(struct OBJGPU *); @@ -885,6 +886,7 @@ struct OBJGPU { NvU32 (*__gpuGetPhysAddrWidth__)(struct OBJGPU *, NV_ADDRESS_SPACE); NvBool (*__gpuFuseSupportsDisplay__)(struct OBJGPU *); NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *); + NvBool (*__gpuCheckIfFbhubPoisonIntrPending__)(struct OBJGPU *); void (*__gpuReadDeviceId__)(struct OBJGPU *, NvU32 *, NvU32 *); NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool); void (*__gpuDetermineSelfHostedMode__)(struct OBJGPU *); @@ -894,6 +896,9 @@ struct OBJGPU { NvBool (*__gpuIsCCEnabledInHw__)(struct OBJGPU *); NvBool (*__gpuIsDevModeEnabledInHw__)(struct OBJGPU *); NvBool (*__gpuIsCtxBufAllocInPmaSupported__)(struct OBJGPU *); + void (*__gpuCheckEccCounts__)(struct OBJGPU *); + NV_STATUS (*__gpuClearEccCounts__)(struct OBJGPU *); + NV_STATUS (*__gpuWaitForGfwBootComplete__)(struct OBJGPU *); NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED; NvBool bVideoLinkDisabled; GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; @@ -1007,6 +1012,9 @@ struct OBJGPU { NvU32 subdeviceInstance; NvS32 numaNodeId; _GPU_UUID gpuUuid; + NvU32 gpuPhysicalId; + NvU32 gpuTerminatedLinkMask; + NvBool gpuLinkTerminationEnabled; NvBool gspRmInitialized; _GPU_PCIE_PEER_CLIQUE pciePeerClique; NvU32 i2cPortForExtdev; @@ -1427,6 +1435,8 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, #define gpuWriteFunctionConfigReg_HAL(pGpu, function, reg, data) gpuWriteFunctionConfigReg_DISPATCH(pGpu, function, reg, data) #define gpuWriteFunctionConfigRegEx(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_DISPATCH(pGpu, function, reg, data, pThreadState) #define gpuWriteFunctionConfigRegEx_HAL(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_DISPATCH(pGpu, function, reg, data, pThreadState) +#define gpuReadVgpuConfigReg(pGpu, index, data) gpuReadVgpuConfigReg_DISPATCH(pGpu, index, data) +#define gpuReadVgpuConfigReg_HAL(pGpu, index, data) gpuReadVgpuConfigReg_DISPATCH(pGpu, index, data) #define gpuGetIdInfo(pGpu) gpuGetIdInfo_DISPATCH(pGpu) #define gpuGetIdInfo_HAL(pGpu) gpuGetIdInfo_DISPATCH(pGpu) #define gpuHandleSanityCheckRegReadError(pGpu, addr, value) gpuHandleSanityCheckRegReadError_DISPATCH(pGpu, addr, value) @@ -1443,6 +1453,8 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, #define gpuFuseSupportsDisplay_HAL(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) +#define gpuCheckIfFbhubPoisonIntrPending(pGpu) gpuCheckIfFbhubPoisonIntrPending_DISPATCH(pGpu) +#define gpuCheckIfFbhubPoisonIntrPending_HAL(pGpu) gpuCheckIfFbhubPoisonIntrPending_DISPATCH(pGpu) #define gpuReadDeviceId(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) #define gpuReadDeviceId_HAL(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) #define gpuGetFlaVasSize(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) @@ -1461,6 +1473,12 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, #define gpuIsDevModeEnabledInHw_HAL(pGpu) gpuIsDevModeEnabledInHw_DISPATCH(pGpu) #define gpuIsCtxBufAllocInPmaSupported(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu) #define gpuIsCtxBufAllocInPmaSupported_HAL(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu) +#define gpuCheckEccCounts(pGpu) gpuCheckEccCounts_DISPATCH(pGpu) +#define gpuCheckEccCounts_HAL(pGpu) gpuCheckEccCounts_DISPATCH(pGpu) +#define gpuClearEccCounts(pGpu) gpuClearEccCounts_DISPATCH(pGpu) +#define gpuClearEccCounts_HAL(pGpu) gpuClearEccCounts_DISPATCH(pGpu) +#define gpuWaitForGfwBootComplete(pGpu) gpuWaitForGfwBootComplete_DISPATCH(pGpu) +#define gpuWaitForGfwBootComplete_HAL(pGpu) gpuWaitForGfwBootComplete_DISPATCH(pGpu) static inline NV_STATUS gpuConstructPhysical_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } @@ -2422,6 +2440,19 @@ static inline void gpuUpdateUserSharedData(struct OBJGPU *pGpu) { #define gpuUpdateUserSharedData_HAL(pGpu) gpuUpdateUserSharedData(pGpu) +void gpuGetTerminatedLinkMask_GA100(struct OBJGPU *pGpu, NvU32 arg0); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuGetTerminatedLinkMask(struct OBJGPU *pGpu, NvU32 arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuGetTerminatedLinkMask(pGpu, arg0) gpuGetTerminatedLinkMask_GA100(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + +#define gpuGetTerminatedLinkMask_HAL(pGpu, arg0) gpuGetTerminatedLinkMask(pGpu, arg0) + NV_STATUS gpuJtVersionSanityCheck_TU102(struct OBJGPU *pGpu); @@ -2970,6 +3001,16 @@ static inline NV_STATUS gpuWriteFunctionConfigRegEx_DISPATCH(struct OBJGPU *pGpu return pGpu->__gpuWriteFunctionConfigRegEx__(pGpu, function, reg, data, pThreadState); } +NV_STATUS gpuReadVgpuConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 *data); + +static inline NV_STATUS gpuReadVgpuConfigReg_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS gpuReadVgpuConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) { + return pGpu->__gpuReadVgpuConfigReg__(pGpu, index, data); +} + void gpuGetIdInfo_GM107(struct OBJGPU *pGpu); void gpuGetIdInfo_GH100(struct OBJGPU *pGpu); @@ -3066,6 +3107,16 @@ static inline NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(struct OBJ return pGpu->__gpuClearFbhubPoisonIntrForBug2924523__(pGpu); } +NvBool gpuCheckIfFbhubPoisonIntrPending_GA100(struct OBJGPU *pGpu); + +static inline NvBool gpuCheckIfFbhubPoisonIntrPending_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuCheckIfFbhubPoisonIntrPending_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuCheckIfFbhubPoisonIntrPending__(pGpu); +} + void gpuReadDeviceId_GM107(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); void gpuReadDeviceId_GH100(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); @@ -3160,6 +3211,36 @@ static inline NvBool gpuIsCtxBufAllocInPmaSupported_DISPATCH(struct OBJGPU *pGpu return pGpu->__gpuIsCtxBufAllocInPmaSupported__(pGpu); } +static inline void gpuCheckEccCounts_d44104(struct OBJGPU *pGpu) { + return; +} + +void gpuCheckEccCounts_TU102(struct OBJGPU *pGpu); + +static inline void gpuCheckEccCounts_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuCheckEccCounts__(pGpu); +} + +static inline NV_STATUS gpuClearEccCounts_ac1694(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuClearEccCounts_TU102(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuClearEccCounts_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuClearEccCounts__(pGpu); +} + +NV_STATUS gpuWaitForGfwBootComplete_TU102(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuWaitForGfwBootComplete_5baef9(struct OBJGPU *pGpu) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS gpuWaitForGfwBootComplete_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuWaitForGfwBootComplete__(pGpu); +} + static inline PENGDESCRIPTOR gpuGetInitEngineDescriptors(struct OBJGPU *pGpu) { return pGpu->engineOrder.pEngineInitDescriptors; } @@ -4639,6 +4720,13 @@ VGPU_STATIC_INFO *gpuGetStaticInfo(struct OBJGPU *pGpu); GspStaticConfigInfo *gpuGetGspStaticInfo(struct OBJGPU *pGpu); #define GPU_GET_GSP_STATIC_INFO(pGpu) gpuGetGspStaticInfo(pGpu) +// +// This function needs to be called when OBJGPU is not created. HAL +// infrastructure can’t be used for this case, so it has been added manually. +// It will be invoked directly by gpumgrIsDeviceMsixAllowed(). +// +NvBool gpuIsMsixAllowed_TU102(RmPhysAddr bar0BaseAddr); + #endif // _OBJGPU_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kern_bus_nvoc.c b/src/nvidia/generated/g_kern_bus_nvoc.c index c2927afc7..1995acf09 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.c +++ b/src/nvidia/generated/g_kern_bus_nvoc.c @@ -892,6 +892,28 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusTeardownCoherentCpuMapping__ = &kbusTeardownCoherentCpuMapping_d44104; } + // Hal function -- kbusGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusGetEccCounts__ = &kbusGetEccCounts_GH100; + } + // default + else + { + pThis->__kbusGetEccCounts__ = &kbusGetEccCounts_4a4dee; + } + + // Hal function -- kbusClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusClearEccCounts__ = &kbusClearEccCounts_GH100; + } + // default + else + { + pThis->__kbusClearEccCounts__ = &kbusClearEccCounts_b3696a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBus_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelBus_engstateStatePreInitLocked; diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h index 13981ff48..8d6dd8a11 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.h +++ b/src/nvidia/generated/g_kern_bus_nvoc.h @@ -381,6 +381,8 @@ struct KernelBus { NvU8 *(*__kbusMapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusUnmapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusTeardownCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvBool); + NvU32 (*__kbusGetEccCounts__)(OBJGPU *, struct KernelBus *); + void (*__kbusClearEccCounts__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusStatePostUnload__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateInitUnlocked__)(POBJGPU, struct KernelBus *); void (*__kbusInitMissing__)(POBJGPU, struct KernelBus *); @@ -607,6 +609,10 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusGetEccCounts(pGpu, pKernelBus) kbusGetEccCounts_DISPATCH(pGpu, pKernelBus) +#define kbusGetEccCounts_HAL(pGpu, pKernelBus) kbusGetEccCounts_DISPATCH(pGpu, pKernelBus) +#define kbusClearEccCounts(pGpu, pKernelBus) kbusClearEccCounts_DISPATCH(pGpu, pKernelBus) +#define kbusClearEccCounts_HAL(pGpu, pKernelBus) kbusClearEccCounts_DISPATCH(pGpu, pKernelBus) #define kbusStatePostUnload(pGpu, pEngstate, arg0) kbusStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbusStateInitUnlocked(pGpu, pEngstate) kbusStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbusInitMissing(pGpu, pEngstate) kbusInitMissing_DISPATCH(pGpu, pEngstate) @@ -2215,6 +2221,26 @@ static inline void kbusTeardownCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct pKernelBus->__kbusTeardownCoherentCpuMapping__(pGpu, pKernelBus, arg0); } +NvU32 kbusGetEccCounts_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvU32 kbusGetEccCounts_4a4dee(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return 0; +} + +static inline NvU32 kbusGetEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusGetEccCounts__(pGpu, pKernelBus); +} + +void kbusClearEccCounts_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline void kbusClearEccCounts_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return; +} + +static inline void kbusClearEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + pKernelBus->__kbusClearEccCounts__(pGpu, pKernelBus); +} + static inline NV_STATUS kbusStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { return pEngstate->__kbusStatePostUnload__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.c b/src/nvidia/generated/g_kern_fsp_nvoc.c index e53bfc294..763ecadd0 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.c +++ b/src/nvidia/generated/g_kern_fsp_nvoc.c @@ -137,10 +137,14 @@ void __nvoc_dtor_KernelFsp(KernelFsp *pThis) { void __nvoc_init_dataField_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) { ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KFSP_IS_MISSING if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ @@ -152,6 +156,12 @@ void __nvoc_init_dataField_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspe { pThis->setProperty(pThis, PDB_PROP_KFSP_IS_MISSING, ((NvBool)(0 == 0))); } + + // NVOC Property Hal field -- PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->setProperty(pThis, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM, ((NvBool)(0 == 0))); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -171,10 +181,14 @@ __nvoc_ctor_KernelFsp_exit: static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) { ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); pThis->__kfspConstructEngine__ = &kfspConstructEngine_IMPL; diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.c b/src/nvidia/generated/g_kern_gmmu_nvoc.c index 6e905e2bb..64e1c5991 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.c +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.c @@ -493,6 +493,28 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuReadShadowBufPutIndex__ = &kgmmuReadShadowBufPutIndex_4a4dee; } + // Hal function -- kgmmuGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kgmmuGetEccCounts__ = &kgmmuGetEccCounts_TU102; + } + // default + else + { + pThis->__kgmmuGetEccCounts__ = &kgmmuGetEccCounts_4a4dee; + } + + // Hal function -- kgmmuClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kgmmuClearEccCounts__ = &kgmmuClearEccCounts_TU102; + } + // default + else + { + pThis->__kgmmuClearEccCounts__ = &kgmmuClearEccCounts_b3696a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGmmu_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelGmmu_engstateStateInitLocked; diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.h b/src/nvidia/generated/g_kern_gmmu_nvoc.h index ecf9ea11d..65638e36b 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.h +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.h @@ -356,6 +356,8 @@ struct KernelGmmu { NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); NvU32 (*__kgmmuReadShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); + NvU32 (*__kgmmuGetEccCounts__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuClearEccCounts__)(OBJGPU *, struct KernelGmmu *); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); @@ -433,6 +435,8 @@ struct KernelGmmu_PRIVATE { NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); NvU32 (*__kgmmuReadShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); + NvU32 (*__kgmmuGetEccCounts__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuClearEccCounts__)(OBJGPU *, struct KernelGmmu *); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); @@ -561,6 +565,10 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuGetGraphicsEngineId_HAL(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) #define kgmmuReadShadowBufPutIndex(pGpu, pKernelGmmu, type) kgmmuReadShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, type) #define kgmmuReadShadowBufPutIndex_HAL(pGpu, pKernelGmmu, type) kgmmuReadShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, type) +#define kgmmuGetEccCounts(pGpu, pKernelGmmu) kgmmuGetEccCounts_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuGetEccCounts_HAL(pGpu, pKernelGmmu) kgmmuGetEccCounts_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuClearEccCounts(pGpu, pKernelGmmu) kgmmuClearEccCounts_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuClearEccCounts_HAL(pGpu, pKernelGmmu) kgmmuClearEccCounts_DISPATCH(pGpu, pKernelGmmu) #define kgmmuStateLoad(pGpu, pEngstate, arg0) kgmmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStateUnload(pGpu, pEngstate, arg0) kgmmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuServiceNotificationInterrupt(pGpu, pIntrService, pParams) kgmmuServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -1305,6 +1313,26 @@ static inline NvU32 kgmmuReadShadowBufPutIndex_DISPATCH(OBJGPU *pGpu, struct Ker return pKernelGmmu->__kgmmuReadShadowBufPutIndex__(pGpu, pKernelGmmu, type); } +NvU32 kgmmuGetEccCounts_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NvU32 kgmmuGetEccCounts_4a4dee(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return 0; +} + +static inline NvU32 kgmmuGetEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuGetEccCounts__(pGpu, pKernelGmmu); +} + +void kgmmuClearEccCounts_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline void kgmmuClearEccCounts_b3696a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return; +} + +static inline void kgmmuClearEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + pKernelGmmu->__kgmmuClearEccCounts__(pGpu, pKernelGmmu); +} + static inline NV_STATUS kgmmuStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { return pEngstate->__kgmmuStateLoad__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.c b/src/nvidia/generated/g_kern_mem_sys_nvoc.c index 9df9f5fce..72145d6d2 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.c +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.c @@ -425,6 +425,73 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysRemoveAllAtsPeers__ = &kmemsysRemoveAllAtsPeers_GV100; } + // Hal function -- kmemsysGetMaxFbpas + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000020UL) )) /* ChipHal: TU102 */ + { + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_GA100; + } + // default + else + { + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_4a4dee; + } + + // Hal function -- kmemsysGetEccDedCountSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysGetEccDedCountSize__ = &kmemsysGetEccDedCountSize_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000420UL) )) /* ChipHal: TU102 | GA100 */ + { + pThis->__kmemsysGetEccDedCountSize__ = &kmemsysGetEccDedCountSize_TU102; + } + // default + else + { + pThis->__kmemsysGetEccDedCountSize__ = &kmemsysGetEccDedCountSize_4a4dee; + } + + // Hal function -- kmemsysGetEccDedCountRegAddr + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysGetEccDedCountRegAddr__ = &kmemsysGetEccDedCountRegAddr_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000420UL) )) /* ChipHal: TU102 | GA100 */ + { + pThis->__kmemsysGetEccDedCountRegAddr__ = &kmemsysGetEccDedCountRegAddr_TU102; + } + // default + else + { + pThis->__kmemsysGetEccDedCountRegAddr__ = &kmemsysGetEccDedCountRegAddr_4a4dee; + } + + // Hal function -- kmemsysGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kmemsysGetEccCounts__ = &kmemsysGetEccCounts_TU102; + } + // default + else + { + pThis->__kmemsysGetEccCounts__ = &kmemsysGetEccCounts_b3696a; + } + + // Hal function -- kmemsysClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_TU102; + } + // default + else + { + pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_b3696a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMemorySystem_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelMemorySystem_engstateStateInitLocked; diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.h b/src/nvidia/generated/g_kern_mem_sys_nvoc.h index 68c61725d..b581a43a2 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.h +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.h @@ -222,6 +222,11 @@ struct KernelMemorySystem { void (*__kmemsysNumaRemoveAllMemory__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysSetupAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); void (*__kmemsysRemoveAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetMaxFbpas__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetEccDedCountSize__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetEccDedCountRegAddr__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32); + void (*__kmemsysGetEccCounts__)(OBJGPU *, struct KernelMemorySystem *, NvU32 *, NvU32 *); + void (*__kmemsysClearEccCounts__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStateLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStateUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStatePostUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); @@ -247,6 +252,8 @@ struct KernelMemorySystem { NvU64 coherentCpuFbEnd; NvU64 numaOnlineBase; NvU64 numaOnlineSize; + NvU64 numaMigPartitionSize[15]; + NvBool bNumaMigPartitionSizeEnumerated; }; #ifndef __NVOC_CLASS_KernelMemorySystem_TYPEDEF__ @@ -323,6 +330,16 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysSetupAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysSetupAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysRemoveAllAtsPeers(pGpu, pKernelMemorySystem) kmemsysRemoveAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysRemoveAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysRemoveAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetMaxFbpas(pGpu, pKernelMemorySystem) kmemsysGetMaxFbpas_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetMaxFbpas_HAL(pGpu, pKernelMemorySystem) kmemsysGetMaxFbpas_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountSize(pGpu, pKernelMemorySystem) kmemsysGetEccDedCountSize_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountSize_HAL(pGpu, pKernelMemorySystem) kmemsysGetEccDedCountSize_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountRegAddr(pGpu, pKernelMemorySystem, fbpa, subp) kmemsysGetEccDedCountRegAddr_DISPATCH(pGpu, pKernelMemorySystem, fbpa, subp) +#define kmemsysGetEccDedCountRegAddr_HAL(pGpu, pKernelMemorySystem, fbpa, subp) kmemsysGetEccDedCountRegAddr_DISPATCH(pGpu, pKernelMemorySystem, fbpa, subp) +#define kmemsysGetEccCounts(pGpu, pKernelMemorySystem, arg0, arg1) kmemsysGetEccCounts_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1) +#define kmemsysGetEccCounts_HAL(pGpu, pKernelMemorySystem, arg0, arg1) kmemsysGetEccCounts_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1) +#define kmemsysClearEccCounts(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysClearEccCounts_HAL(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysStateLoad(pGpu, pEngstate, arg0) kmemsysStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStateUnload(pGpu, pEngstate, arg0) kmemsysStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStatePostUnload(pGpu, pEngstate, arg0) kmemsysStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -733,6 +750,62 @@ static inline void kmemsysRemoveAllAtsPeers_DISPATCH(OBJGPU *pGpu, struct Kernel pKernelMemorySystem->__kmemsysRemoveAllAtsPeers__(pGpu, pKernelMemorySystem); } +NvU32 kmemsysGetMaxFbpas_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +NvU32 kmemsysGetMaxFbpas_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysGetMaxFbpas_4a4dee(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return 0; +} + +static inline NvU32 kmemsysGetMaxFbpas_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysGetMaxFbpas__(pGpu, pKernelMemorySystem); +} + +NvU32 kmemsysGetEccDedCountSize_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +NvU32 kmemsysGetEccDedCountSize_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysGetEccDedCountSize_4a4dee(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return 0; +} + +static inline NvU32 kmemsysGetEccDedCountSize_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysGetEccDedCountSize__(pGpu, pKernelMemorySystem); +} + +NvU32 kmemsysGetEccDedCountRegAddr_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp); + +NvU32 kmemsysGetEccDedCountRegAddr_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp); + +static inline NvU32 kmemsysGetEccDedCountRegAddr_4a4dee(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp) { + return 0; +} + +static inline NvU32 kmemsysGetEccDedCountRegAddr_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp) { + return pKernelMemorySystem->__kmemsysGetEccDedCountRegAddr__(pGpu, pKernelMemorySystem, fbpa, subp); +} + +void kmemsysGetEccCounts_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 *arg0, NvU32 *arg1); + +static inline void kmemsysGetEccCounts_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 *arg0, NvU32 *arg1) { + return; +} + +static inline void kmemsysGetEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 *arg0, NvU32 *arg1) { + pKernelMemorySystem->__kmemsysGetEccCounts__(pGpu, pKernelMemorySystem, arg0, arg1); +} + +void kmemsysClearEccCounts_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline void kmemsysClearEccCounts_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return; +} + +static inline void kmemsysClearEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + pKernelMemorySystem->__kmemsysClearEccCounts__(pGpu, pKernelMemorySystem); +} + static inline NV_STATUS kmemsysStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { return pEngstate->__kmemsysStateLoad__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index d0aa00e1e..c1052d00c 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -483,6 +483,28 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_TU102; } + // Hal function -- kbifGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetEccCounts__ = &kbifGetEccCounts_GH100; + } + // default + else + { + pThis->__kbifGetEccCounts__ = &kbifGetEccCounts_4a4dee; + } + + // Hal function -- kbifClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifClearEccCounts__ = &kbifClearEccCounts_GH100; + } + // default + else + { + pThis->__kbifClearEccCounts__ = &kbifClearEccCounts_56cd7a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBif_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelBif_engstateStateInitLocked; diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index fd6a9aa14..b87121645 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -116,6 +116,8 @@ struct KernelBif { NV_STATUS (*__kbifGetBusOptionsAddr__)(struct OBJGPU *, struct KernelBif *, BUS_OPTIONS, NvU32 *); NV_STATUS (*__kbifPreOsGlobalErotGrantRequest__)(struct OBJGPU *, struct KernelBif *); void (*__kbifCacheVFInfo__)(struct OBJGPU *, struct KernelBif *); + NvU32 (*__kbifGetEccCounts__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifClearEccCounts__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifStatePreLoad__)(POBJGPU, struct KernelBif *, NvU32); NV_STATUS (*__kbifStatePostUnload__)(POBJGPU, struct KernelBif *, NvU32); void (*__kbifStateDestroy__)(POBJGPU, struct KernelBif *); @@ -266,6 +268,10 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelBif) kbifPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelBif) #define kbifCacheVFInfo(pGpu, pKernelBif) kbifCacheVFInfo_DISPATCH(pGpu, pKernelBif) #define kbifCacheVFInfo_HAL(pGpu, pKernelBif) kbifCacheVFInfo_DISPATCH(pGpu, pKernelBif) +#define kbifGetEccCounts(pGpu, pKernelBif) kbifGetEccCounts_DISPATCH(pGpu, pKernelBif) +#define kbifGetEccCounts_HAL(pGpu, pKernelBif) kbifGetEccCounts_DISPATCH(pGpu, pKernelBif) +#define kbifClearEccCounts(pGpu, pKernelBif) kbifClearEccCounts_DISPATCH(pGpu, pKernelBif) +#define kbifClearEccCounts_HAL(pGpu, pKernelBif) kbifClearEccCounts_DISPATCH(pGpu, pKernelBif) #define kbifStatePreLoad(pGpu, pEngstate, arg0) kbifStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbifStatePostUnload(pGpu, pEngstate, arg0) kbifStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbifStateDestroy(pGpu, pEngstate) kbifStateDestroy_DISPATCH(pGpu, pEngstate) @@ -617,6 +623,26 @@ static inline void kbifCacheVFInfo_DISPATCH(struct OBJGPU *pGpu, struct KernelBi pKernelBif->__kbifCacheVFInfo__(pGpu, pKernelBif); } +NvU32 kbifGetEccCounts_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NvU32 kbifGetEccCounts_4a4dee(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return 0; +} + +static inline NvU32 kbifGetEccCounts_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifGetEccCounts__(pGpu, pKernelBif); +} + +NV_STATUS kbifClearEccCounts_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifClearEccCounts_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return NV_OK; +} + +static inline NV_STATUS kbifClearEccCounts_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifClearEccCounts__(pGpu, pKernelBif); +} + static inline NV_STATUS kbifStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { return pEngstate->__kbifStatePreLoad__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.c b/src/nvidia/generated/g_kernel_ce_nvoc.c index 54d03c2e5..b1f4d93f8 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_nvoc.c @@ -221,6 +221,16 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceServiceNotificationInterrupt__ = &kceServiceNotificationInterrupt_IMPL; + // Hal function -- kceGetP2PCes + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceGetP2PCes__ = &kceGetP2PCes_GH100; + } + else + { + pThis->__kceGetP2PCes__ = &kceGetP2PCes_GV100; + } + // Hal function -- kceGetNvlinkAutoConfigCeValues if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.h b/src/nvidia/generated/g_kernel_ce_nvoc.h index bb03062a2..90d04d2b7 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_nvoc.h @@ -113,6 +113,7 @@ struct KernelCE { NV_STATUS (*__kceStateUnload__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceRegisterIntrService__)(OBJGPU *, struct KernelCE *, IntrServiceRecord *); NV_STATUS (*__kceServiceNotificationInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceNotificationInterruptArguments *); + NV_STATUS (*__kceGetP2PCes__)(struct KernelCE *, OBJGPU *, NvU32, NvU32 *); NV_STATUS (*__kceGetNvlinkAutoConfigCeValues__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); NvBool (*__kceGetNvlinkMaxTopoForTable__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, void *, NvU32, NvU32 *); NvBool (*__kceIsCurrentMaxTopology__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *); @@ -190,6 +191,8 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceStateUnload_HAL(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) #define kceRegisterIntrService(arg0, arg1, arg2) kceRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define kceServiceNotificationInterrupt(arg0, arg1, arg2) kceServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) +#define kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_DISPATCH(arg0, pGpu, gpuMask, nvlinkP2PCeMask) +#define kceGetP2PCes_HAL(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_DISPATCH(arg0, pGpu, gpuMask, nvlinkP2PCeMask) #define kceGetNvlinkAutoConfigCeValues(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) #define kceGetNvlinkAutoConfigCeValues_HAL(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) #define kceGetNvlinkMaxTopoForTable(pGpu, pKCe, arg0, arg1, arg2, arg3) kceGetNvlinkMaxTopoForTable_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3) @@ -305,20 +308,6 @@ static inline NvBool kceIsCeNvlinkP2P(OBJGPU *pGpu, struct KernelCE *pKCe) { #define kceIsCeNvlinkP2P_HAL(pGpu, pKCe) kceIsCeNvlinkP2P(pGpu, pKCe) -NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); - - -#ifdef __nvoc_kernel_ce_h_disabled -static inline NV_STATUS kceGetP2PCes(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { - NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_ce_h_disabled -#define kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_GV100(arg0, pGpu, gpuMask, nvlinkP2PCeMask) -#endif //__nvoc_kernel_ce_h_disabled - -#define kceGetP2PCes_HAL(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) - void kceGetSysmemRWLCEs_GV100(struct KernelCE *arg0, NvU32 *rd, NvU32 *wr); @@ -397,6 +386,14 @@ static inline NV_STATUS kceServiceNotificationInterrupt_DISPATCH(OBJGPU *arg0, s return arg1->__kceServiceNotificationInterrupt__(arg0, arg1, arg2); } +NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); + +NV_STATUS kceGetP2PCes_GH100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); + +static inline NV_STATUS kceGetP2PCes_DISPATCH(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { + return arg0->__kceGetP2PCes__(arg0, pGpu, gpuMask, nvlinkP2PCeMask); +} + NV_STATUS kceGetNvlinkAutoConfigCeValues_TU102(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); NV_STATUS kceGetNvlinkAutoConfigCeValues_GA100(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index b8573c500..96c0144de 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -118,6 +118,10 @@ static NV_STATUS __nvoc_thunk_KernelGsp_kflcnResetHw(struct OBJGPU *pGpu, struct return kgspResetHw(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelFalcon.offset)); } +static void __nvoc_thunk_KernelGsp_kcrashcatEngineReadEmem(struct KernelCrashCatEngine *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf) { + kgspReadEmem((struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, size, pBuf); +} + static NvBool __nvoc_thunk_KernelCrashCatEngine_kgspConfigured(struct KernelGsp *arg0) { return kcrashcatEngineConfigured((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset)); } @@ -166,10 +170,6 @@ static NvBool __nvoc_thunk_OBJENGSTATE_kgspIsPresent(POBJGPU pGpu, struct Kernel return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); } -static void __nvoc_thunk_KernelCrashCatEngine_kgspReadEmem(struct KernelGsp *arg0, NvU64 offset, NvU64 size, void *pBuf) { - kcrashcatEngineReadEmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, size, pBuf); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateLoad(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } @@ -314,6 +314,21 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe pThis->fwHeapParamOsCarveoutSize = (20 << 20); } } + + // Hal field -- ememPort + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->ememPort = 6; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->ememPort = 2; + } + // default + else + { + pThis->ememPort = 0; + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -779,6 +794,9 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; } + // Hal function -- kgspReadEmem + pThis->__kgspReadEmem__ = &kgspReadEmem_TU102; + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGsp_engstateConstructEngine; pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelGsp_intrservRegisterIntrService; @@ -787,6 +805,8 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelGsp_kflcnResetHw; + pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__kcrashcatEngineReadEmem__ = &__nvoc_thunk_KernelGsp_kcrashcatEngineReadEmem; + pThis->__kgspConfigured__ = &__nvoc_thunk_KernelCrashCatEngine_kgspConfigured; pThis->__kgspPriRead__ = &__nvoc_thunk_KernelCrashCatEngine_kgspPriRead; @@ -811,8 +831,6 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__kgspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgspIsPresent; - pThis->__kgspReadEmem__ = &__nvoc_thunk_KernelCrashCatEngine_kgspReadEmem; - pThis->__kgspStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStateLoad; pThis->__kgspGetScratchOffsets__ = &__nvoc_thunk_KernelCrashCatEngine_kgspGetScratchOffsets; diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index 9f487bb00..a18ac7f0e 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -296,6 +296,7 @@ struct KernelGsp { NV_STATUS (*__kgspFreeVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32); const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspSetupGspFmcArgs__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); + void (*__kgspReadEmem__)(struct KernelGsp *, NvU64, NvU64, void *); NvBool (*__kgspConfigured__)(struct KernelGsp *); NvU32 (*__kgspPriRead__)(struct KernelGsp *, NvU32); void (*__kgspRegWrite__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32); @@ -308,7 +309,6 @@ struct KernelGsp { void (*__kgspSyncBufferDescriptor__)(struct KernelGsp *, CrashCatBufferDescriptor *, NvU32, NvU32); NvU32 (*__kgspRegRead__)(struct OBJGPU *, struct KernelGsp *, NvU32); NvBool (*__kgspIsPresent__)(POBJGPU, struct KernelGsp *); - void (*__kgspReadEmem__)(struct KernelGsp *, NvU64, NvU64, void *); NV_STATUS (*__kgspStateLoad__)(POBJGPU, struct KernelGsp *, NvU32); const NvU32 *(*__kgspGetScratchOffsets__)(struct KernelGsp *, NV_CRASHCAT_SCRATCH_GROUP_ID); void (*__kgspUnload__)(struct KernelGsp *); @@ -381,6 +381,7 @@ struct KernelGsp { NvBool bScrubberUcodeSupported; NvU32 fwHeapParamBaseSize; NvU32 fwHeapParamOsCarveoutSize; + NvU8 ememPort; }; #ifndef __NVOC_CLASS_KernelGsp_TYPEDEF__ @@ -488,6 +489,8 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetSignatureSectionNamePrefix_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp) #define kgspSetupGspFmcArgs(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspReadEmem(pKernelGsp, offset, size, pBuf) kgspReadEmem_DISPATCH(pKernelGsp, offset, size, pBuf) +#define kgspReadEmem_HAL(pKernelGsp, offset, size, pBuf) kgspReadEmem_DISPATCH(pKernelGsp, offset, size, pBuf) #define kgspConfigured(arg0) kgspConfigured_DISPATCH(arg0) #define kgspPriRead(arg0, offset) kgspPriRead_DISPATCH(arg0, offset) #define kgspRegWrite(pGpu, pKernelFlcn, offset, data) kgspRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) @@ -500,7 +503,6 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspSyncBufferDescriptor(arg0, pBufDesc, offset, size) kgspSyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size) #define kgspRegRead(pGpu, pKernelFlcn, offset) kgspRegRead_DISPATCH(pGpu, pKernelFlcn, offset) #define kgspIsPresent(pGpu, pEngstate) kgspIsPresent_DISPATCH(pGpu, pEngstate) -#define kgspReadEmem(arg0, offset, size, pBuf) kgspReadEmem_DISPATCH(arg0, offset, size, pBuf) #define kgspStateLoad(pGpu, pEngstate, arg0) kgspStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgspGetScratchOffsets(arg0, scratchGroupId) kgspGetScratchOffsets_DISPATCH(arg0, scratchGroupId) #define kgspUnload(arg0) kgspUnload_DISPATCH(arg0) @@ -1018,6 +1020,12 @@ static inline NV_STATUS kgspSetupGspFmcArgs_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspSetupGspFmcArgs__(pGpu, pKernelGsp, pGspFw); } +void kgspReadEmem_TU102(struct KernelGsp *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf); + +static inline void kgspReadEmem_DISPATCH(struct KernelGsp *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf) { + pKernelGsp->__kgspReadEmem__(pKernelGsp, offset, size, pBuf); +} + static inline NvBool kgspConfigured_DISPATCH(struct KernelGsp *arg0) { return arg0->__kgspConfigured__(arg0); } @@ -1066,10 +1074,6 @@ static inline NvBool kgspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEng return pEngstate->__kgspIsPresent__(pGpu, pEngstate); } -static inline void kgspReadEmem_DISPATCH(struct KernelGsp *arg0, NvU64 offset, NvU64 size, void *pBuf) { - arg0->__kgspReadEmem__(arg0, offset, size, pBuf); -} - static inline NV_STATUS kgspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return pEngstate->__kgspStateLoad__(pGpu, pEngstate, arg0); } @@ -1339,6 +1343,8 @@ void kgspFreeVbiosImg(KernelGspVbiosImg *pVbiosImg); /* Free a KernelGspFlcnUcode structure */ void kgspFreeFlcnUcode(KernelGspFlcnUcode *pFlcnUcode); +void kgspLogRpcDebugInfo(struct OBJGPU *pGpu, OBJRPC *pRpc, NvU32 errorNum, NvBool bPollingForRpcResponse); + #endif // KERNEL_GSP_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kernel_rc_nvoc.h b/src/nvidia/generated/g_kernel_rc_nvoc.h index c7bdf1b68..4272e241e 100644 --- a/src/nvidia/generated/g_kernel_rc_nvoc.h +++ b/src/nvidia/generated/g_kernel_rc_nvoc.h @@ -527,6 +527,17 @@ static inline void krcWatchdogCallbackVblankRecovery(struct OBJGPU *pGpu, struct #define krcWatchdogCallbackVblankRecovery(pGpu, pKernelRc) krcWatchdogCallbackVblankRecovery_IMPL(pGpu, pKernelRc) #endif //__nvoc_kernel_rc_h_disabled +NV_STATUS krcWatchdogGetClientHandle_IMPL(struct KernelRc *arg0, NvHandle *arg1); + +#ifdef __nvoc_kernel_rc_h_disabled +static inline NV_STATUS krcWatchdogGetClientHandle(struct KernelRc *arg0, NvHandle *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_rc_h_disabled +#define krcWatchdogGetClientHandle(arg0, arg1) krcWatchdogGetClientHandle_IMPL(arg0, arg1) +#endif //__nvoc_kernel_rc_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c index 609fed6e1..272f98729 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c @@ -105,10 +105,6 @@ static NV_STATUS __nvoc_thunk_MemoryMulticastFabric_memControl(struct Memory *pM return memorymulticastfabricControl((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_MemoryMulticastFabric_rmresControl_Prologue(struct RmResource *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memorymulticastfabricControl_Prologue((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); -} - static NvBool __nvoc_thunk_MemoryMulticastFabric_memIsGpuMapAllowed(struct Memory *pMemoryMulticastFabric, struct OBJGPU *pGpu) { return memorymulticastfabricIsGpuMapAllowed((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pGpu); } @@ -137,6 +133,10 @@ static void __nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pReference); } +static NV_STATUS __nvoc_thunk_RmResource_memorymulticastfabricControl_Prologue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); } @@ -324,8 +324,6 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricControl__ = &memorymulticastfabricControl_IMPL; - pThis->__memorymulticastfabricControl_Prologue__ = &memorymulticastfabricControl_Prologue_IMPL; - pThis->__memorymulticastfabricIsGpuMapAllowed__ = &memorymulticastfabricIsGpuMapAllowed_IMPL; pThis->__memorymulticastfabricGetMapAddrSpace__ = &memorymulticastfabricGetMapAddrSpace_IMPL; @@ -356,8 +354,6 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryMulticastFabric_memControl; - pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__rmresControl_Prologue__ = &__nvoc_thunk_MemoryMulticastFabric_rmresControl_Prologue; - pThis->__nvoc_base_Memory.__memIsGpuMapAllowed__ = &__nvoc_thunk_MemoryMulticastFabric_memIsGpuMapAllowed; pThis->__nvoc_base_Memory.__memGetMapAddrSpace__ = &__nvoc_thunk_MemoryMulticastFabric_memGetMapAddrSpace; @@ -372,6 +368,8 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants; + pThis->__memorymulticastfabricControl_Prologue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Prologue; + pThis->__memorymulticastfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom; pThis->__memorymulticastfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue; diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h index 19353539a..e266ff092 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h @@ -158,7 +158,6 @@ struct MemoryMulticastFabric { NV_STATUS (*__memorymulticastfabricCopyConstruct__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricIsReady__)(struct MemoryMulticastFabric *, NvBool); NV_STATUS (*__memorymulticastfabricControl__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memorymulticastfabricControl_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memorymulticastfabricIsGpuMapAllowed__)(struct MemoryMulticastFabric *, struct OBJGPU *); NV_STATUS (*__memorymulticastfabricGetMapAddrSpace__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__memorymulticastfabricCtrlGetInfo__)(struct MemoryMulticastFabric *, NV00FD_CTRL_GET_INFO_PARAMS *); @@ -171,6 +170,7 @@ struct MemoryMulticastFabric { NV_STATUS (*__memorymulticastfabricMapTo__)(struct MemoryMulticastFabric *, RS_RES_MAP_TO_PARAMS *); NvU32 (*__memorymulticastfabricGetRefCount__)(struct MemoryMulticastFabric *); void (*__memorymulticastfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryMulticastFabric *, RsResourceRef *); + NV_STATUS (*__memorymulticastfabricControl_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricUnmapFrom__)(struct MemoryMulticastFabric *, RS_RES_UNMAP_FROM_PARAMS *); void (*__memorymulticastfabricControl_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricControlLookup__)(struct MemoryMulticastFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -220,7 +220,6 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric**, Dynami #define memorymulticastfabricCopyConstruct(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricCopyConstruct_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) #define memorymulticastfabricIsReady(pMemoryMulticastFabric, bCopyConstructorContext) memorymulticastfabricIsReady_DISPATCH(pMemoryMulticastFabric, bCopyConstructorContext) #define memorymulticastfabricControl(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricControl_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) -#define memorymulticastfabricControl_Prologue(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricControl_Prologue_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) #define memorymulticastfabricIsGpuMapAllowed(pMemoryMulticastFabric, pGpu) memorymulticastfabricIsGpuMapAllowed_DISPATCH(pMemoryMulticastFabric, pGpu) #define memorymulticastfabricGetMapAddrSpace(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) memorymulticastfabricGetMapAddrSpace_DISPATCH(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) #define memorymulticastfabricCtrlGetInfo(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlGetInfo_DISPATCH(pMemoryMulticastFabric, pParams) @@ -233,6 +232,7 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric**, Dynami #define memorymulticastfabricMapTo(pResource, pParams) memorymulticastfabricMapTo_DISPATCH(pResource, pParams) #define memorymulticastfabricGetRefCount(pResource) memorymulticastfabricGetRefCount_DISPATCH(pResource) #define memorymulticastfabricAddAdditionalDependants(pClient, pResource, pReference) memorymulticastfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memorymulticastfabricControl_Prologue(pResource, pCallContext, pParams) memorymulticastfabricControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memorymulticastfabricUnmapFrom(pResource, pParams) memorymulticastfabricUnmapFrom_DISPATCH(pResource, pParams) #define memorymulticastfabricControl_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memorymulticastfabricControlLookup(pResource, pParams, ppEntry) memorymulticastfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -271,12 +271,6 @@ static inline NV_STATUS memorymulticastfabricControl_DISPATCH(struct MemoryMulti return pMemoryMulticastFabric->__memorymulticastfabricControl__(pMemoryMulticastFabric, pCallContext, pParams); } -NV_STATUS memorymulticastfabricControl_Prologue_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); - -static inline NV_STATUS memorymulticastfabricControl_Prologue_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemoryMulticastFabric->__memorymulticastfabricControl_Prologue__(pMemoryMulticastFabric, pCallContext, pParams); -} - NvBool memorymulticastfabricIsGpuMapAllowed_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, struct OBJGPU *pGpu); static inline NvBool memorymulticastfabricIsGpuMapAllowed_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, struct OBJGPU *pGpu) { @@ -339,6 +333,10 @@ static inline void memorymulticastfabricAddAdditionalDependants_DISPATCH(struct pResource->__memorymulticastfabricAddAdditionalDependants__(pClient, pResource, pReference); } +static inline NV_STATUS memorymulticastfabricControl_Prologue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memorymulticastfabricControl_Prologue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS memorymulticastfabricUnmapFrom_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__memorymulticastfabricUnmapFrom__(pResource, pParams); } diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index 4db8e3386..adc2aec36 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -1810,21 +1810,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2322, 0x17ee, 0x10DE, "NVIDIA H800-40C" }, { 0x2322, 0x17ef, 0x10DE, "NVIDIA H800-80C" }, { 0x2322, 0x1845, 0x10DE, "NVIDIA H800-1-20C" }, - { 0x2330, 0x187a, 0x10DE, "NVIDIA H100XM-1-10CME" }, - { 0x2330, 0x187b, 0x10DE, "NVIDIA H100XM-1-10C" }, - { 0x2330, 0x187c, 0x10DE, "NVIDIA H100XM-1-20C" }, - { 0x2330, 0x187d, 0x10DE, "NVIDIA H100XM-2-20C" }, - { 0x2330, 0x187e, 0x10DE, "NVIDIA H100XM-3-40C" }, - { 0x2330, 0x187f, 0x10DE, "NVIDIA H100XM-4-40C" }, - { 0x2330, 0x1880, 0x10DE, "NVIDIA H100XM-7-80C" }, - { 0x2330, 0x1881, 0x10DE, "NVIDIA H100XM-4C" }, - { 0x2330, 0x1882, 0x10DE, "NVIDIA H100XM-5C" }, - { 0x2330, 0x1883, 0x10DE, "NVIDIA H100XM-8C" }, - { 0x2330, 0x1884, 0x10DE, "NVIDIA H100XM-10C" }, - { 0x2330, 0x1885, 0x10DE, "NVIDIA H100XM-16C" }, - { 0x2330, 0x1886, 0x10DE, "NVIDIA H100XM-20C" }, - { 0x2330, 0x1887, 0x10DE, "NVIDIA H100XM-40C" }, - { 0x2330, 0x1888, 0x10DE, "NVIDIA H100XM-80C" }, { 0x2331, 0x16d3, 0x10DE, "NVIDIA H100-1-10C" }, { 0x2331, 0x16d4, 0x10DE, "NVIDIA H100-2-20C" }, { 0x2331, 0x16d5, 0x10DE, "NVIDIA H100-3-40C" }, @@ -2046,8 +2031,8 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B9, 0x189c, 0x10DE, "NVIDIA L40S-16A" }, { 0x26B9, 0x189d, 0x10DE, "NVIDIA L40S-24A" }, { 0x26B9, 0x189e, 0x10DE, "NVIDIA L40S-48A" }, - { 0x26B9, 0x189f, 0x10DE, "GeForce RTX 3050" }, - { 0x26B9, 0x18a0, 0x10DE, "GeForce RTX 3060" }, + { 0x26B9, 0x189f, 0x10DE, "NVIDIA GeForce RTX 3050" }, + { 0x26B9, 0x18a0, 0x10DE, "NVIDIA GeForce RTX 3060" }, { 0x26B9, 0x18a1, 0x10DE, "NVIDIA L40S-1" }, { 0x26B9, 0x18a2, 0x10DE, "NVIDIA L40S-2" }, { 0x26B9, 0x18a3, 0x10DE, "NVIDIA L40S-3" }, diff --git a/src/nvidia/generated/g_os_nvoc.h b/src/nvidia/generated/g_os_nvoc.h index 0345d983f..60cc7fb8b 100644 --- a/src/nvidia/generated/g_os_nvoc.h +++ b/src/nvidia/generated/g_os_nvoc.h @@ -880,6 +880,10 @@ NV_STATUS osReserveCpuAddressSpaceUpperBound(void **ppSectionHandle, NvU64 maxSectionSize); void osReleaseCpuAddressSpaceUpperBound(void *pSectionHandle); +void* osGetPidInfo(void); +void osPutPidInfo(void *pOsPidInfo); +NV_STATUS osFindNsPid(void *pOsPidInfo, NvU32 *pNsPid); + // OS Tegra IPC functions NV_STATUS osTegraDceRegisterIpcClient(NvU32 interfaceType, void *usrCtx, NvU32 *clientId); @@ -1249,6 +1253,8 @@ static NV_INLINE NV_STATUS isrWrapper(NvBool testIntr, OBJGPU *pGpu) #define OS_PCIE_CAP_MASK_REQ_ATOMICS_64 NVBIT(1) #define OS_PCIE_CAP_MASK_REQ_ATOMICS_128 NVBIT(2) +void osGetNumaMemoryUsage(NvS32 numaId, NvU64 *free_memory_bytes, NvU64 *total_memory_bytes); + NV_STATUS osNumaAddGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, NvU64 size, NvU32 *pNumaNodeId); void osNumaRemoveGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.c b/src/nvidia/generated/g_profiler_v2_nvoc.c index 15948201d..703b7ae3a 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.c +++ b/src/nvidia/generated/g_profiler_v2_nvoc.c @@ -455,6 +455,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [17] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0117u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdDisableDynamicMMABoost" +#endif + }, + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0118u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdGetDynamicMMABoostStatus" +#endif + }, + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -469,7 +499,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalPermissionsInit" #endif }, - { /* [18] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -484,7 +514,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalAllocPmaStream" #endif }, - { /* [19] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -499,7 +529,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalFreePmaStream" #endif }, - { /* [20] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -514,7 +544,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalGetMaxPmas" #endif }, - { /* [21] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -529,7 +559,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalBindPmResources" #endif }, - { /* [22] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -544,7 +574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalUnbindPmResources" #endif }, - { /* [23] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -559,7 +589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalReserveHwpmLegacy" #endif }, - { /* [24] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -574,7 +604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdRequestCgControls" #endif }, - { /* [25] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -594,7 +624,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler const struct NVOC_EXPORT_INFO __nvoc_export_info_ProfilerBase = { - /*numEntries=*/ 26, + /*numEntries=*/ 28, /*pExportEntries=*/ __nvoc_exported_method_def_ProfilerBase }; @@ -745,6 +775,14 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdReleaseCgControls__ = &profilerBaseCtrlCmdReleaseCgControls_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdDisableDynamicMMABoost__ = &profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdGetDynamicMMABoostStatus__ = &profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL; +#endif + pThis->__profilerBaseShareCallback__ = &__nvoc_thunk_GpuResource_profilerBaseShareCallback; pThis->__profilerBaseCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap; diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.h b/src/nvidia/generated/g_profiler_v2_nvoc.h index d84a9a491..951e5de4a 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.h +++ b/src/nvidia/generated/g_profiler_v2_nvoc.h @@ -92,6 +92,8 @@ struct ProfilerBase { NV_STATUS (*__profilerBaseCtrlCmdReleaseHes__)(struct ProfilerBase *, NVB0CC_CTRL_RELEASE_HES_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdRequestCgControls__)(struct ProfilerBase *, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReleaseCgControls__)(struct ProfilerBase *, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdDisableDynamicMMABoost__)(struct ProfilerBase *, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdGetDynamicMMABoostStatus__)(struct ProfilerBase *, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *); NvBool (*__profilerBaseShareCallback__)(struct ProfilerBase *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__profilerBaseCheckMemInterUnmap__)(struct ProfilerBase *, NvBool); NV_STATUS (*__profilerBaseMapTo__)(struct ProfilerBase *, RS_RES_MAP_TO_PARAMS *); @@ -180,6 +182,8 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseCtrlCmdReleaseHes(pProfiler, pParams) profilerBaseCtrlCmdReleaseHes_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdRequestCgControls(pProfiler, pParams) profilerBaseCtrlCmdRequestCgControls_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReleaseCgControls(pProfiler, pParams) profilerBaseCtrlCmdReleaseCgControls_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdDisableDynamicMMABoost(pProfiler, pParams) profilerBaseCtrlCmdDisableDynamicMMABoost_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdGetDynamicMMABoostStatus(pProfiler, pParams) profilerBaseCtrlCmdGetDynamicMMABoostStatus_DISPATCH(pProfiler, pParams) #define profilerBaseShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerBaseShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define profilerBaseCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerBaseCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define profilerBaseMapTo(pResource, pParams) profilerBaseMapTo_DISPATCH(pResource, pParams) @@ -392,6 +396,18 @@ static inline NV_STATUS profilerBaseCtrlCmdReleaseCgControls_DISPATCH(struct Pro return pProfiler->__profilerBaseCtrlCmdReleaseCgControls__(pProfiler, pParams); } +NV_STATUS profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdDisableDynamicMMABoost_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdDisableDynamicMMABoost__(pProfiler, pParams); +} + +NV_STATUS profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdGetDynamicMMABoostStatus_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdGetDynamicMMABoostStatus__(pProfiler, pParams); +} + static inline NvBool profilerBaseShareCallback_DISPATCH(struct ProfilerBase *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__profilerBaseShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } diff --git a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h index 37ce899a9..f9967e28c 100644 --- a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h +++ b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h @@ -1184,6 +1184,7 @@ struct NVOCFwdDeclHack { struct KernelHostVgpuDeviceApi *PRIVATE_FIELD(KernelHostVgpuDeviceApi_NVA084_KERNEL_HOST_VGPU_DEVICE); struct ThirdPartyP2P *PRIVATE_FIELD(ThirdPartyP2P_NV50_THIRD_PARTY_P2P); struct GenericEngineApi *PRIVATE_FIELD(GenericEngineApi_GF100_SUBDEVICE_MASTER); + struct GenericEngineApi *PRIVATE_FIELD(GenericEngineApi_GF100_SUBDEVICE_INFOROM); struct TimerApi *PRIVATE_FIELD(TimerApi_NV01_TIMER); struct I2cApi *PRIVATE_FIELD(I2cApi_NV40_I2C); struct DiagApi *PRIVATE_FIELD(DiagApi_NV20_SUBDEVICE_DIAG); diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index 68b6d7496..190cdfc0a 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -1753,12 +1753,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [101] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetSKUInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + /*flags=*/ 0x212u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800808u, /*paramSize=*/ sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS), @@ -5668,12 +5668,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [362] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) - /*flags=*/ 0x6210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + /*flags=*/ 0x4210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801829u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS), @@ -7825,7 +7825,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBiosGetNbsiV2__ = &subdeviceCtrlCmdBiosGetNbsiV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__subdeviceCtrlCmdBiosGetSKUInfo__ = &subdeviceCtrlCmdBiosGetSKUInfo_IMPL; #endif @@ -7969,9 +7969,8 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusGetEomStatus__ = &subdeviceCtrlCmdBusGetEomStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) - pThis->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__ = &subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBusGetPcieReqAtomicsCaps + pThis->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__ = &subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_92bfc3; #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) pThis->__subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics__ = &subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_IMPL; diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 1ae58323f..86c9d679a 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -747,6 +747,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdBusGetUphyDlnCfgSpace(pSubdevice, pParams) subdeviceCtrlCmdBusGetUphyDlnCfgSpace_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetEomStatus(pSubdevice, pParams) subdeviceCtrlCmdBusGetEomStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetPcieReqAtomicsCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_HAL(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetC2CInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetC2CErrorInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CErrorInfo_DISPATCH(pSubdevice, pParams) @@ -1487,7 +1488,10 @@ static inline NV_STATUS subdeviceCtrlCmdBusGetEomStatus_DISPATCH(struct Subdevic return pSubdevice->__subdeviceCtrlCmdBusGetEomStatus__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams); +static inline NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__(pSubdevice, pParams); diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index 08f267944..9011d22e7 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -412,6 +412,7 @@ #define RMCFG_CLASS_MAXWELL_PROFILER 1 // Base Profiler Class #define RMCFG_CLASS_MAXWELL_PROFILER_DEVICE 1 // Device level Profiler Client Support #define RMCFG_CLASS_GF100_SUBDEVICE_MASTER 1 +#define RMCFG_CLASS_GF100_SUBDEVICE_INFOROM 1 // Inforom interface #define RMCFG_CLASS_GF100_ZBC_CLEAR 1 #define RMCFG_CLASS_GF100_DISP_SW 1 #define RMCFG_CLASS_GF100_TIMED_SEMAPHORE_SW 1 diff --git a/src/nvidia/inc/kernel/core/printf.h b/src/nvidia/inc/kernel/core/printf.h index 96846c77a..b66247a66 100644 --- a/src/nvidia/inc/kernel/core/printf.h +++ b/src/nvidia/inc/kernel/core/printf.h @@ -301,6 +301,15 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length); #define DBG_VAL_PTR(p) #endif +#define NV_ERROR_LOG(pGpu, num, fmt, ...) \ + nvErrorLog_va((void*)pGpu, num, fmt, ##__VA_ARGS__); \ + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \ + NV_PRINTF_ADD_PREFIX("Xid %d: " fmt), num, ##__VA_ARGS__) + +#define NV_ERROR_LOG_DATA(pGpu, num, fmt, ...) \ + portDbgPrintf(NV_PRINTF_ADD_PREFIX(fmt), ##__VA_ARGS__); \ + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \ + NV_PRINTF_ADD_PREFIX(fmt), ##__VA_ARGS__) void nvErrorLog(void *pVoid, NvU32 num, const char *pFormat, va_list arglist); void nvErrorLog_va(void * pGpu, NvU32 num, const char * pFormat, ...); diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h index 93a7d821b..eeed65d4c 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h @@ -177,10 +177,9 @@ typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 phys */ typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected); typedef void (*pmaMapDestroy_t)(void *pMap); -typedef void (*pmaMapChangeState_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState); -typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, NvBool writeAttrib); typedef void (*pmaMapChangeStateAttribEx_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); -typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, NvBool writeAttrib); +typedef void (*pmaMapChangePageStateAttribEx_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); +typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU64 numFrames, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib); typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, @@ -200,10 +199,9 @@ struct _PMA_MAP_INFO NvU32 mode; pmaMapInit_t pmaMapInit; pmaMapDestroy_t pmaMapDestroy; - pmaMapChangeState_t pmaMapChangeState; - pmaMapChangeStateAttrib_t pmaMapChangeStateAttrib; pmaMapChangeStateAttribEx_t pmaMapChangeStateAttribEx; - pmaMapChangePageStateAttrib_t pmaMapChangePageStateAttrib; + pmaMapChangePageStateAttribEx_t pmaMapChangePageStateAttribEx; + pmaMapChangeBlockStateAttrib_t pmaMapChangeBlockStateAttrib; pmaMapRead_t pmaMapRead; pmaMapScanContiguous_t pmaMapScanContiguous; pmaMapScanDiscontiguous_t pmaMapScanDiscontiguous; diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h index 1e3a5605d..8de31675f 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h @@ -90,34 +90,6 @@ NvU64 pmaRegmapGetEvictingFrames(void *pMap); void pmaRegmapSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess); /*! - * @brief Changes the recorded state bits - * - * Changes the state of the bits given the physical frame number - * - * @param[in] pMap The regmap to change - * @param[in] frameNum The frame number to change - * @param[in] newState The new state to change to - * - * @return void - */ -void pmaRegmapChangeState(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState); - -/*! - * @brief Changes the recorded state & attrib bits - * - * Changes the state of the bits given the physical frame number - * - * @param[in] pMap The regmap to change - * @param[in] frameNum The frame number to change - * @param[in] newState The new state to change to - * @param[in] writeAttrib Write attribute bits as well - * - * @return void - */ -void pmaRegmapChangeStateAttrib(void *pMap, NvU64 frameNum, - PMA_PAGESTATUS newState, NvBool writeAttrib); - -/*! * @brief Changes the recorded state & attrib bits for an entire page * * Changes the state of the bits for an entire page given the physical @@ -131,8 +103,8 @@ void pmaRegmapChangeStateAttrib(void *pMap, NvU64 frameNum, * * @return void */ -void pmaRegmapChangePageStateAttrib(void * pMap, NvU64 frameNumStart, NvU64 pageSize, - PMA_PAGESTATUS newState, NvBool writeAttrib); +void pmaRegmapChangePageStateAttribEx(void * pMap, NvU64 frameNumStart, NvU64 pageSize, + PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); /*! * @brief Changes the state & attrib bits specified by mask @@ -151,6 +123,25 @@ void pmaRegmapChangeStateAttribEx(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newStateMask); /*! + * @brief Changes the state & attrib bits specified by mask + * + * Changes the state of the bits given the physical frame number + * and the number of frames to change + * + * @param[in] pMap The regmap to change + * @param[in] frameNum The frame number to change + * @param[in] numFrames The number of frames to change + * @param[in] newState The new state to change to + * @param[in] newStateMask Specific bits to write + * + * @return void + */ +void pmaRegmapChangeBlockStateAttrib(void *pMap, NvU64 frameNum, + NvU64 numFrames, + PMA_PAGESTATUS newState, + PMA_PAGESTATUS newStateMask); + +/*! * @brief Read the page state & attrib bits * * Read the state of the page given the physical frame number diff --git a/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h b/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h index fffe04183..d971568ef 100644 --- a/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h +++ b/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h @@ -79,6 +79,7 @@ typedef struct { NvNotification *notifiers[NV_MAX_SUBDEVICES]; NvNotification *errorContext; NvNotification *notifierToken; + NvBool bHandleValid; } KernelWatchdog; diff --git a/src/nvidia/inc/kernel/rmapi/rmapi_utils.h b/src/nvidia/inc/kernel/rmapi/rmapi_utils.h index 56efc8290..457da64d2 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi_utils.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi_utils.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,6 +25,7 @@ #include "rmapi/rmapi.h" + // // Alloc a client, device and subdevice handle for a gpu // diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index cfb32ed0f..645a50787 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -1919,4 +1919,14 @@ #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_DISABLE 0 #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE 1 +// +// Type DWORD +// This regkey force-disables write-combine iomap allocations, used for chipsets where +// write-combine is broken. +// +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC "RmForceDisableIomapWC" +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES 0x00000001 +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 0x00000000 +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_DEFAULT NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO + #endif // NVRM_REGISTRY_H diff --git a/src/nvidia/kernel/inc/objrpc.h b/src/nvidia/kernel/inc/objrpc.h index 95e1dbbc3..f0e22cf7b 100644 --- a/src/nvidia/kernel/inc/objrpc.h +++ b/src/nvidia/kernel/inc/objrpc.h @@ -53,7 +53,9 @@ typedef struct _object_vgpu OBJVGPU, *POBJVGPU; typedef struct RpcHistoryEntry { NvU32 function; - NvU32 data[3]; + NvU64 data[2]; + NvU64 ts_start; + NvU64 ts_end; } RpcHistoryEntry; struct OBJRPC{ @@ -79,6 +81,8 @@ struct OBJRPC{ RpcHistoryEntry rpcHistory[RPC_HISTORY_DEPTH]; NvU32 rpcHistoryCurrent; + RpcHistoryEntry rpcEventHistory[RPC_HISTORY_DEPTH]; + NvU32 rpcEventHistoryCurrent; NvU32 timeoutCount; NvBool bQuietPrints; diff --git a/src/nvidia/kernel/vgpu/nv/objvgpu.c b/src/nvidia/kernel/vgpu/nv/objvgpu.c index b4c44f5d1..f5d333925 100644 --- a/src/nvidia/kernel/vgpu/nv/objvgpu.c +++ b/src/nvidia/kernel/vgpu/nv/objvgpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #include "core/core.h" +#include "core/locks.h" #include "os/os.h" #include "gpu/gpu.h" #include "vgpu/vgpu_version.h" @@ -39,7 +40,7 @@ vgpuCreateObject OBJGPU *pGpu ) { - NV_STATUS rmStatus = NV_OK; + NV_STATUS rmStatus = NV_OK; return rmStatus; } diff --git a/src/nvidia/src/kernel/diagnostics/nvlog_printf.c b/src/nvidia/src/kernel/diagnostics/nvlog_printf.c index 32a2c1ec5..d031c8bfe 100644 --- a/src/nvidia/src/kernel/diagnostics/nvlog_printf.c +++ b/src/nvidia/src/kernel/diagnostics/nvlog_printf.c @@ -1283,7 +1283,7 @@ done: // RmMsgPrefix - Add the RmMsg prefix to the passed in string, returning // the length of the formatted string. // -// Format: "NVRM file linenum function timestamp: " +// Format: "NVRM: file linenum function timestamp: " // NvU32 RmMsgPrefix @@ -1306,7 +1306,8 @@ RmMsgPrefix { portStringCopy(str + len, totalLen - len, NV_PRINTF_PREFIX, sizeof(NV_PRINTF_PREFIX)); len += sizeof(NV_PRINTF_PREFIX) - 1; - space = " "; + portStringCopy(str + len, totalLen - len, NV_PRINTF_PREFIX_SEPARATOR, sizeof(NV_PRINTF_PREFIX_SEPARATOR)); + len += sizeof(NV_PRINTF_PREFIX_SEPARATOR) - 1; } if (prefix & NVRM_MSG_PREFIX_FILE) diff --git a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c index 3e7c75d7d..9934421c1 100644 --- a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +++ b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c @@ -237,3 +237,11 @@ gpuGetChildrenPresent_GA102(OBJGPU *pGpu, NvU32 *pNumEntries) return gpuChildrenPresent_GA102; } +NvBool +gpuCheckIfFbhubPoisonIntrPending_GA100 +( + OBJGPU *pGpu +) +{ + return intrIsVectorPending_HAL(pGpu, GPU_GET_INTR(pGpu), NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT, NULL); +} diff --git a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c index 681c0dc34..af04f7c88 100644 --- a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c +++ b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c @@ -32,6 +32,7 @@ #include "published/hopper/gh100/dev_pmc.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" +#include "published/hopper/gh100/dev_xtl_ep_pri.h" #include "ctrl/ctrl2080/ctrl2080mc.h" @@ -78,6 +79,28 @@ gpuReadBusConfigReg_GH100 } /*! + * @brief Read the non-private registers on vGPU through mirror space + * + * @param[in] pGpu GPU object pointer + * @param[in] index Register offset in PCIe config space + * @param[out] pData Value of the register + * + * @returns NV_OK on success + */ +NV_STATUS +gpuReadVgpuConfigReg_GH100 +( + OBJGPU *pGpu, + NvU32 index, + NvU32 *pData +) +{ + *pData = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index); + + return NV_OK; +} + +/*! * @brief Get GPU ID based on PCIE config reads. * Also determine other properties of the PCIE capabilities. * diff --git a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c index 8ad221cb0..447b82528 100644 --- a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c @@ -24,8 +24,17 @@ #include "gpu/gpu_child_class_defs.h" #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/hwproject.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/mem_mgr/rm_page_size.h" +#include "nverror.h" #include "jt.h" +#include "published/turing/tu102/dev_nv_xve.h" +#include "published/turing/tu102/dev_gc6_island.h" +#include "published/turing/tu102/dev_gc6_island_addendum.h" + /*! * @brief Returns SR-IOV capabilities * @@ -257,3 +266,235 @@ gpuJtVersionSanityCheck_TU102 gpuJtVersionSanityCheck_TU102_EXIT: return status; } + +/* + * @brief Function that checks if ECC error occurred by reading various count + * registers/interrupt registers. This function is not floorsweeping-aware so + * PRI errors are ignored + */ +void +gpuCheckEccCounts_TU102 +( + OBJGPU *pGpu +) +{ + NvU32 dramCount = 0; + NvU32 ltcCount = 0; + NvU32 mmuCount = 0; + NvU32 pcieCount = 0; + + kmemsysGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu), &dramCount, <cCount); + mmuCount += kgmmuGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_GMMU(pGpu)); + pcieCount += kbifGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_BIF(pGpu)); + pcieCount += kbusGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu)); + + // If counts > 0 or if poison interrupt pending, ECC error has occurred. + if (((dramCount + ltcCount + mmuCount + pcieCount) != 0) || gpuCheckIfFbhubPoisonIntrPending_HAL(pGpu)) + { + NV_ERROR_LOG(pGpu, UNRECOVERABLE_ECC_ERROR_ESCAPE, + "An uncorrectable ECC error detected " + "(possible firmware handling failure) " + "DRAM:%d, LTC:%d, MMU:%d, PCIE:%d", dramCount, ltcCount, mmuCount, pcieCount); + } +} + +/* + * @brief Function that clears ECC error count registers. + */ +NV_STATUS +gpuClearEccCounts_TU102 +( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + + gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu); + + kmemsysClearEccCounts_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + + kgmmuClearEccCounts_HAL(pGpu, GPU_GET_KERNEL_GMMU(pGpu)); + + kbusClearEccCounts_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu)); + + status = kbifClearEccCounts_HAL(pGpu, GPU_GET_KERNEL_BIF(pGpu)); + if (status != NV_OK) + { + return status; + } + + return NV_OK; +} + +// +// This function checks for GFW boot completion status by reading +// NV_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED bits and +// return true if GFW boot has completed. +// +// Either pGpu or pgc6VirtAddr should be not null. +// This function needs to be called in early init code-path where OBJGPU +// has not created. For that case, the NV_PGC6 base address will be mapped +// and pgc6VirtAddr will contain the virtual address for NV_PGC6. +// If pgc6VirtAddr is not null, then read the register with MEM_RD32, +// otherwise use the GPU_REG_RD32. +// +// The current GFW boot progress value will be returned in gfwBootProgressVal. +// +static NvBool +_gpuIsGfwBootCompleted_TU102 +( + OBJGPU *pGpu, + NvU8 *pgc6VirtAddr, + NvU32 *gfwBootProgressVal +) +{ + NvU32 regVal; + + if (pgc6VirtAddr != NULL) + { + regVal = MEM_RD32(pgc6VirtAddr + + (NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK - + DEVICE_BASE(NV_PGC6))); + } + else + { + regVal = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK); + } + + // + // Before reading the actual GFW_BOOT status register, + // we want to check that FWSEC has lowered its PLM first. + // If not then obviously it has not completed. + // + if (!FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK, + _READ_PROTECTION_LEVEL0, _ENABLE, regVal)) + { + *gfwBootProgressVal = 0x0; + return NV_FALSE; + } + + if (pgc6VirtAddr != NULL) + { + regVal = MEM_RD32(pgc6VirtAddr + + (NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT - + DEVICE_BASE(NV_PGC6))); + } + else + { + regVal = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT); + } + + *gfwBootProgressVal = DRF_VAL(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, + _PROGRESS, regVal); + + return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, + _PROGRESS, _COMPLETED, regVal); +} + +#define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms +#define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s +#define GPU_GFW_BOOT_COMPLETION_TIMEOUT_US (FWSECLIC_PROG_START_TIMEOUT + \ + FWSECLIC_PROG_COMPLETE_TIMEOUT) +NV_STATUS +gpuWaitForGfwBootComplete_TU102 +( + OBJGPU *pGpu +) +{ + NvU32 timeoutUs = GPU_GFW_BOOT_COMPLETION_TIMEOUT_US; + NvU32 gfwBootProgressVal = 0; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + + // Use the OS timer since the GPU timer is not ready yet + gpuSetTimeout(pGpu, gpuScaleTimeout(pGpu, timeoutUs), &timeout, + GPU_TIMEOUT_FLAGS_OSTIMER); + + while (status == NV_OK) + { + if (_gpuIsGfwBootCompleted_TU102(pGpu, NULL, &gfwBootProgressVal)) + { + return NV_OK; + } + + status = gpuCheckTimeout(pGpu, &timeout); + } + + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: (progress 0x%x)\n", + gfwBootProgressVal); + return status; +} + +// +// Workaround for Bug 3809777. +// +// This function is not created through HAL infrastructure. It needs to be +// called when OBJGPU is not created. HAL infrastructure can’t be used for +// this case, so it has been added manually. It will be invoked directly by +// gpumgrIsDeviceMsixAllowed() after checking the GPU architecture. +// +// When driver is running inside guest in pass-through mode, check if MSI-X +// is enabled by reading NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP. The devinit +// can disable MSI-X capability, if configured. The hypervisor issues reset +// before launching VM. After reset, the MSI-X capability will be visible +// for some duration and then devinit hides the MSI-X capability. This +// devinit will run in the background. During this time, the hypervisor can +// assume that MSI-X capability is present in the GPU and configure the guest +// GPU PCIe device instance with MSI-X capability. When GPU tries to use the +// MSI-X interrupts later, then interrupt won’t be triggered. To identify +// this case, wait for GPU devinit completion and check if MSI-X capability +// is not hidden. +// +NvBool gpuIsMsixAllowed_TU102 +( + RmPhysAddr bar0BaseAddr +) +{ + NvU8 *vAddr; + NvU32 regVal; + NvU32 timeUs = 0; + NvU32 gfwBootProgressVal = 0; + NvBool bGfwBootCompleted = NV_FALSE; + + ct_assert(DRF_SIZE(NV_PGC6) <= RM_PAGE_SIZE); + vAddr = osMapKernelSpace(bar0BaseAddr + DEVICE_BASE(NV_PGC6), + RM_PAGE_SIZE, NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + if (vAddr == NULL) + { + return NV_FALSE; + } + + while (timeUs < GPU_GFW_BOOT_COMPLETION_TIMEOUT_US) + { + bGfwBootCompleted = _gpuIsGfwBootCompleted_TU102(NULL, vAddr, &gfwBootProgressVal); + if (bGfwBootCompleted) + { + break; + } + + osDelayUs(1000); + timeUs += 1000; + } + + osUnmapKernelSpace(vAddr, RM_PAGE_SIZE); + if (!bGfwBootCompleted) + { + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: (progress 0x%x)\n", + gfwBootProgressVal); + return NV_FALSE; + } + + vAddr = osMapKernelSpace(bar0BaseAddr + DEVICE_BASE(NV_PCFG) + + NV_XVE_PRIV_MISC_1, 4, NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + if (vAddr == NULL) + { + return NV_FALSE; + } + + regVal = MEM_RD32(vAddr); + osUnmapKernelSpace(vAddr, 4); + + return FLD_TEST_DRF(_XVE, _PRIV_MISC_1, _CYA_HIDE_MSIX_CAP, _FALSE, regVal); +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c index b3c791ced..a73016394 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c @@ -31,7 +31,9 @@ #include "ctrl/ctrl2080/ctrl2080bus.h" #include "published/hopper/gh100/dev_fb.h" +#include "published/hopper/gh100/hwproject.h" #include "published/hopper/gh100/dev_xtl_ep_pri.h" +#include "published/hopper/gh100/dev_nv_xpl.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/hwproject.h" @@ -870,3 +872,76 @@ kbifCacheVFInfo_GH100 pGpu->sriovState.b64bitVFBar2 = barIs64Bit; } +NvU32 +kbifGetEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 regVal; + NvU32 count = 0; + + // PCIE RBUF + regVal = GPU_REG_RD32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_RBUF); + count += DRF_VAL(_XPL_DL, _ERR_COUNT_RBUF, _UNCORR_ERR, regVal); + + // PCIE SEQ_LUT + regVal = GPU_REG_RD32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_SEQ_LUT); + count += DRF_VAL(_XPL_DL, _ERR_COUNT_SEQ_LUT, _UNCORR_ERR, regVal); + + // PCIE XTL + regVal = GPU_REG_RD32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS); + if (regVal != 0) + { + count += 1; + } + + // PCIE XTL + regVal = GPU_REG_RD32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS); + if (regVal != 0) + { + count += 1; + } + + return count; +} + +NV_STATUS +kbifClearEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + NvU32 regVal; + + // Reset XTL-EP status registers + GPU_REG_WR32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS, ~0); + GPU_REG_WR32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS, ~0); + + // Reset XPL-EP error counters + regVal = DRF_DEF(_XPL, _DL_ERR_RESET, _RBUF_UNCORR_ERR_COUNT, _PENDING) | + DRF_DEF(_XPL, _DL_ERR_RESET, _SEQ_LUT_UNCORR_ERR_COUNT, _PENDING); + GPU_REG_WR32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_RESET, regVal); + + // Wait for the error counter reset to complete + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + for (;;) + { + status = gpuCheckTimeout(pGpu, &timeout); + + regVal = GPU_REG_RD32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_RESET); + + if (FLD_TEST_DRF(_XPL, _DL_ERR_RESET, _RBUF_UNCORR_ERR_COUNT, _DONE, regVal) && + FLD_TEST_DRF(_XPL, _DL_ERR_RESET, _SEQ_LUT_UNCORR_ERR_COUNT, _DONE, regVal)) + break; + + if (status != NV_OK) + return status; + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c index 8710bb711..fb3cd807a 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c @@ -2608,3 +2608,36 @@ kbusGetEgmPeerId_GH100 return BUS_INVALID_PEER; } + +NvU32 +kbusGetEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 regVal; + NvU32 count = 0; + + // PCIE RE ORDER + regVal = GPU_REG_RD32(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT); + count += DRF_VAL(_XAL_EP, _REORDER_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // PCIE P2PREQ + regVal = GPU_REG_RD32(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT); + count += DRF_VAL(_XAL_EP, _P2PREQ_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + return count; +} + +void +kbusClearEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + // Reset XAL-EP counts + GPU_REG_WR32(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT, 0); + GPU_REG_WR32(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT, 0); +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index e207d0e57..ce54442e5 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -2334,6 +2334,8 @@ kbusUpdateRmAperture_GM107 { pFmt = pKernelBus->bar2[gfid].pFmt; + NV_CHECK_OR_RETURN(LEVEL_ERROR, pFmt != NULL, NV_ERR_INVALID_ARGUMENT); + // MMU_MAP_CTX mapTarget.pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, BIT_IDX_64(pageSize)); diff --git a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c index a5ebeec8c..3949a7eab 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c @@ -45,6 +45,7 @@ #define NV_CE_NUM_FBPCE 4 #define NV_CE_NUM_PCES_NO_LINK_CASE 12 #define NV_CE_MAX_PCE_PER_GRCE 2 +#define NV_CE_HSHUBNVL_ID_0 2 /* * Table for setting the PCE2LCE mapping for WAR configs that cannot be implemented @@ -931,3 +932,204 @@ kceGetMappings_GH100 NV_PRINTF(LEVEL_INFO, "status = %d, statusC2C = %d\n", status, statusC2C); return NV_OK; } + +NV_STATUS kceGetP2PCes_GH100(KernelCE *pKCe, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) +{ + // + // Currently Bug 4103154 requires an updated algorithm described below + // to assign the proper LCE. Cases without MODS enabled can default back + // to the previous version. + // + return kceGetP2PCes_GV100(pKCe, pGpu, gpuMask, nvlinkP2PCeMask); + + NvU32 gpuCount = gpumgrGetSubDeviceCount(gpuMask); + NvU32 minP2PLce = (NV_CE_EVEN_ASYNC_LCE_MASK | NV_CE_ODD_ASYNC_LCE_MASK) & NV_CE_MAX_LCE_MASK; + NvU32 i; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + if (pKernelNvlink == NULL) + { + return NV_WARN_NOTHING_TO_DO; + } + + if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + return kceGetP2PCes_GV100(pKCe, pGpu, gpuMask, nvlinkP2PCeMask); + } + + LOWESTBITIDX_32(minP2PLce); + *nvlinkP2PCeMask = 0; + + if (gpuCount == 1) + { + *nvlinkP2PCeMask |= NVBIT(minP2PLce); + for (i = minP2PLce; i < gpuGetNumCEs(pGpu); i++) + { + *nvlinkP2PCeMask |= NVBIT(i); + + } + } + else if (gpuCount > 2) + { + // if gpuCount > 2, this is an invalid request. Print warning and return NV_OK + NV_PRINTF(LEVEL_INFO, "GPU %d invalid request for gpuCount %d\n", gpuGetInstance(pGpu), gpuCount); + return NV_ERR_INVALID_STATE; + } + else + { + OBJGPU *pRemoteGpu = NULL; + KernelCE *pKCeLoop = NULL; + NvU32 peerLinkMask = 0; + NvU32 gpuInstance = 0; + NvU32 phyLinkId, status, targetPceMask, numPces; + + // + // The LCE returned should be the LCE which has the most PCEs mapped + // on the given HSHUB. This HSHUB should be determined by + // tracking where the majority of links are connected. + // + NvU32 linksPerHshub[NV_CE_MAX_HSHUBS] = {0}; + NvU32 maxLinksConnectedHshub = 0; + NvU32 maxConnectedHshubId = NV_CE_MAX_HSHUBS; + NvU32 lceAssignedMask = 0; + KernelCE *maxLcePerHshub[NV_CE_MAX_HSHUBS] = {0}; + + NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS params; + + if (pKernelNvlink != NULL) + { + // Get the remote GPU + while ((pRemoteGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (pRemoteGpu != pGpu) + break; + } + + NV_ASSERT_OR_RETURN(pRemoteGpu != NULL, NV_ERR_INVALID_STATE); + gpuInstance = gpuGetInstance(pRemoteGpu); + + peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); + } + + portMemSet(¶ms, 0, sizeof(params)); + params.linkMask = peerLinkMask; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS, + (void *)¶ms, sizeof(params)); + NV_ASSERT_OK_OR_RETURN(status); + + + FOR_EACH_INDEX_IN_MASK(32, phyLinkId, peerLinkMask) + { + NvU32 hshubId = params.hshubIds[phyLinkId]; + linksPerHshub[hshubId]++; + + if (linksPerHshub[hshubId] > maxLinksConnectedHshub) + { + maxLinksConnectedHshub = linksPerHshub[hshubId]; + maxConnectedHshubId = hshubId; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // + // Iterate through all Async LCEs to track which HSHUB should + // be using which LCE. This is decided based on the majority. If + // there is a tie, then LCE with the lower index is preferred. + // + KCE_ITER_ALL_BEGIN(pGpu, pKCeLoop, minP2PLce) + NvU32 localMaxPcePerHshub = 0; + KernelCE *localMaxLcePerHshub; + NvU32 localMaxHshub = NV_CE_MAX_HSHUBS; + + // if LCE is stubbed or LCE is already assigned to another peer + if (pKCeLoop->bStubbed) + { + continue; + } + + // LCE is already assigned to this peer + if ((pKCeLoop->nvlinkPeerMask & NVBIT(gpuInstance)) != 0) + { + maxLcePerHshub[maxConnectedHshubId] = pKCeLoop; + break; + } + // LCE is already assigned to another peer + else if (pKCeLoop->nvlinkPeerMask != 0) + { + continue; + } + + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS params = {0}; + + params.ceEngineType = NV2080_ENGINE_TYPE_COPY(pKCeLoop->publicID); + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK, + (void *)¶ms, sizeof(params)); + NV_ASSERT_OK_OR_RETURN(status); + + // + // An LCE may be utilized across several HSHUBs. Loop through all HSHUBs + // in order to decide which HSHUB holds the majority of this specific LCE. + // To help with this, create a mask of PCEs only on the HSHUB which the peer + // is most connected to by shifting the HSHUB PCE mask + // + + for (i = NV_CE_HSHUBNVL_ID_0; i < NV_CE_MAX_HSHUBS; i++) + { + targetPceMask = params.pceMask & ((NVBIT(NV_CE_PCE_PER_HSHUB) - 1) << ((i - NV_CE_HSHUBNVL_ID_0) * NV_CE_PCE_PER_HSHUB)); + numPces = nvPopCount32(targetPceMask); + if (numPces > localMaxPcePerHshub && !(lceAssignedMask & NVBIT(pKCeLoop->publicID))) + { + localMaxPcePerHshub = numPces; + localMaxLcePerHshub = pKCeLoop; + localMaxHshub = i; + } + } + + if (localMaxHshub < NV_CE_MAX_HSHUBS) + { + maxLcePerHshub[localMaxHshub] = localMaxLcePerHshub; + lceAssignedMask |= NVBIT(localMaxLcePerHshub->publicID); + } + + KCE_ITER_END + + if (maxLcePerHshub[maxConnectedHshubId] != NULL) + { + NV_PRINTF(LEVEL_INFO, + "GPU %d Assigning Peer %d to preferred LCE %d\n", + gpuGetInstance(pGpu), gpuInstance, + maxLcePerHshub[maxConnectedHshubId]->publicID); + } + else + { + // + // In the event that the preferred HSHUB's primary LCE is not available, + // choose the first available LCE which was found and set that index as + // the new preferred hshub. + // + for (i = 0; i < NV_CE_MAX_HSHUBS; i++) + { + if (maxLcePerHshub[i] != NULL) + { + NV_PRINTF(LEVEL_INFO, + "GPU %d Assigning Peer %d to first available LCE %d\n", + gpuGetInstance(pGpu), gpuInstance, + maxLcePerHshub[i]->publicID); + maxConnectedHshubId = i; + break; + } + } + } + + if (maxConnectedHshubId < NV_CE_MAX_HSHUBS) + { + maxLcePerHshub[maxConnectedHshubId]->nvlinkPeerMask = NVBIT(gpuInstance); + *nvlinkP2PCeMask = NVBIT(maxLcePerHshub[maxConnectedHshubId]->publicID); + } + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c index 336660fa3..374536ceb 100644 --- a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c +++ b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c @@ -51,6 +51,9 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU32 data = 0; + NvBool bForceEnableCC = 0; pConfCompute->pSpdm = NULL; portMemSet(&pConfCompute->ccStaticInfo, 0, sizeof(pConfCompute->ccStaticInfo)); pConfCompute->gspProxyRegkeys = 0; @@ -74,6 +77,20 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) { + bForceEnableCC = (osReadRegistryDword(pGpu, NV_REG_STR_RM_CONFIDENTIAL_COMPUTE, &data) == NV_OK) && + FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _ENABLED, _YES, data); + + if (!RMCFG_FEATURE_PLATFORM_GSP && !RMCFG_FEATURE_PLATFORM_MODS && !bForceEnableCC) + { + if (!(sysGetStaticConfig(pSys)->bOsCCEnabled)) + { + NV_PRINTF(LEVEL_ERROR, "CPU does not support confidential compute.\n"); + NV_ASSERT(0); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED, NV_FALSE); + return NV_ERR_INVALID_OPERATION; + } + } + NV_CHECK_OR_RETURN(LEVEL_ERROR, confComputeIsGpuCcCapable_HAL(pGpu, pConfCompute), NV_ERR_INVALID_OPERATION); if (pGpu->getProperty(pGpu, PDB_PROP_GPU_APM_FEATURE_CAPABLE)) @@ -92,7 +109,7 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, } else { - NV_PRINTF(LEVEL_ERROR, "GPU does not support confidential compute"); + NV_PRINTF(LEVEL_ERROR, "GPU does not support confidential compute.\n"); NV_ASSERT(0); return NV_ERR_INVALID_OPERATION; } diff --git a/src/nvidia/src/kernel/gpu/deferred_api.c b/src/nvidia/src/kernel/gpu/deferred_api.c index 880fa7ddd..e3b03293b 100644 --- a/src/nvidia/src/kernel/gpu/deferred_api.c +++ b/src/nvidia/src/kernel/gpu/deferred_api.c @@ -660,7 +660,8 @@ _class5080DeferredApiV2 callContext.secInfo.pProcessToken = (void *)(NvU64) gfid; } - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(rmStatus, + resservSwapTlsCallContext(&pOldContext, &callContext), cleanup); rmStatus = serverControl_Prologue(&g_resServ, &rmCtrlParams, &access, &releaseFlags); @@ -680,7 +681,7 @@ _class5080DeferredApiV2 } } - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); rmStatus = serverControl_Epilogue(&g_resServ, &rmCtrlParams, access, &releaseFlags, rmStatus); } diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index 7b2730c8a..8ffcf73df 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -50,6 +50,8 @@ #include "kernel/gpu/intr/engine_idx.h" +#include "gpu/external_device/external_device.h" + #include "ctrl/ctrl2080.h" #include "class/cl5070.h" @@ -490,6 +492,8 @@ void kdispStateDestroy_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay) { + extdevDestroy(pGpu); + if (pKernelDisplay->pInst != NULL) { instmemStateDestroy(pGpu, pKernelDisplay->pInst); diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c b/src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c index 377dcb7ad..323e9dd38 100644 --- a/src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c @@ -264,7 +264,7 @@ void *kcrashcatEngineMapBufferDescriptor_IMPL memdescMap(pMemDesc, 0, memdescGetSize(pMemDesc), NV_TRUE, NV_PROTECT_READABLE, &pBuf, &pPriv), { - if (pBufDesc->pEngPriv == NULL) + if (!pBufDesc->bRegistered) memdescDestroy(pMemDesc); return NULL; }); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c index 3cbdd2a34..d3d52fddd 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c @@ -419,18 +419,21 @@ kchangrpDestroy_IMPL kfifoChannelListDestroy(pGpu, pKernelFifo, pKernelChannelGroup->pChanList); pKernelChannelGroup->pChanList= NULL; - // Remove this from the <grIPD, PCHGRP> that we maintain in OBJFIFO - pKernelChannelGroupTemp = mapFind(pChidMgr->pChanGrpTree, pKernelChannelGroup->grpID); - if (pKernelChannelGroupTemp == NULL) + if (pChidMgr != NULL) { - NV_PRINTF(LEVEL_ERROR, "Could not find channel group %d\n", - pKernelChannelGroup->grpID); - return NV_ERR_OBJECT_NOT_FOUND; - } - mapRemove(pChidMgr->pChanGrpTree, pKernelChannelGroupTemp); + // Remove this from the <grIPD, PCHGRP> that we maintain in OBJFIFO + pKernelChannelGroupTemp = mapFind(pChidMgr->pChanGrpTree, pKernelChannelGroup->grpID); + if (pKernelChannelGroupTemp == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Could not find channel group %d\n", + pKernelChannelGroup->grpID); + return NV_ERR_OBJECT_NOT_FOUND; + } + mapRemove(pChidMgr->pChanGrpTree, pKernelChannelGroupTemp); - // Release the free grpID - kfifoChidMgrFreeChannelGroupHwID(pGpu, pKernelFifo, pChidMgr, pKernelChannelGroup->grpID); + // Release the free grpID + kfifoChidMgrFreeChannelGroupHwID(pGpu, pKernelFifo, pChidMgr, pKernelChannelGroup->grpID); + } // // Free the method buffer if applicable diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c index ebf2b98fc..74954472a 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c @@ -28,6 +28,7 @@ #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/falcon/kernel_falcon.h" +#include "kernel/gpu/rc/kernel_rc.h" #include "kernel/gpu/conf_compute/conf_compute.h" @@ -242,13 +243,28 @@ kchangrpapiConstruct_IMPL if (!RMCFG_FEATURE_PLATFORM_GSP) { - NV_ASSERT_OK_OR_GOTO(rmStatus, - ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pCtxBufPool), - failed); + NvHandle hRcWatchdog; - NV_ASSERT_OK_OR_GOTO(rmStatus, - ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pChannelBufPool), - failed); + // + // WAR for 4217716 - Force allocations made on behalf of watchdog client to + // RM reserved heap. This avoids a constant memory allocation from appearing + // due to the ctxBufPool reservation out of PMA. + // + rmStatus = krcWatchdogGetClientHandle(GPU_GET_KERNEL_RC(pGpu), &hRcWatchdog); + if ((rmStatus != NV_OK) || (pParams->hClient != hRcWatchdog)) + { + NV_ASSERT_OK_OR_GOTO(rmStatus, + ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pCtxBufPool), + failed); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pChannelBufPool), + failed); + } + else + { + NV_PRINTF(LEVEL_INFO, "Skipping ctxBufPoolInit for RC watchdog\n"); + } } NV_ASSERT_OK_OR_GOTO(rmStatus, diff --git a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c index de030bafa..2e8c2edf3 100644 --- a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c @@ -41,6 +41,7 @@ #include "published/hopper/gh100/dev_therm_addendum.h" #include "os/os.h" #include "nvRmReg.h" +#include "nverror.h" #include "gpu/conf_compute/conf_compute.h" @@ -622,9 +623,13 @@ kfspWaitForSecureBoot_GH100 status = gpuCheckTimeout(pGpu, &timeout); if (status == NV_ERR_TIMEOUT) { - NV_PRINTF(LEVEL_ERROR, - "Timout while polling for FSP boot complete I2CS_SCRATCH : %x\n", - GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE)); + NV_ERROR_LOG((void*) pGpu, GPU_INIT_ERROR, "Timeout while polling for FSP boot complete, " + "0x%x, 0x%x, 0x%x, 0x%x, 0x%x", + GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(2)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(3))); break; } } @@ -844,7 +849,7 @@ kfspSetupGspImages pGspImageMapSize = NV_ALIGN_UP(pGspImageSize, 0x1000); status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags); + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); status = memdescAlloc(pKernelFsp->pGspFmcMemdesc); @@ -1097,7 +1102,7 @@ kfspSendBootCommands_GH100 // flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags); + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); status = memdescAlloc(pKernelFsp->pSysmemFrtsMemdesc); diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index a8d164fc5..6194d4c55 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -618,7 +618,7 @@ static NV_STATUS _gpuRmApiControl callCtx.pControlParams = &rmCtrlParams; callCtx.pLockInfo = rmCtrlParams.pLockInfo; - resservSwapTlsCallContext(&oldCtx, &callCtx); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&oldCtx, &callCtx)); if (pEntry->paramSize == 0) { @@ -629,7 +629,7 @@ static NV_STATUS _gpuRmApiControl status = ((NV_STATUS(*)(void*,void*))pEntry->pFunc)(pGpu->pCachedSubdevice, pParams); } - resservRestoreTlsCallContext(oldCtx); + NV_ASSERT_OK(resservRestoreTlsCallContext(oldCtx)); } else { @@ -1411,6 +1411,15 @@ gpuDestruct_IMPL memdescFree(pGpu->userSharedData.pMemDesc); memdescDestroy(pGpu->userSharedData.pMemDesc); + // + // If device instance is unassigned, we haven't initialized far enough to + // do any accounting with it + // + if (gpuGetDeviceInstance(pGpu) != NV_MAX_DEVICES) + { + rmapiReportLeakedDevices(gpuGetGpuMask(pGpu)); + } + // Free children in reverse order from construction for (typeNum = GPU_NUM_CHILD_TYPES - 1; typeNum >= 0; typeNum--) { @@ -1431,15 +1440,6 @@ gpuDestruct_IMPL } } - // - // If device instance is unassigned, we haven't initialized far enough to - // do any accounting with it - // - if (gpuGetDeviceInstance(pGpu) != NV_MAX_DEVICES) - { - rmapiReportLeakedDevices(gpuGetGpuMask(pGpu)); - } - _gpuFreeEngineOrderList(pGpu); portMemFree(pGpu->pUserRegisterAccessMap); @@ -4936,17 +4936,27 @@ gpuReadBusConfigCycle_IMPL NvU32 *pData ) { - NvU32 domain = gpuGetDomain(pGpu); - NvU8 bus = gpuGetBus(pGpu); - NvU8 device = gpuGetDevice(pGpu); - NvU8 function = 0; + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU8 function = 0; + NvBool bIsCCFeatureEnabled = NV_FALSE; - if (pGpu->hPci == NULL) + bIsCCFeatureEnabled = gpuIsCCFeatureEnabled(pGpu); + + if (IS_PASSTHRU(pGpu) && !bIsCCFeatureEnabled) { - pGpu->hPci = osPciInitHandle(domain, bus, device, function, NULL, NULL); + gpuReadVgpuConfigReg_HAL(pGpu, index, pData); } + else + { + if (pGpu->hPci == NULL) + { + pGpu->hPci = osPciInitHandle(domain, bus, device, function, NULL, NULL); + } - *pData = osPciReadDword(pGpu->hPci, index); + *pData = osPciReadDword(pGpu->hPci, index); + } return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/gpu_resource.c b/src/nvidia/src/kernel/gpu/gpu_resource.c index dc0f35837..05f19bc89 100644 --- a/src/nvidia/src/kernel/gpu/gpu_resource.c +++ b/src/nvidia/src/kernel/gpu/gpu_resource.c @@ -381,6 +381,7 @@ gpuresControl_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { + NV_ASSERT_OR_RETURN(pGpuResource->pGpu != NULL, NV_ERR_INVALID_STATE); gpuresControlSetup(pParams, pGpuResource); return resControl_IMPL(staticCast(pGpuResource, RsResource), diff --git a/src/nvidia/src/kernel/gpu/gpu_rmapi.c b/src/nvidia/src/kernel/gpu/gpu_rmapi.c index cdafd2c6f..f61b55353 100644 --- a/src/nvidia/src/kernel/gpu/gpu_rmapi.c +++ b/src/nvidia/src/kernel/gpu/gpu_rmapi.c @@ -647,6 +647,20 @@ _gpuiIsPidSavedAlready return NV_FALSE; } +static NV_STATUS +_gpuConvertPid +( + RmClient *pClient, + NvU32 *pNsPid +) +{ + if (pClient->pOsPidInfo != NULL) + return osFindNsPid(pClient->pOsPidInfo, pNsPid); + + *pNsPid = pClient->ProcID; + return NV_OK; +} + // // Searches through clients to find processes with clients that have // allocated an ElementType of class, defined by elementID. The return values @@ -673,6 +687,7 @@ gpuGetProcWithObject_IMPL RmClient *pClient; RsClient *pRsClient; RsResourceRef *pResourceRef; + NV_STATUS status; NV_ASSERT_OR_RETURN((pPidArray != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((pPidArrayCount != NULL), NV_ERR_INVALID_ARGUMENT); @@ -782,8 +797,15 @@ gpuGetProcWithObject_IMPL } if (elementInClient) { - pPidArray[pidcount] = pClient->ProcID; - pidcount++; + status = _gpuConvertPid(pClient, &pPidArray[pidcount]); + if (status == NV_OK) + { + pidcount++; + } + else if (status != NV_ERR_OBJECT_NOT_FOUND) + { + return status; + } if (pidcount == NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT) { diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c index 410024afc..6d7260413 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c @@ -1732,8 +1732,9 @@ kgraphicsCreateGoldenImageChannel_IMPL NvU32 classNum; MIG_INSTANCE_REF ref; NvU32 objectType; + NvU32 primarySliSubDeviceInstance; - // XXX This should be removed when braodcast SLI support is deprecated + // XXX This should be removed when broadcast SLI support is deprecated if (!gpumgrIsParentGPU(pGpu)) { return NV_OK; @@ -1744,6 +1745,8 @@ kgraphicsCreateGoldenImageChannel_IMPL // FIXME these allocations corrupt BC state NV_ASSERT_OK_OR_RETURN( rmapiutilAllocClientAndDeviceHandles(pRmApi, pGpu, &hClientId, &hDeviceId, &hSubdeviceId)); + // rmapiutilAllocClientAndDeviceHandles allocates a subdevice object for this subDeviceInstance + primarySliSubDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClientId, &pClientId)); @@ -1759,6 +1762,11 @@ kgraphicsCreateGoldenImageChannel_IMPL { NvHandle hSecondary; NV2080_ALLOC_PARAMETERS nv2080AllocParams; + NvU32 thisSubDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + // Skip if already allocated by rmapiutilAllocClientAndDeviceHandles() + if (thisSubDeviceInstance == primarySliSubDeviceInstance) + SLI_LOOP_CONTINUE; // Allocate a subDevice NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -1766,7 +1774,7 @@ kgraphicsCreateGoldenImageChannel_IMPL cleanup); portMemSet(&nv2080AllocParams, 0, sizeof(nv2080AllocParams)); - nv2080AllocParams.subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + nv2080AllocParams.subDeviceId = thisSubDeviceInstance; NV_CHECK_OK(status, LEVEL_WARNING, pRmApi->AllocWithHandle(pRmApi, diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c index 39b0beb06..5a33f6df5 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c @@ -63,20 +63,19 @@ kgspConfigureFalcon_GA102 falconConfig.bIsPmcDeviceEngine = NV_FALSE; falconConfig.physEngDesc = ENG_GSP; - // Enable CrashCat monitoring - falconConfig.crashcatEngConfig.bEnable = NV_TRUE; - falconConfig.crashcatEngConfig.pName = MAKE_NV_PRINTF_STR("GSP"); - falconConfig.crashcatEngConfig.errorId = GSP_ERROR; ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); - if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) - { - // No CrashCat queue when CC is enabled, as it's not encrypted - falconConfig.crashcatEngConfig.allocQueueSize = 0; - } - else + + // + // No CrashCat queue when CC is enabled, as it's not encrypted. + // Don't bother enabling the host-side decoding either. + // + if (pCC == NULL || !pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) { - falconConfig.crashcatEngConfig.allocQueueSize = RM_PAGE_SIZE; + // Enable CrashCat monitoring + falconConfig.crashcatEngConfig.bEnable = NV_TRUE; + falconConfig.crashcatEngConfig.pName = MAKE_NV_PRINTF_STR("GSP"); + falconConfig.crashcatEngConfig.errorId = GSP_ERROR; } kflcnConfigureEngine(pGpu, staticCast(pKernelGsp, KernelFalcon), &falconConfig); diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c index 1064e84af..d4a152145 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c @@ -29,6 +29,7 @@ #include "gpu/conf_compute/conf_compute.h" #include "gpu/fsp/kern_fsp.h" #include "gpu/gsp/kernel_gsp.h" +#include "gpu/mem_sys/kern_mem_sys.h" #include "gsp/gspifpub.h" #include "vgpu/rpc.h" @@ -532,8 +533,16 @@ kgspBootstrapRiscvOSEarly_GH100 return NV_ERR_NOT_SUPPORTED; } + // Clear ECC errors before attempting to load GSP + status = gpuClearEccCounts_HAL(pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Issue clearing ECC counts! Status:0x%x\n", status); + } + // Setup the descriptors that GSP-FMC needs to boot GSP-RM - NV_ASSERT_OK_OR_RETURN(kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw)); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw), exit); kgspSetupLibosInitArgs(pGpu, pKernelGsp); @@ -562,7 +571,8 @@ kgspBootstrapRiscvOSEarly_GH100 { NV_PRINTF(LEVEL_NOTICE, "Starting to boot GSP via FSP.\n"); pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM, NV_TRUE); - NV_ASSERT_OK_OR_RETURN(kfspSendBootCommands_HAL(pGpu, pKernelFsp)); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kfspSendBootCommands_HAL(pGpu, pKernelFsp), exit); } else { @@ -585,7 +595,7 @@ kgspBootstrapRiscvOSEarly_GH100 kfspDumpDebugState_HAL(pGpu, pKernelFsp); } - return status; + goto exit; } } @@ -606,7 +616,7 @@ kgspBootstrapRiscvOSEarly_GH100 kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0)); NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_MAILBOX1 = 0x%x\n", kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1)); - return status; + goto exit; } // Start polling for libos logs now that lockdown is released @@ -640,6 +650,11 @@ kgspBootstrapRiscvOSEarly_GH100 NV_PRINTF(LEVEL_INFO, "GSP FW RM ready.\n"); exit: + // If GSP fails to boot, check if there's any DED error. + if (status != NV_OK) + { + gpuCheckEccCounts_HAL(pGpu); + } NV_ASSERT(status == NV_OK); return status; diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c index 11baf3fe7..e2c6d8c1e 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c @@ -788,18 +788,14 @@ kgspHealthCheck_TU102 { bHealthy = NV_FALSE; - pKernelGsp->bFatalError = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, "****************************** GSP-CrashCat Report *******************************\n"); crashcatReportLog(pReport); - NV_PRINTF(LEVEL_ERROR, - "**********************************************************************************\n"); objDelete(pReport); } - return bHealthy; + goto exit_health_check; } NvU32 mb0 = GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)); @@ -812,9 +808,8 @@ kgspHealthCheck_TU102 { NvU32 mb1 = GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(1)); NvU32 skipped = DRF_VAL(_GSP, _ERROR, _SKIPPED, mb0); - bHealthy = NV_FALSE; - pKernelGsp->bFatalError = NV_TRUE; + bHealthy = NV_FALSE; // Clear the mailbox GPU_REG_WR32(pGpu, NV_PGSP_MAILBOX(0), 0); @@ -822,14 +817,8 @@ kgspHealthCheck_TU102 NV_PRINTF(LEVEL_ERROR, "********************************* GSP Failure **********************************\n"); - nvErrorLog_va((void*)pGpu, GSP_ERROR, - "GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x. The GPU likely needs to be reset.", - DRF_VAL(_GSP, _ERROR, _TASK, mb0), - DRF_VAL(_GSP, _ERROR, _CODE, mb0), - DRF_VAL(_GSP, _ERROR, _REASON, mb0), - mb1); - NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, NV_PRINTF_ADD_PREFIX - ("GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x"), + NV_ERROR_LOG(pGpu, GSP_ERROR, + "GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x. The GPU likely needs to be reset.", DRF_VAL(_GSP, _ERROR, _TASK, mb0), DRF_VAL(_GSP, _ERROR, _CODE, mb0), DRF_VAL(_GSP, _ERROR, _REASON, mb0), @@ -840,11 +829,21 @@ kgspHealthCheck_TU102 { NV_PRINTF(LEVEL_ERROR, "%d more errors skipped\n", skipped); } + } + +exit_health_check: + if (!bHealthy) + { + pKernelGsp->bFatalError = NV_TRUE; + + if (pKernelGsp->pRpc) + kgspLogRpcDebugInfo(pGpu, pKernelGsp->pRpc, GSP_ERROR, pKernelGsp->bPollingForRpcResponse); + + gpuCheckEccCounts_HAL(pGpu); NV_PRINTF(LEVEL_ERROR, - "********************************************************************************\n"); + "**********************************************************************************\n"); } - return bHealthy; } @@ -957,9 +956,6 @@ kgspIsWpr2Up_TU102 return (wpr2HiVal != 0); } -#define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms -#define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s - NV_STATUS kgspWaitForGfwBootOk_TU102 ( @@ -967,51 +963,16 @@ kgspWaitForGfwBootOk_TU102 KernelGsp *pKernelGsp ) { - NvU32 timeoutUs = FWSECLIC_PROG_START_TIMEOUT + FWSECLIC_PROG_COMPLETE_TIMEOUT; - RMTIMEOUT timeout; NV_STATUS status = NV_OK; - // Use the OS timer since the GPU timer is not ready yet - gpuSetTimeout(pGpu, gpuScaleTimeout(pGpu, timeoutUs), &timeout, - GPU_TIMEOUT_FLAGS_OSTIMER); - - while (status == NV_OK) + status = gpuWaitForGfwBootComplete_HAL(pGpu); + if (status != NV_OK) { - // - // Before reading the actual GFW_BOOT status register, - // we want to check that FWSEC has lowered its PLM first. - // If not then obviously it has not completed. - // - if (GPU_FLD_TEST_DRF_DEF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK, - _READ_PROTECTION_LEVEL0, - _ENABLE) - ) - { - if (GPU_FLD_TEST_DRF_DEF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, - _PROGRESS, - _COMPLETED) - ) - { - return NV_OK; - } - } - - status = gpuCheckTimeout(pGpu, &timeout); + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW boot complete: 0x%x VBIOS version %s\n", + status, pKernelGsp->vbiosVersionStr); + NV_PRINTF(LEVEL_ERROR, "(the GPU may be in a bad state and may need to be reset)\n"); } - // The wait failed if we reach here (as above loop returns upon success). - NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: 0x%x (progress 0x%x, VBIOS version %s)\n", - status, GPU_REG_RD_DRF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, - _PROGRESS), - pKernelGsp->vbiosVersionStr); - NV_PRINTF(LEVEL_ERROR, "(the GPU may be in a bad state and may need to be reset)\n"); - return status; } @@ -1136,3 +1097,36 @@ exit_cleanup: kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); return nvStatus; } + +void +kgspReadEmem_TU102 +( + KernelGsp *pKernelGsp, + NvU64 offset, + NvU64 size, + void *pBuf +) +{ + NvU32 ememMask = DRF_SHIFTMASK(NV_PGSP_EMEMC_OFFS) | DRF_SHIFTMASK(NV_PGSP_EMEMC_BLK); + OBJGPU *pGpu = ENG_GET_GPU(pKernelGsp); + NvU32 limit = size - NVBIT(DRF_SHIFT(NV_PGSP_EMEMC_OFFS)); + NvU32 *pBuffer = pBuf; + + portMemSet(pBuf, 0, size); + +#if defined(DEBUG) || defined(DEVELOP) + NV_ASSERT_OR_RETURN_VOID((offset & ~ememMask) == 0); + NV_ASSERT_OR_RETURN_VOID(limit <= ememMask); + NV_ASSERT_OR_RETURN_VOID(offset + limit <= ememMask); +#else + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, (offset & ~ememMask) == 0); + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, limit <= ememMask); + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, offset + limit <= ememMask); +#endif + + GPU_REG_WR32(pGpu, NV_PGSP_EMEMC(pKernelGsp->ememPort), + offset | DRF_DEF(_PGSP, _EMEMC, _AINCR, _TRUE)); + + for (NvU32 idx = 0; idx < size / sizeof(NvU32); idx++) + pBuffer[idx] = GPU_REG_RD32(pGpu, NV_PGSP_EMEMD(pKernelGsp->ememPort)); +} diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index 654c54091..e60bd7661 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -143,12 +143,13 @@ _kgspGetActiveRpcDebugData ( OBJRPC *pRpc, NvU32 function, - NvU32 *data0, - NvU32 *data1 + NvU64 *data0, + NvU64 *data1 ) { switch (function) { + // Functions (CPU -> GSP) case NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: { RPC_PARAMS(gsp_rm_control, _v03_00); @@ -170,6 +171,36 @@ _kgspGetActiveRpcDebugData *data1 = rpc_params->params.hObjectParent; break; } + + // Events (CPU <- GSP) + case NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: + { + RPC_PARAMS(run_cpu_sequencer, _v17_00); + *data0 = rpc_params->cmdIndex; + *data1 = rpc_params->bufferSizeDWord; + break; + } + case NV_VGPU_MSG_EVENT_POST_EVENT: + { + RPC_PARAMS(post_event, _v17_00); + *data0 = rpc_params->notifyIndex; + *data1 = rpc_params->data; + break; + } + case NV_VGPU_MSG_EVENT_RC_TRIGGERED: + { + RPC_PARAMS(rc_triggered, _v17_02); + *data0 = rpc_params->nv2080EngineType; + *data1 = rpc_params->exceptType; + break; + } + case NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED: + { + RPC_PARAMS(vgpu_gsp_plugin_triggered, _v17_00); + *data0 = rpc_params->gfid; + *data1 = rpc_params->notifyIndex; + break; + } case NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: { RPC_PARAMS(gsp_lockdown_notice, _v17_00); @@ -177,6 +208,7 @@ _kgspGetActiveRpcDebugData *data1 = 0; break; } + default: { *data0 = 0; @@ -187,42 +219,98 @@ _kgspGetActiveRpcDebugData } static NV_STATUS -_kgspRpcSanityCheck(OBJGPU *pGpu) +_kgspRpcSanityCheck(OBJGPU *pGpu, KernelGsp *pKernelGsp, OBJRPC *pRpc) { + if (pKernelGsp->bFatalError) + { + NV_PRINTF(LEVEL_INFO, "GSP crashed, skipping RPC\n"); + // + // In case of a fatal GSP error, if there was an outstanding RPC at the + // time, we should have already printed the error for that, so this is a + // new RPC call...from now on don't bother printing RPC errors anymore, + // as it can be too noisy and overrun logs. + // + pRpc->bQuietPrints = NV_TRUE; + return NV_ERR_RESET_REQUIRED; + } if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU in reset, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU in reset, skipping RPC\n"); return NV_ERR_GPU_IN_FULLCHIP_RESET; } if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu) || pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST)) { - NV_PRINTF(LEVEL_INFO, - "GPU lost, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU lost, skipping RPC\n"); return NV_ERR_GPU_IS_LOST; } if (osIsGpuShutdown(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU shutdown, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU shutdown, skipping RPC\n"); return NV_ERR_GPU_IS_LOST; } if (!gpuIsGpuFullPowerForPmResume(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU not full power, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU not full power, skipping RPC\n"); return NV_ERR_GPU_NOT_FULL_POWER; } if (!gpuCheckSysmemAccess(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU has no sysmem access, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU has no sysmem access, skipping RPC\n"); return NV_ERR_INVALID_ACCESS_TYPE; } return NV_OK; } +static void +_kgspAddRpcHistoryEntry +( + OBJRPC *pRpc, + RpcHistoryEntry *pHistory, + NvU32 *pCurrent +) +{ + NvU32 func = RPC_HDR->function; + NvU32 entry; + + entry = *pCurrent = (*pCurrent + 1) % RPC_HISTORY_DEPTH; + + portMemSet(&pHistory[entry], 0, sizeof(pHistory[0])); + pHistory[entry].function = func; + pHistory[entry].ts_start = osGetTimestamp(); + + _kgspGetActiveRpcDebugData(pRpc, func, + &pHistory[entry].data[0], + &pHistory[entry].data[1]); +} + +static void +_kgspCompleteRpcHistoryEntry +( + RpcHistoryEntry *pHistory, + NvU32 current +) +{ + NvU32 historyIndex; + NvU32 historyEntry; + + pHistory[current].ts_end = osGetTimestamp(); + + // + // Complete any previous entries that aren't marked complete yet, using the same timestamp + // (we may not have explicitly waited for them) + // + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (current + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + if (pHistory[historyEntry].ts_start != 0 && + pHistory[historyEntry].ts_end == 0) + { + pHistory[historyEntry].ts_end = pHistory[current].ts_end; + } + } +} + /*! * GSP client RM RPC send routine */ @@ -238,7 +326,7 @@ _kgspRpcSendMessage NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, _kgspRpcSanityCheck(pGpu)); + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, _kgspRpcSanityCheck(pGpu, pKernelGsp, pRpc)); nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu); if (nvStatus != NV_OK) @@ -256,20 +344,7 @@ _kgspRpcSendMessage kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, pRpc->pMessageQueueInfo->queueIdx, 0); - // Add RPC history entry - { - NvU32 func = RPC_HDR->function; - NvU32 entry; - - entry = pRpc->rpcHistoryCurrent = (pRpc->rpcHistoryCurrent + 1) % RPC_HISTORY_DEPTH; - - portMemSet(&pRpc->rpcHistory[entry], 0, sizeof(pRpc->rpcHistory[0])); - pRpc->rpcHistory[entry].function = func; - - _kgspGetActiveRpcDebugData(pRpc, func, - &pRpc->rpcHistory[entry].data[0], - &pRpc->rpcHistory[entry].data[1]); - } + _kgspAddRpcHistoryEntry(pRpc, pRpc->rpcHistory, &pRpc->rpcHistoryCurrent); return NV_OK; } @@ -1075,7 +1150,7 @@ const char *_getRpcName /*! * GSP client process RPC events */ -static NV_STATUS +static void _kgspProcessRpcEvent ( OBJGPU *pGpu, @@ -1084,11 +1159,14 @@ _kgspProcessRpcEvent { rpc_message_header_v *pMsgHdr = RPC_HDR; NV_STATUS nvStatus = NV_OK; + NvU32 event = pMsgHdr->function; NV_PRINTF(LEVEL_INFO, "received event from GPU%d: 0x%x (%s) status: 0x%x size: %d\n", - gpuGetInstance(pGpu), pMsgHdr->function, _getRpcName(pMsgHdr->function), pMsgHdr->rpc_result, pMsgHdr->length); + gpuGetInstance(pGpu), event, _getRpcName(event), pMsgHdr->rpc_result, pMsgHdr->length); + + _kgspAddRpcHistoryEntry(pRpc, pRpc->rpcEventHistory, &pRpc->rpcEventHistoryCurrent); - switch(pMsgHdr->function) + switch(event) { case NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: nvStatus = _kgspRpcRunCpuSequencer(pGpu, pRpc); @@ -1205,17 +1283,29 @@ _kgspProcessRpcEvent case NV_VGPU_MSG_EVENT_GSP_INIT_DONE: // Handled by _kgspRpcRecvPoll. default: // + // Log, but otherwise ignore unexpected events. + // // We will get here if the previous RPC timed out. The response // eventually comes in as an unexpected event. The error handling - // for the timeout has already happened, and returning an error here - // causes subsequent messages to fail. So return NV_OK. + // for the timeout should have already happened. // NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event from GPU%d: 0x%x (%s)\n", - gpuGetInstance(pGpu), pMsgHdr->function, _getRpcName(pMsgHdr->function)); + gpuGetInstance(pGpu), event, _getRpcName(event)); break; } - return nvStatus; + if (nvStatus != NV_OK) + { + // + // Failing to properly handle a specific event does not mean we should stop + // processing events/RPCs, so print the error and soldier on. + // + NV_PRINTF(LEVEL_ERROR, + "Failed to process received event 0x%x (%s) from GPU%d: status=0x%x\n", + event, _getRpcName(event), gpuGetInstance(pGpu), nvStatus); + } + + _kgspCompleteRpcHistoryEntry(pRpc->rpcEventHistory, pRpc->rpcEventHistoryCurrent); } /*! @@ -1226,7 +1316,7 @@ _kgspProcessRpcEvent * NV_OK if the event is successfully handled. * NV_WARN_NOTHING_TO_DO if there are no events available. * NV_WARN_MORE_PROCESSING_REQUIRED if the event is expectedFunc: it is unhandled and in the staging area. - * (Another status) if event reading or processing fails. + * (Another status) if event reading fails. */ static NV_STATUS _kgspRpcDrainOneEvent @@ -1248,20 +1338,15 @@ _kgspRpcDrainOneEvent if (nvStatus == NV_OK) { rpc_message_header_v *pMsgHdr = RPC_HDR; + if (pMsgHdr->function == expectedFunc) return NV_WARN_MORE_PROCESSING_REQUIRED; - nvStatus = _kgspProcessRpcEvent(pGpu, pRpc); - if (nvStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to process received event 0x%x (%s) from GPU%d: status=0x%x\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function), gpuGetInstance(pGpu), nvStatus); - } + _kgspProcessRpcEvent(pGpu, pRpc); } // - // We don't expect the NV_WARN_MORE_PROCESSING_REQUIRED from either called function. + // We don't expect NV_WARN_MORE_PROCESSING_REQUIRED here. // If we get it we need to suppress it to avoid confusing our caller, for whom it has special meaning. // NV_ASSERT_OR_ELSE(nvStatus != NV_WARN_MORE_PROCESSING_REQUIRED, @@ -1299,7 +1384,7 @@ _kgspRpcDrainEvents kgspDumpGspLogs(pKernelGsp, NV_FALSE); } - // If GSP-RM has died, + // If GSP-RM has died, the GPU will need to be reset if (!kgspHealthCheck_HAL(pGpu, pKernelGsp)) return NV_ERR_RESET_REQUIRED; @@ -1309,6 +1394,165 @@ _kgspRpcDrainEvents return nvStatus; } +static NvU64 +_tsDiffToDuration +( + NvU64 duration, + char *pDurationUnitsChar +) +{ + const NvU64 tsFreqUs = osGetTimestampFreq() / 1000000; + + *pDurationUnitsChar = 'u'; + + NV_ASSERT_OR_RETURN(tsFreqUs > 0, 0); + + duration /= tsFreqUs; + + // 999999us then 1000ms + if (duration >= 1000000) + { + duration /= 1000; + *pDurationUnitsChar = 'm'; + } + + // 9999ms then 10s + if (duration >= 10000) + { + duration /= 1000; + *pDurationUnitsChar = ' '; // so caller can always just append 's' + } + + return duration; +} + +static NvBool +_kgspIsTimestampDuringRecentRpc +( + OBJRPC *pRpc, + NvU64 timestamp, + NvBool bCheckIncompleteRpcsOnly +) +{ + NvU32 historyIndex; + NvU32 historyEntry; + + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + if (pRpc->rpcHistory[historyEntry].function != 0) + { + if ((timestamp >= pRpc->rpcHistory[historyEntry].ts_start) && + ((pRpc->rpcHistory[historyEntry].ts_end == 0) || + (!bCheckIncompleteRpcsOnly && (timestamp <= pRpc->rpcHistory[historyEntry].ts_end)))) + { + return NV_TRUE; + } + } + } + + return NV_FALSE; +} + +static void +_kgspLogRpcHistoryEntry +( + OBJGPU *pGpu, + NvU32 errorNum, + NvU32 historyIndex, + RpcHistoryEntry *pEntry, + NvBool lastColumnCondition +) +{ + NvU64 duration; + char durationUnitsChar; + + if (pEntry->function != 0) + { + duration = (pEntry->ts_end > pEntry->ts_start) ? (pEntry->ts_end - pEntry->ts_start) : 0; + if (duration) + { + duration = _tsDiffToDuration(duration, &durationUnitsChar); + + NV_ERROR_LOG_DATA(pGpu, errorNum, + " %c%-4d %-4d %-21.21s 0x%016llx 0x%016llx 0x%016llx 0x%016llx %6llu%cs %c\n", + ((historyIndex == 0) ? ' ' : '-'), + historyIndex, + pEntry->function, + _getRpcName(pEntry->function), + pEntry->data[0], + pEntry->data[1], + pEntry->ts_start, + pEntry->ts_end, + duration, durationUnitsChar, + (lastColumnCondition ? 'y' : ' ')); + } + else + { + NV_ERROR_LOG_DATA(pGpu, errorNum, + " %c%-4d %-4d %-21.21s 0x%016llx 0x%016llx 0x%016llx 0x%016llx %c\n", + ((historyIndex == 0) ? ' ' : '-'), + historyIndex, + pEntry->function, + _getRpcName(pEntry->function), + pEntry->data[0], + pEntry->data[1], + pEntry->ts_start, + pEntry->ts_end, + (lastColumnCondition ? 'y' : ' ')); + } + } +} + +void +kgspLogRpcDebugInfo +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvU32 errorNum, + NvBool bPollingForRpcResponse +) +{ + const rpc_message_header_v *pMsgHdr = RPC_HDR; + NvU32 historyIndex; + NvU32 historyEntry; + NvU64 activeData[2]; + + _kgspGetActiveRpcDebugData(pRpc, pMsgHdr->function, + &activeData[0], &activeData[1]); + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d GSP RPC buffer contains function %d (%s) and data 0x%016llx 0x%016llx.\n", + gpuGetInstance(pGpu), + pMsgHdr->function, _getRpcName(pMsgHdr->function), + activeData[0], activeData[1]); + + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d RPC history (CPU -> GSP):\n", + gpuGetInstance(pGpu)); + NV_ERROR_LOG_DATA(pGpu, errorNum, + " entry function data0 data1 ts_start ts_end duration actively_polling\n"); + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + _kgspLogRpcHistoryEntry(pGpu, errorNum, historyIndex, &pRpc->rpcHistory[historyEntry], + ((historyIndex == 0) && bPollingForRpcResponse)); + } + + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d RPC event history (CPU <- GSP):\n", + gpuGetInstance(pGpu)); + NV_ERROR_LOG_DATA(pGpu, errorNum, + " entry function data0 data1 ts_start ts_end duration during_incomplete_rpc\n"); + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcEventHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + _kgspLogRpcHistoryEntry(pGpu, errorNum, historyIndex, &pRpc->rpcEventHistory[historyEntry], + _kgspIsTimestampDuringRecentRpc(pRpc, + pRpc->rpcEventHistory[historyEntry].ts_start, + NV_TRUE/*bCheckIncompleteRpcsOnly*/)); + } +} + /*! * Log Xid 119 - GSP RPC Timeout */ @@ -1320,65 +1564,36 @@ _kgspLogXid119 NvU32 expectedFunc ) { - NvU32 historyEntry = pRpc->rpcHistoryCurrent; + RpcHistoryEntry *pHistoryEntry = &pRpc->rpcHistory[pRpc->rpcHistoryCurrent]; + NvU64 ts_end = osGetTimestamp(); + NvU64 duration; + char durationUnitsChar; if (pRpc->timeoutCount == 1) { NV_PRINTF(LEVEL_ERROR, - "********************************* GSP Failure **********************************\n"); + "********************************* GSP Timeout **********************************\n"); + NV_PRINTF(LEVEL_ERROR, + "Note: Please also check logs above.\n"); } - NV_ASSERT(expectedFunc == pRpc->rpcHistory[historyEntry].function); + NV_ASSERT(expectedFunc == pHistoryEntry->function); + + NV_ASSERT(ts_end > pHistoryEntry->ts_start); + duration = _tsDiffToDuration(ts_end - pHistoryEntry->ts_start, &durationUnitsChar); - nvErrorLog_va((void*)pGpu, GSP_RPC_TIMEOUT, - "Timeout waiting for RPC from GSP%d! Expected function %d (%s) (0x%x 0x%x).", - gpuGetInstance(pGpu), - expectedFunc, - _getRpcName(expectedFunc), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, NV_PRINTF_ADD_PREFIX - ("Timeout waiting for RPC from GSP%d! Expected function %d (0x%x 0x%x)"), + NV_ERROR_LOG(pGpu, GSP_RPC_TIMEOUT, + "Timeout after %llus of waiting for RPC response from GPU%d GSP! Expected function %d (%s) (0x%x 0x%x).", + (durationUnitsChar == 'm' ? duration / 1000 : duration), gpuGetInstance(pGpu), expectedFunc, - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); + _getRpcName(expectedFunc), + pHistoryEntry->data[0], + pHistoryEntry->data[1]); if (pRpc->timeoutCount == 1) { - NvU32 activeData[2]; - NvU32 historyIndex; - rpc_message_header_v *pMsgHdr = RPC_HDR; - - _kgspGetActiveRpcDebugData(pRpc, pMsgHdr->function, - &activeData[0], &activeData[1]); - - if ((expectedFunc != pMsgHdr->function) || - (pRpc->rpcHistory[historyEntry].data[0] != activeData[0]) || - (pRpc->rpcHistory[historyEntry].data[1] != activeData[1])) - { - NV_PRINTF(LEVEL_ERROR, - "Current RPC function %d (%s) or data (0x%x 0x%x) does not match expected function %d (%s) or data (0x%x 0x%x).\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function), - activeData[0], activeData[1], - expectedFunc, _getRpcName(expectedFunc), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - } - - NV_PRINTF(LEVEL_ERROR, "RPC history (CPU -> GSP%d):\n", gpuGetInstance(pGpu)); - NV_PRINTF(LEVEL_ERROR, "\tentry\tfunc\t\t\t\tdata\n"); - for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) - { - historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; - NV_PRINTF(LEVEL_ERROR, "\t%c%-2d\t%2d %-22s\t0x%08x 0x%08x\n", - ((historyIndex == 0) ? ' ' : '-'), - historyIndex, - pRpc->rpcHistory[historyEntry].function, - _getRpcName(pRpc->rpcHistory[historyEntry].function), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - } + kgspLogRpcDebugInfo(pGpu, pRpc, GSP_RPC_TIMEOUT, NV_TRUE/*bPollingForRpcResponse*/); osAssertFailed(); @@ -1394,17 +1609,8 @@ _kgspRpcIncrementTimeoutCountAndRateLimitPrints OBJRPC *pRpc ) { - KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - pRpc->timeoutCount++; - if (pKernelGsp->bFatalError) - { - // in case of a fatal GSP error, don't bother printing RPC errors at all - pRpc->bQuietPrints = NV_TRUE; - return; - } - if ((pRpc->timeoutCount == (RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH + 1)) && (RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP > 0)) { @@ -1460,6 +1666,7 @@ _kgspRpcRecvPoll NV_ASSERT_OR_RETURN(!pKernelGsp->bPollingForRpcResponse, NV_ERR_INVALID_STATE); pKernelGsp->bPollingForRpcResponse = NV_TRUE; + // // GSP-RM init in emulation/simulation environment is extremely slow, // so need to increment timeout. // Apply the timeout extension to other RPCs as well, mostly so that @@ -1485,9 +1692,11 @@ _kgspRpcRecvPoll } else { + // // We should only ever timeout this when GSP is in really bad state, so if it just // happens to timeout on default timeout it should be OK for us to give it a little // more time - make this timeout 1.5 of the default to allow some leeway. + // timeoutUs = defaultus + defaultus / 2; } } @@ -1512,6 +1721,8 @@ _kgspRpcRecvPoll switch (rpcStatus) { case NV_WARN_MORE_PROCESSING_REQUIRED: + // The synchronous RPC response we were waiting for is here + _kgspCompleteRpcHistoryEntry(pRpc->rpcHistory, pRpc->rpcHistoryCurrent); rpcStatus = NV_OK; goto done; case NV_OK: @@ -1521,7 +1732,7 @@ _kgspRpcRecvPoll goto done; } - NV_CHECK_OK_OR_GOTO(rpcStatus, LEVEL_SILENT, _kgspRpcSanityCheck(pGpu), done); + NV_CHECK_OK_OR_GOTO(rpcStatus, LEVEL_SILENT, _kgspRpcSanityCheck(pGpu, pKernelGsp, pRpc), done); if (timeoutStatus == NV_ERR_TIMEOUT) { @@ -1642,7 +1853,10 @@ _kgspConstructRpcObject pRpc->pMessageQueueInfo = pMQI; portMemSet(&pRpc->rpcHistory, 0, sizeof(pRpc->rpcHistory)); - pRpc->rpcHistoryCurrent = RPC_HISTORY_DEPTH - 1; + pRpc->rpcHistoryCurrent = RPC_HISTORY_DEPTH - 1; + portMemSet(&pRpc->rpcEventHistory, 0, sizeof(pRpc->rpcEventHistory)); + pRpc->rpcEventHistoryCurrent = RPC_HISTORY_DEPTH - 1; + pRpc->message_buffer = (NvU32 *)pRpc->pMessageQueueInfo->pRpcMsgBuf; pRpc->maxRpcSize = GSP_MSG_QUEUE_RPC_SIZE_MAX; @@ -2438,7 +2652,8 @@ kgspInitRm_IMPL if (pKernelGsp->pLogElf == NULL) NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, nvlogRegisterFlushCb(kgspNvlogFlushCb, pKernelGsp), done); - // Wait for GFW_BOOT OK status + // Reset thread state timeout and wait for GFW_BOOT OK status + threadStateResetTimeout(pGpu); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp), done); // Fail early if WPR2 is up diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c index 514b5fd56..b2fed7ec2 100644 --- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c +++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c @@ -589,7 +589,9 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) if (pNextElement == NULL) { pMQI->txBufferFull++; - NV_PRINTF_COND(pMQI->txBufferFull == 1, LEVEL_ERROR, LEVEL_INFO, "buffer is full\n"); + NV_PRINTF_COND(pMQI->txBufferFull == 1, LEVEL_ERROR, LEVEL_INFO, + "buffer is full (waiting for %d free elements, got %d)\n", + pCQE->elemCount, i); nvStatus = NV_ERR_BUSY_RETRY; goto done; } diff --git a/src/nvidia/src/kernel/gpu/intr/intr.c b/src/nvidia/src/kernel/gpu/intr/intr.c index 0822a114f..6f9709659 100644 --- a/src/nvidia/src/kernel/gpu/intr/intr.c +++ b/src/nvidia/src/kernel/gpu/intr/intr.c @@ -1579,7 +1579,7 @@ intrServiceStallList_IMPL } } - resservSwapTlsCallContext(&pOldContext, NULL); + NV_ASSERT_OK_OR_ELSE(status, resservSwapTlsCallContext(&pOldContext, NULL), return); // prevent the isr from coming in _intrEnterCriticalSection(pGpu, pIntr, &intrMaskCtx); @@ -1608,7 +1608,7 @@ done: // allow the isr to come in. _intrExitCriticalSection(pGpu, pIntr, &intrMaskCtx); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c index 6b5001ea4..f1721e2be 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c @@ -36,6 +36,7 @@ #include "gpu/mem_mgr/ce_utils.h" #include "gpu/subdevice/subdevice.h" #include "kernel/gpu/mem_mgr/ce_utils_sizes.h" +#include "vgpu/rpc_headers.h" #include "class/clb0b5.h" // MAXWELL_DMA_COPY_A #include "class/clc0b5.h" // PASCAL_DMA_COPY_A @@ -91,8 +92,21 @@ ceutilsConstruct_IMPL status = serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient); NV_ASSERT_OR_GOTO(status == NV_OK, free_client); - status = clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U); - NV_ASSERT_OR_GOTO(status == NV_OK, free_client); + if (IS_VIRTUAL(pGpu)) + { + NV_ASSERT_OK_OR_GOTO( + status, + clientSetHandleGenerator(staticCast(pClient, RsClient), RS_UNIQUE_HANDLE_BASE, + RS_UNIQUE_HANDLE_RANGE/2 - VGPU_RESERVED_HANDLE_RANGE), + free_client); + } + else + { + NV_ASSERT_OK_OR_GOTO( + status, + clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U), + free_client); + } pChannel->bClientAllocated = NV_TRUE; pChannel->pGpu = pGpu; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c index c346fb23c..b29c75762 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c @@ -753,12 +753,6 @@ channelFillSec2Pb portMemCopy((void*)pBufScrub, SHA_256_HASH_SIZE_BYTE, (const void*)&hmacDigest[0], SHA_256_HASH_SIZE_BYTE); - if (methodIdx > SEC2_WL_METHOD_ARRAY_SIZE) - { - status = NV_ERR_INVALID_ARGUMENT; - goto cleanup; - } - for (NvU32 i = 0; i < methodIdx; i++) { NV_PUSH_INC_1U(RM_SUBCHANNEL, pMethods[i*2 + 0], pMethods[i*2 + 1]); @@ -786,12 +780,6 @@ channelFillSec2Pb portMemCopy((void*)pBufSema, SHA_256_HASH_SIZE_BYTE, (const void*)&hmacDigest[0], SHA_256_HASH_SIZE_BYTE); - if (methodIdx > SEC2_WL_METHOD_ARRAY_SIZE) - { - status = NV_ERR_INVALID_ARGUMENT; - goto cleanup; - } - for (NvU32 i = 0; i < methodIdx; i++) { NV_PUSH_INC_1U(RM_SUBCHANNEL, pMethods[i*2 + 0], pMethods[i*2 + 1]); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c index 22bdd35be..c1acc5358 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c @@ -481,19 +481,6 @@ memmgrStateLoad_IMPL memmgrScrubInit_HAL(pGpu, pMemoryManager); } - if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) - { - // - // NUMA onlined memory size should not exceed memory size assigned to PMA. - // TODO : Currently in selfhosted and P9+GV100 systems numaOnlined size is less - // than PMA Memory Size. Ideally both of them should be identical. Bug 4051320. - // - NvU64 pmaTotalMemorySize; - NvU64 numaOnlineSize = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->numaOnlineSize; - pmaGetTotalMemory(&GPU_GET_HEAP(pGpu)->pmaObject, &pmaTotalMemorySize); - NV_ASSERT_OR_RETURN(pmaTotalMemorySize >= numaOnlineSize, NV_ERR_INVALID_STATE); - } - // Dump FB regions memmgrDumpFbRegions(pGpu, pMemoryManager); @@ -1965,6 +1952,7 @@ memmgrSetPartitionableMem_IMPL { PMA_REGION_DESCRIPTOR *pFirstPmaRegionDesc = NULL; NvU32 numPmaRegions; + NvU32 pmaConfig = PMA_QUERY_NUMA_ONLINED; NV_ASSERT_OK_OR_RETURN(pmaGetRegionInfo(&pHeap->pmaObject, &numPmaRegions, &pFirstPmaRegionDesc)); @@ -1973,6 +1961,8 @@ memmgrSetPartitionableMem_IMPL pmaGetFreeMemory(&pHeap->pmaObject, &freeMem); pmaGetTotalMemory(&pHeap->pmaObject, &size); + NV_ASSERT_OK(pmaQueryConfigs(&pHeap->pmaObject, &pmaConfig)); + // // MIG won't be used alongside APM and hence the check below is of no use // Even if we enable the check for APM the check will fail given that after @@ -1983,8 +1973,11 @@ memmgrSetPartitionableMem_IMPL // channels are required to be in CPR vidmem. This changes the calculation below // We can ignore this for the non-MIG case. // - if (!gpuIsCCorApmFeatureEnabled(pGpu) || - IS_MIG_ENABLED(pGpu)) + // When FB memory is onlined as NUMA node, kernel can directly alloc FB memory + // and hence free memory can not be expected to be same as total memory. + // + if ((!gpuIsCCorApmFeatureEnabled(pGpu) || IS_MIG_ENABLED(pGpu)) && + !(pmaConfig & PMA_QUERY_NUMA_ONLINED)) { // // PMA should be completely free at this point, otherwise we risk @@ -2289,17 +2282,6 @@ memmgrAllocMIGGPUInstanceMemory_PF NvS32 numaNodeId; NvU64 partitionBaseAddr = pAddrRange->lo; NvU64 partitionSize = rangeLength(*pAddrRange); - NvU64 unalignedPartitionBaseAddr = partitionBaseAddr; - NvU64 memblockSize = 0; - - NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); - // - // Align the partition base and size to memblock size - // Some FB memory is wasted here if it is not already aligned. - // - partitionBaseAddr = NV_ALIGN_UP64(unalignedPartitionBaseAddr, memblockSize); - partitionSize -= (partitionBaseAddr - unalignedPartitionBaseAddr); - partitionSize = NV_ALIGN_DOWN64(partitionSize, memblockSize); if (kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager) == 0x0) { @@ -2873,6 +2855,7 @@ memmgrPmaRegisterRegions_IMPL NvU32 blPageIndex; NvU32 blackListCount; NvU64 base, size; + NvU64 pmaTotalMemorySize = 0; NV_STATUS status = NV_OK; const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); @@ -2965,6 +2948,7 @@ memmgrPmaRegisterRegions_IMPL } } + pmaTotalMemorySize += (pmaRegion.limit - pmaRegion.base + 1); NV_PRINTF(LEVEL_INFO, "Register FB region %llx..%llx of size %llx with PMA\n", pmaRegion.base, pmaRegion.limit, @@ -2990,6 +2974,18 @@ memmgrPmaRegisterRegions_IMPL pmaRegionIdx++; } + if (gpuIsSelfHosted(pGpu) && osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + // + // NUMA onlined memory size should not exceed memory size assigned to PMA. + // TODO : Currently in selfhosted and P9+GV100 systems numaOnlined size is less + // than PMA Memory Size. Ideally both of them should be identical. Bug 4051320. + // + NvU64 numaTotalSize = 0; + NvU64 numaFreeSize = 0; + osGetNumaMemoryUsage(pPma->numaNodeId, &numaFreeSize, &numaTotalSize); + NV_ASSERT_OR_RETURN(pmaTotalMemorySize >= numaTotalSize, NV_ERR_INVALID_STATE); + } // // bug #200354346, make sure the RM reserved region(s) are // scrubbed during the region creation itself. Top Down scrubber, diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c index a58d08a3d..eeca6bfc6 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c @@ -250,6 +250,44 @@ deviceCtrlCmdFbGetCapsV2_IMPL } // +// deviceCtrlCmdSetDefaultVidmemPhysicality +// +// Lock Requirements: +// Assert that API lock held on entry +// +NV_STATUS +deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL +( + Device *pDevice, + NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + NvU32 override; + + switch (pParams->value) + { + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT: + override = NVOS32_ATTR_PHYSICALITY_DEFAULT; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_CONTIGUOUS; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS; + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + pDevice->defaultVidmemPhysicalityOverride = override; + + return NV_OK; +} + +// // subdeviceCtrlCmdFbGetBar1Offset // // Lock Requirements: diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c index 7459d26fd..0ec5ec126 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c @@ -69,11 +69,13 @@ static NvU32 _scrubMemory(OBJMEMSCRUB *pScrubber, RmPhysAddr base, NvU64 size, NvU32 dstCpuCacheAttrib, NvU32 freeToken); static void _scrubWaitAndSave(OBJMEMSCRUB *pScrubber, PSCRUB_NODE pList, NvLength itemsToSave); static NvU64 _scrubGetFreeEntries(OBJMEMSCRUB *pScrubber); -static NvU64 _scrubCheckAndSubmit(OBJMEMSCRUB *pScrubber, NvU64 chunkSize, NvU64 *pPages, - NvU64 pageCount, PSCRUB_NODE pList, NvLength pagesToScrubCheck); +static NvU64 _scrubCheckAndSubmit(OBJMEMSCRUB *pScrubber, NvU64 pageCount, PSCRUB_NODE pList, + PSCRUB_NODE pScrubListCopy, NvLength pagesToScrubCheck); static void _scrubCopyListItems(OBJMEMSCRUB *pScrubber, PSCRUB_NODE pList, NvLength itemsToSave); static NV_STATUS _scrubCheckLocked(OBJMEMSCRUB *pScrubber, PSCRUB_NODE *ppList, NvU64 *pSize); +static NV_STATUS _scrubCombinePages(NvU64 *pPages, NvU64 pageSize, NvU64 pageCount, + PSCRUB_NODE *ppScrubList, NvU64 *pSize); /** * Constructs the memory scrubber object and signals @@ -403,63 +405,78 @@ scrubSubmitPages { NvU64 curPagesSaved = 0; PSCRUB_NODE pScrubList = NULL; + PSCRUB_NODE pScrubListCopy = NULL; + NvU64 scrubListSize = 0; NvLength pagesToScrubCheck = 0; NvU64 totalSubmitted = 0; NvU64 numFinished = 0; NvU64 freeEntriesInList = 0; NvU64 scrubCount = 0; - NvU64 numPagesToScrub = pageCount; + NvU64 numPagesToScrub = 0; NV_STATUS status = NV_OK; portSyncMutexAcquire(pScrubber->pScrubberMutex); *pSize = 0; *ppList = pScrubList; + NV_CHECK_OR_GOTO(LEVEL_INFO, pageCount > 0, cleanup); + NV_PRINTF(LEVEL_INFO, "submitting pages, pageCount = 0x%llx chunkSize = 0x%llx\n", pageCount, chunkSize); freeEntriesInList = _scrubGetFreeEntries(pScrubber); - if (freeEntriesInList < pageCount) + + NV_ASSERT_OK_OR_GOTO(status, + _scrubCombinePages(pPages, + chunkSize, + pageCount, + &pScrubList, + &scrubListSize), + cleanup); + + numPagesToScrub = scrubListSize; + + if (freeEntriesInList < scrubListSize) { - pScrubList = (PSCRUB_NODE) - portMemAllocNonPaged((NvLength)(sizeof(SCRUB_NODE) * (pageCount - freeEntriesInList))); + pScrubListCopy = (PSCRUB_NODE) + portMemAllocNonPaged((NvLength)(sizeof(SCRUB_NODE) * (scrubListSize - freeEntriesInList))); - if (pScrubList == NULL) + if (pScrubListCopy == NULL) { status = NV_ERR_NO_MEMORY; goto cleanup; } - while (freeEntriesInList < pageCount) + while (freeEntriesInList < scrubListSize) { - if (pageCount > MAX_SCRUB_ITEMS) + if (scrubListSize > MAX_SCRUB_ITEMS) { pagesToScrubCheck = (NvLength)(MAX_SCRUB_ITEMS - freeEntriesInList); scrubCount = MAX_SCRUB_ITEMS; } else { - pagesToScrubCheck = (NvLength)(pageCount - freeEntriesInList); - scrubCount = pageCount; + pagesToScrubCheck = (NvLength)(scrubListSize - freeEntriesInList); + scrubCount = scrubListSize; } - numFinished = _scrubCheckAndSubmit(pScrubber, chunkSize, &pPages[totalSubmitted], - scrubCount, &pScrubList[curPagesSaved], + numFinished = _scrubCheckAndSubmit(pScrubber, scrubCount, + &pScrubList[totalSubmitted], + &pScrubListCopy[curPagesSaved], pagesToScrubCheck); - pageCount -= numFinished; + scrubListSize -= numFinished; curPagesSaved += pagesToScrubCheck; totalSubmitted += numFinished; freeEntriesInList = _scrubGetFreeEntries(pScrubber); } - *ppList = pScrubList; + *ppList = pScrubListCopy; *pSize = curPagesSaved; } else { - totalSubmitted = _scrubCheckAndSubmit(pScrubber, chunkSize, pPages, - pageCount, NULL, - 0); + totalSubmitted = _scrubCheckAndSubmit(pScrubber, scrubListSize, + pScrubList, NULL, 0); *ppList = NULL; *pSize = 0; } @@ -467,6 +484,12 @@ scrubSubmitPages cleanup: portSyncMutexRelease(pScrubber->pScrubberMutex); + if (pScrubList != NULL) + { + portMemFree(pScrubList); + pScrubList = NULL; + } + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, status); if (totalSubmitted == numPagesToScrub) @@ -507,15 +530,33 @@ scrubWaitPages ) { - NvU32 iter = 0; - NV_STATUS status = NV_OK; + NvU32 iter = 0; + NV_STATUS status = NV_OK; + PSCRUB_NODE pScrubList = NULL; + NvU64 scrubListSize = 0; + + NV_ASSERT_OK_OR_RETURN(_scrubCombinePages(pPages, + chunkSize, + pageCount, + &pScrubList, + &scrubListSize)); portSyncMutexAcquire(pScrubber->pScrubberMutex); - for (iter = 0; iter < pageCount; iter++) + + for (iter = 0; iter < scrubListSize; iter++) { - _waitForPayload(pScrubber, pPages[iter], (pPages[iter] + chunkSize - 1)); + _waitForPayload(pScrubber, + pScrubList[iter].base, + (pScrubList[iter].base + pScrubList[iter].size - 1)); } portSyncMutexRelease(pScrubber->pScrubberMutex); + + if (pScrubList != NULL) + { + portMemFree(pScrubList); + pScrubList = NULL; + } + return status; } @@ -644,36 +685,35 @@ _scrubCopyListItems /* This function is used to check and submit work items always within the * available / maximum scrub list size. * - * @param[in] pScrubber OBJMEMSCRUB pointer - * @param[in] chunkSize size of each page - * @param[in] pPages Array of base address - * @param[in] pageCount number of pages in the array - * @param[in] pList pointer will store the return check array + * @param[in] pScrubber OBJMEMSCRUB pointer + * @param[in] pageCount number of pages in the array + * @param[in] pList pointer will store the return check array + * @param[in] pScrubListCopy List where pages are saved + * @param[in] pagesToScrubCheck How many pages will need to be saved * @returns the number of work successfully submitted, else 0 */ static NvU64 _scrubCheckAndSubmit ( OBJMEMSCRUB *pScrubber, - NvU64 chunkSize, - NvU64 *pPages, NvU64 pageCount, PSCRUB_NODE pList, + PSCRUB_NODE pScrubListCopy, NvLength pagesToScrubCheck ) { - NvU64 iter = 0; - NvU64 newId; - NV_STATUS status; + NvU64 iter = 0; + NvU64 newId; + NV_STATUS status; - if (pList == NULL && pagesToScrubCheck != 0) + if (pScrubListCopy == NULL && pagesToScrubCheck != 0) { NV_PRINTF(LEVEL_ERROR, "pages need to be saved off, but stash list is invalid\n"); goto exit; } - _scrubWaitAndSave(pScrubber, pList, pagesToScrubCheck); + _scrubWaitAndSave(pScrubber, pScrubListCopy, pagesToScrubCheck); for (iter = 0; iter < pageCount; iter++) { @@ -681,19 +721,19 @@ _scrubCheckAndSubmit NV_PRINTF(LEVEL_INFO, "Submitting work, Id: %llx, base: %llx, size: %llx\n", - newId, pPages[iter], chunkSize); + newId, pList[iter].base, pList[iter].size); { - status =_scrubMemory(pScrubber, pPages[iter], chunkSize, NV_MEMORY_DEFAULT, + status =_scrubMemory(pScrubber, pList[iter].base, pList[iter].size, NV_MEMORY_DEFAULT, (NvU32)newId); } if(status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failing because the work dint submit.\n"); + NV_PRINTF(LEVEL_ERROR, "Failing because the work didn't submit.\n"); goto exit; } - _scrubAddWorkToList(pScrubber, pPages[iter], chunkSize, newId); + _scrubAddWorkToList(pScrubber, pList[iter].base, pList[iter].size, newId); _scrubCheckProgress(pScrubber); } @@ -897,7 +937,7 @@ _scrubCheckProgress else lastSWSemaphoreDone = ceutilsUpdateProgress(pScrubber->pCeUtils); } - + pScrubber->lastSWSemaphoreDone = lastSWSemaphoreDone; return lastSWSemaphoreDone; @@ -949,3 +989,42 @@ cleanup: memdescDestroy(pMemDesc); return status; } + +static NV_STATUS +_scrubCombinePages +( + NvU64 *pPages, + NvU64 pageSize, + NvU64 pageCount, + PSCRUB_NODE *ppScrubList, + NvU64 *pSize +) +{ + NvU64 i, j; + + *ppScrubList = (PSCRUB_NODE)portMemAllocNonPaged(sizeof(SCRUB_NODE) * pageCount); + NV_ASSERT_OR_RETURN(*ppScrubList != NULL, NV_ERR_NO_MEMORY); + + // Copy first element from original list to new list + (*ppScrubList)[0].base = pPages[0]; + (*ppScrubList)[0].size = pageSize; + + for (i = 0, j = 0; i < (pageCount - 1); i++) + { + if ((((*ppScrubList)[j].size + pageSize) > SCRUB_MAX_BYTES_PER_LINE) || + ((pPages[i] + pageSize) != pPages[i+1])) + { + j++; + (*ppScrubList)[j].base = pPages[i+1]; + (*ppScrubList)[j].size = pageSize; + } + else + { + (*ppScrubList)[j].size += pageSize; + } + } + + *pSize = j + 1; + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c index b73206bb3..2a56c95a7 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c @@ -363,7 +363,7 @@ static NV_STATUS _pmaNumaAllocatePages osAllocAcquirePage(sysPhysAddr + (1 << osPageShift), (pageSize >> osPageShift) - 1); } - if (bScrubOnAlloc) + if (bScrubOnAlloc && (i > 0)) { PSCRUB_NODE pPmaScrubList = NULL; NvU64 count; @@ -608,7 +608,7 @@ NV_STATUS pmaNumaAllocate status = NV_ERR_NO_MEMORY; break; } - pPma->pMapInfo->pmaMapChangeStateAttrib(pMap, frameOffset, allocOption, NV_TRUE); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pMap, frameOffset, allocOption, MAP_MASK); } if (status != NV_OK) break; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c index 74bcdc89a..3ba3d7b10 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c @@ -97,7 +97,7 @@ _pmaRollback for (j = 0; j < framesPerPage; j++) { - pPma->pMapInfo->pmaMapChangeState(pPma->pRegions[regId], (frameNum + j), oldState); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), oldState, STATE_MASK); } } } @@ -110,7 +110,7 @@ _pmaRollback frameNum = PMA_ADDR2FRAME(pPages[failCount], addrBase); for(i = 0; i < failFrame; i++) { - pPma->pMapInfo->pmaMapChangeState(pPma->pRegions[regId], (frameNum + i), oldState); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + i), oldState, STATE_MASK); } } } @@ -208,10 +208,9 @@ pmaInitialize(PMA *pPma, NvU32 initFlags) // pMapInfo->pmaMapInit = pmaRegmapInit; pMapInfo->pmaMapDestroy = pmaRegmapDestroy; - pMapInfo->pmaMapChangeState = pmaRegmapChangeState; - pMapInfo->pmaMapChangeStateAttrib = pmaRegmapChangeStateAttrib; pMapInfo->pmaMapChangeStateAttribEx = pmaRegmapChangeStateAttribEx; - pMapInfo->pmaMapChangePageStateAttrib = pmaRegmapChangePageStateAttrib; + pMapInfo->pmaMapChangePageStateAttribEx = pmaRegmapChangePageStateAttribEx; + pMapInfo->pmaMapChangeBlockStateAttrib = pmaRegmapChangeBlockStateAttrib; pMapInfo->pmaMapRead = pmaRegmapRead; pMapInfo->pmaMapScanContiguous = pmaRegmapScanContiguous; pMapInfo->pmaMapScanDiscontiguous = pmaRegmapScanDiscontiguous; @@ -1036,11 +1035,8 @@ pmaAllocatePages_retry: frameBase, frameBase + numFramesAllocated - 1); - for (i = 0; i < numPagesAllocatedSoFar; i++) - { - pPma->pMapInfo->pmaMapChangePageStateAttrib(pMap, frameBase + (i * framesPerPage), - pageSize, pinOption, NV_TRUE); - } + pPma->pMapInfo->pmaMapChangeBlockStateAttrib(pMap, frameBase, numPagesAllocatedSoFar * framesPerPage, + pinOption, MAP_MASK); if (blacklistOffFlag && blacklistOffPerRegion[regId]) { @@ -1086,8 +1082,8 @@ pmaAllocatePages_retry: } lastFrameRangeEnd = frameBase + framesPerPage - 1; - pPma->pMapInfo->pmaMapChangePageStateAttrib(pMap, PMA_ADDR2FRAME(pPages[i], addrBase), - pageSize, pinOption, NV_TRUE); + pPma->pMapInfo->pmaMapChangePageStateAttribEx(pMap, PMA_ADDR2FRAME(pPages[i], addrBase), + pageSize, pinOption, MAP_MASK); } NV_PRINTF(LEVEL_INFO, "0x%llx through 0x%llx \n", @@ -1210,7 +1206,7 @@ pmaPinPages } else { - pPma->pMapInfo->pmaMapChangeState(pPma->pRegions[regId], (frameNum + j), STATE_PIN); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), STATE_PIN, STATE_MASK); } } } @@ -1263,7 +1259,7 @@ pmaUnpinPages } else { - pPma->pMapInfo->pmaMapChangeState(pPma->pRegions[regId], (frameNum + j), STATE_UNPIN); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), STATE_UNPIN, STATE_MASK); } } } @@ -1553,6 +1549,24 @@ pmaGetFreeMemory NvU64 *pBytesFree ) { +#if !defined(SRT_BUILD) + NvU64 val; + + portSyncSpinlockAcquire(pPma->pPmaLock); + NvBool nodeOnlined = pPma->nodeOnlined; + portSyncSpinlockRelease(pPma->pPmaLock); + + if (nodeOnlined) + { + osGetNumaMemoryUsage(pPma->numaNodeId, pBytesFree, &val); + return; + } + // + // what to return when bNUMA == NV_TRUE and nodeOnlined==NV_FALSE? + // TODO : BUG 4199482. + // +#endif + portSyncSpinlockAcquire(pPma->pPmaLock); *pBytesFree = pPma->pmaStats.numFreeFrames << PMA_PAGE_SHIFT; @@ -1573,6 +1587,24 @@ pmaGetTotalMemory *pBytesTotal = 0; +#if !defined(SRT_BUILD) + NvU64 val; + + portSyncSpinlockAcquire(pPma->pPmaLock); + NvBool nodeOnlined = pPma->nodeOnlined; + portSyncSpinlockRelease(pPma->pPmaLock); + + if (nodeOnlined) + { + osGetNumaMemoryUsage(pPma->numaNodeId, &val, pBytesTotal); + return; + } + // + // what to return when bNUMA == NV_TRUE and nodeOnlined==NV_FALSE? + // TODO : BUG 4199482. + // +#endif + for (i = 0; i < pPma->regSize; i++) { pMap = pPma->pRegions[i]; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c index 1c58270a5..7d510dce0 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c @@ -35,12 +35,13 @@ #include "nvport/nvport.h" #include "nvmisc.h" -#define _UINT_SIZE 64 -#define _UINT_SHIFT 6 +#define FRAME_TO_U64_SHIFT 6 +#define FRAME_TO_U64_SIZE (1llu << FRAME_TO_U64_SHIFT) +#define FRAME_TO_U64_MASK (FRAME_TO_U64_SIZE - 1llu) -#define PAGE_BITIDX(n) ((n) & (_UINT_SIZE - 1)) -#define PAGE_MAPIDX(n) ((n) >> _UINT_SHIFT) -#define MAKE_BITMASK(n) ((NvU64)0x1 << (n)) +#define PAGE_BITIDX(n) ((n) & (FRAME_TO_U64_SIZE - 1llu)) +#define PAGE_MAPIDX(n) ((n) >> FRAME_TO_U64_SHIFT) +#define MAKE_BITMASK(n) (1llu << (n)) #define SETBITS(bits, mask, newVal) ((bits & (~mask)) | (mask & newVal)) @@ -105,12 +106,12 @@ _checkOne(NvU64 *bits, NvU64 start, NvU64 end) if (bits[mapIdx] != 0) { firstSetBit = portUtilCountTrailingZeros64(bits[mapIdx]); - return ((mapIdx << _UINT_SHIFT) + firstSetBit); + return ((mapIdx << FRAME_TO_U64_SHIFT) + firstSetBit); } } // handle edge case - endMask = (NV_U64_MAX >> (_UINT_SIZE - endBitIdx - 1)); + endMask = (NV_U64_MAX >> (FRAME_TO_U64_SIZE - endBitIdx - 1)); if ((bits[endMapIdx] & endMask) == 0) { @@ -140,7 +141,7 @@ _checkOne(NvU64 *bits, NvU64 start, NvU64 end) NV_ASSERT(startMapIdx == endMapIdx); startMask = (NV_U64_MAX << startBitIdx); - endMask = (NV_U64_MAX >> (_UINT_SIZE - endBitIdx - 1)); + endMask = (NV_U64_MAX >> (FRAME_TO_U64_SIZE - endBitIdx - 1)); handle = (startMask & endMask); if ((handle & bits[startMapIdx]) == 0) @@ -159,43 +160,11 @@ _checkOne(NvU64 *bits, NvU64 start, NvU64 end) static NvU64 alignUpToMod(NvU64 frame, NvU64 alignment, NvU64 mod) { - if ((frame & (alignment - 1)) <= mod) - return NV_ALIGN_DOWN(frame, alignment) + mod; - else - return NV_ALIGN_UP(frame, alignment) + mod; + return ((frame - mod + alignment - 1ll) & ~(alignment - 1ll)) + mod; } - -// -// Determine if all frames in the 2MB range is not allocated -// They could be in scrubbing or eviction state. -// -static NvBool _pmaRegmapAllFree2mb(PMA_REGMAP *pRegmap, NvU64 frameNum) +static NvU64 alignDownToMod(NvU64 frame, NvU64 alignment, NvU64 mod) { - NvU64 baseFrame = (NV_ALIGN_DOWN((frameNum << PMA_PAGE_SHIFT), _PMA_2MB)) >> PMA_PAGE_SHIFT; - NvU32 numFrames = _PMA_2MB >> PMA_PAGE_SHIFT; - - // Always return false if the last 2MB range is incomplete - if ((baseFrame + numFrames) >= pRegmap->totalFrames) - { - return NV_FALSE; - } - - // - // We only care about STATE_PIN and STATE_UNPIN because: - // Even if the page is marked as SCRUBBING for example, we should not report OOM and prevent - // the clients from scanning the bitmap. - // - if (_checkOne(pRegmap->map[MAP_IDX_ALLOC_PIN], baseFrame, (baseFrame + numFrames - 1)) != -1) - { - return NV_FALSE; - } - - if (_checkOne(pRegmap->map[MAP_IDX_ALLOC_UNPIN], baseFrame, (baseFrame + numFrames - 1)) != -1) - { - return NV_FALSE; - } - - return NV_TRUE; + return ((frame - mod) & ~(alignment - 1ll)) + mod; } // @@ -235,7 +204,7 @@ _pmaRegmapScanNumaUnevictable if (mapIter == endMapIdx) { - mask = (mask >> (_UINT_SIZE - endBitIdx - 1)); + mask = (mask >> (FRAME_TO_U64_SIZE - endBitIdx - 1)); } if (mapIter == startMapIdx) @@ -246,7 +215,7 @@ _pmaRegmapScanNumaUnevictable #ifdef DEBUG_VERBOSE NV_PRINTF(LEVEL_INFO, "mapIter %llx frame %llx mask %llx unpinbitmap %llx pinbitmap %llx evictbitmap %llx", - mapIter, (mapIter << _UINT_SHIFT), mask, unpinBitmap[mapIter], pinBitmap[mapIter], evictBitmap[mapIter]); + mapIter, (mapIter << FRAME_TO_U64_SHIFT), mask, unpinBitmap[mapIter], pinBitmap[mapIter], evictBitmap[mapIter]); #endif // start from the end if ((unpinBitmap[mapIter] & mask) == mask) @@ -259,15 +228,15 @@ _pmaRegmapScanNumaUnevictable if (mapIter == endMapIdx) unevictableFrameIndex = frameEnd; else - unevictableFrameIndex = (mapIter << _UINT_SHIFT) + (_UINT_SIZE - 1); + unevictableFrameIndex = (mapIter << FRAME_TO_U64_SHIFT) + (FRAME_TO_U64_SIZE - 1); break; } #ifdef DEBUG_VERBOSE NV_PRINTF(LEVEL_INFO, "Check leading zero of %llx", ~(unpinBitmap[mapIter] & mask)); #endif - unevictableIndex = _UINT_SIZE - portUtilCountLeadingZeros64((~unpinBitmap[mapIter]) & mask) - 1; - unevictableFrameIndex = (mapIter << _UINT_SHIFT) + unevictableIndex; + unevictableIndex = FRAME_TO_U64_SIZE - portUtilCountLeadingZeros64((~unpinBitmap[mapIter]) & mask) - 1; + unevictableFrameIndex = (mapIter << FRAME_TO_U64_SHIFT) + unevictableIndex; break; } @@ -384,119 +353,6 @@ pmaRegMapScanContiguousNumaEviction return status; } -// -// Check whether the specified frame range is available for allocation or -// eviction. -// -// Returns: -// - NV_OK if the whole range is available and leaves frameIndex unset. -// -// - NV_ERR_IN_USE if some frames would need to be evicted, and sets frameIndex -// to the first one. -// -// - NV_ERR_NO_MEMORY if some frames are unavailable, and sets frameIndex to -// the first one. -// -// TODO: Would it be better to return the last frame index instead, given how the -// search skips over right past it? -// -static NV_STATUS -_pmaRegmapStatus(PMA_REGMAP *pRegmap, NvU64 start, NvU64 end, NvU64 *frameIndex) -{ - NvS64 diff; - - if ((diff = _checkOne(pRegmap->map[MAP_IDX_ALLOC_PIN], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - - if (pRegmap->frameEvictionsInProcess > 0) - { - // - // Pages that are being evicted may be in the free state so we need to - // check for eviction on all frames as long as any eviction is happening - // in the region. - // - if ((diff = _checkOne(pRegmap->map[MAP_IDX_EVICTING], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - } - - // - // Check SCRUBBING - // TODO: Skip this check if scrubbing has been completed for all frames. - // - if ((diff = _checkOne(pRegmap->map[MAP_IDX_SCRUBBING], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - - if ((diff = _checkOne(pRegmap->map[MAP_IDX_NUMA_REUSE], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - - if ((diff = _checkOne(pRegmap->map[MAP_IDX_ALLOC_UNPIN], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_IN_USE; - } - - if ((diff = _checkOne(pRegmap->map[MAP_IDX_BLACKLIST], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - - return NV_OK; -} - -// -// Return ALL_FREE if all frames in the [start, end] range are available for -// allocation or the first frame index that isn't. -// -static NvS64 -_pmaRegmapAvailable(PMA_REGMAP *pRegmap, NvU64 start, NvU64 end) -{ - NvU64 unavailableFrameIndex; - NV_STATUS frameStatus = _pmaRegmapStatus(pRegmap, start, end, &unavailableFrameIndex); - - if (frameStatus == NV_OK) - return ALL_FREE; - - NV_ASSERT(unavailableFrameIndex >= start); - NV_ASSERT(unavailableFrameIndex <= end); - - return unavailableFrameIndex; -} - -// -// Return ALL_FREE if all frames in the [start, end] range are available for -// allocation, EVICTABLE if some of them would need to be evicted, or the first -// frame index that isn't free nor evictable. -// -static NvS64 -_pmaRegmapEvictable(PMA_REGMAP *pRegmap, NvU64 start, NvU64 end) -{ - NvU64 unavailableFrameIndex; - NvS64 frameStatus = _pmaRegmapStatus(pRegmap, start, end, &unavailableFrameIndex); - - if (frameStatus == NV_OK) - return ALL_FREE; - - NV_ASSERT(unavailableFrameIndex >= start); - NV_ASSERT(unavailableFrameIndex <= end); - - if (frameStatus == NV_ERR_IN_USE) - return EVICTABLE; - - return unavailableFrameIndex; -} void * pmaRegmapInit @@ -552,6 +408,16 @@ pmaRegmapInit } portMemSet(newMap->map[i], 0, (NvLength) (newMap->mapLength * sizeof(NvU64))); } + { + // + // Simplify logic for 2M tracking. Set the last few nonaligned bits as pinned + // so that the XOR logic for delta 2M tracking is never true for an incomplete final page + // + NvU64 endOffs = (numFrames - 1llu) >> FRAME_TO_U64_SHIFT; + NvU64 endBit = (numFrames - 1llu) & FRAME_TO_U64_MASK; + NvU64 endMask = endBit == FRAME_TO_U64_MASK ? 0llu : ~(NV_U64_MAX >> (FRAME_TO_U64_MASK - endBit)); + newMap->map[MAP_IDX_ALLOC_PIN][endOffs] |= endMask; + } return (void *)newMap; } @@ -596,7 +462,6 @@ pmaRegmapDestroy(void *pMap) // Masks: // STATE_MASK, ATTRIB_MASK // - void pmaRegmapChangeStateAttribEx ( @@ -606,175 +471,178 @@ pmaRegmapChangeStateAttribEx PMA_PAGESTATUS newStateMask ) { - NvU64 mapIndex, mapOffset, bits, newVal, mask; - NvU32 i, bitWriteCount; - PMA_PAGESTATUS oldState, updatedState; - NvBool bUpdate2mbTracking = NV_FALSE; - PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap; - - mapIndex = PAGE_MAPIDX(frameNum); - mapOffset = PAGE_BITIDX(frameNum); - - NV_ASSERT(pRegmap != NULL); // possible error code return - NV_ASSERT(mapIndex < pRegmap->mapLength); - - bitWriteCount = PMA_STATE_BITS_PER_PAGE + PMA_ATTRIB_BITS_PER_PAGE; - - mask = (NvU64)MAKE_BITMASK(mapOffset); - - oldState = pmaRegmapRead(pRegmap, frameNum, NV_TRUE); - - // - // If we are going to allocate the 2MB page, we need bookkeeping - // before the bitmap is changed - // - if (((newState & STATE_MASK) != STATE_FREE) && _pmaRegmapAllFree2mb(pRegmap, frameNum)) - { - bUpdate2mbTracking = NV_TRUE; - } - - for (i = 0; i < bitWriteCount; i++) - { - if (NVBIT(i) & newStateMask) - { - newVal = ((NvU64) (newState & (1 << i)) >> i) << mapOffset; - bits = pRegmap->map[i][mapIndex]; - pRegmap->map[i][mapIndex] = (NvU64) SETBITS(bits, mask, newVal); - } - } - - // Update some stats for optimization - updatedState = pmaRegmapRead(pRegmap, frameNum, NV_TRUE); - - pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFrames, 1, - oldState, updatedState); + pmaRegmapChangeBlockStateAttrib(pMap, frameNum, 1, newState, newStateMask); +} - if (pRegmap->bProtected) - { - pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFramesProtected, 1, - oldState, updatedState); - } +void +pmaRegmapChangePageStateAttribEx +( + void * pMap, + NvU64 startFrame, + NvU64 pageSize, + PMA_PAGESTATUS newState, + PMA_PAGESTATUS newStateMask +) +{ + pmaRegmapChangeBlockStateAttrib(pMap, startFrame, pageSize / _PMA_64KB, newState, newStateMask); +} - // - // If we are freeing a frame, we should check if we need to update the 2MB - // page tracking - // - if (bUpdate2mbTracking || - (((oldState & STATE_MASK) != STATE_FREE) && _pmaRegmapAllFree2mb(pRegmap, frameNum))) - { - pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPages, 1, - oldState, updatedState); - if (pRegmap->bProtected) - { - pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPagesProtected, 1, - oldState, updatedState); - } - } +static NV_FORCEINLINE +void +_pmaRegmapDoSingleStateChange +( + PMA_REGMAP *pRegmap, + NvU64 idx, + NvU32 newState, + NvU32 writeMask, + NvU64 bitMask, + NvU64 *delta2m, + NvU64 *delta64k +) +{ + // get bits from map + NvU64 pinIn = pRegmap->map[MAP_IDX_ALLOC_PIN][idx]; + NvU64 unpinIn = pRegmap->map[MAP_IDX_ALLOC_UNPIN][idx]; + // Or of state for delta-tracking purposes + NvU64 initialState = pinIn | unpinIn; + // Mask out bits that are being upda + NvU64 maskedPin = pinIn & ~bitMask; + NvU64 maskedUnpin = unpinIn & ~bitMask; + // Update bits in new with bitMask + NvU64 pinRes = ((newState & (1llu << MAP_IDX_ALLOC_PIN)) ? bitMask : 0llu); + NvU64 unpinRes = ((newState & (1llu << MAP_IDX_ALLOC_UNPIN)) ? bitMask : 0llu); + // Output state based on whether writeMask is set + NvU64 pinOut = (writeMask & (1llu << MAP_IDX_ALLOC_PIN)) ? (maskedPin | pinRes) : pinIn; + NvU64 unpinOut = (writeMask & (1llu << MAP_IDX_ALLOC_UNPIN)) ? (maskedUnpin | unpinRes) : unpinIn; + // Or of final state for delta-tracking purposes + NvU64 finalState = pinOut | unpinOut; + NvU64 xored = initialState ^ finalState; + + // Write out new bits + pRegmap->map[MAP_IDX_ALLOC_PIN][idx] = pinOut; + pRegmap->map[MAP_IDX_ALLOC_UNPIN][idx] = unpinOut; + + // Update deltas + (*delta64k) += nvPopCount64(xored); + // Each 2M page is 32 64K pages, so we check each half of a 64-bit qword and xor them + (*delta2m) += ((((NvU32)finalState) == 0) != (((NvU32)initialState) == 0)) + + ((((NvU32)(finalState >> 32)) == 0) != (((NvU32)(initialState >> 32)) == 0)); } void -pmaRegmapChangeStateAttrib +pmaRegmapChangeBlockStateAttrib ( void *pMap, - NvU64 frameNum, + NvU64 frame, + NvU64 len, PMA_PAGESTATUS newState, - NvBool writeAttrib + PMA_PAGESTATUS writeMask ) { - NvU64 mapIndex, mapOffset, bits, newVal, mask; - NvU32 i; - NvU32 bitWriteCount; - PMA_PAGESTATUS oldState; - NvBool bUpdate2mbTracking = NV_FALSE; + NvU64 initialIdx = PAGE_MAPIDX(frame); + NvU64 finalIdx = PAGE_MAPIDX(frame + len - 1llu); + NvU64 initialOffs = PAGE_BITIDX(frame); + NvU64 finalOffs = PAGE_BITIDX(frame + len - 1llu); + NvU64 initialMask = NV_U64_MAX << initialOffs; + NvU64 finalMask = NV_U64_MAX >> (FRAME_TO_U64_MASK - finalOffs); PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap; + NvU64 i; + NvU64 delta2m = 0, delta64k = 0; - mapIndex = PAGE_MAPIDX(frameNum); - mapOffset = PAGE_BITIDX(frameNum); - - NV_ASSERT(pRegmap != NULL); // possible error code return - NV_ASSERT(mapIndex < pRegmap->mapLength); - - bitWriteCount = (writeAttrib ? - (PMA_STATE_BITS_PER_PAGE + PMA_ATTRIB_BITS_PER_PAGE) : - PMA_STATE_BITS_PER_PAGE); + NV_ASSERT(pRegmap != NULL); + NV_ASSERT(frame + len <= pRegmap->totalFrames); - mask = (NvU64)MAKE_BITMASK(mapOffset); - - oldState = pmaRegmapRead(pRegmap, frameNum, NV_TRUE); - - // - // If we are going to allocate the 2MB page, we need bookkeeping - // before the bitmap is changed - // - if (((newState & STATE_MASK) != STATE_FREE) && _pmaRegmapAllFree2mb(pRegmap, frameNum)) + // Update non-state attributes first in a tight loop. + for (i = PMA_STATE_BITS_PER_PAGE; i < PMA_BITS_PER_PAGE; i++) { - bUpdate2mbTracking = NV_TRUE; + NvU64 j; + NvU64 toWrite = (newState & (1u << i)) ? NV_U64_MAX : 0llu; + if (!((1u << i) & writeMask)) + { + continue; + } + if (initialIdx == finalIdx) + { + pRegmap->map[i][initialIdx] &= ~(initialMask & finalMask); + pRegmap->map[i][initialIdx] |= toWrite & (initialMask & finalMask); + continue; + } + + pRegmap->map[i][initialIdx] &= ~initialMask; + pRegmap->map[i][initialIdx] |= toWrite & initialMask; + + for (j = initialIdx + 1; j < finalIdx; j++) + { + pRegmap->map[i][j] = toWrite; + + } + pRegmap->map[i][finalIdx] &= ~finalMask; + pRegmap->map[i][finalIdx] |= toWrite & finalMask; + } - for (i = 0; i < bitWriteCount; i++) + if (!(writeMask & STATE_MASK)) { - newVal = ((NvU64) (newState & (1 << i)) >> i) << mapOffset; - bits = pRegmap->map[i][mapIndex]; - pRegmap->map[i][mapIndex] = (NvU64) SETBITS(bits, mask, newVal); + return; } - NV_ASSERT(pmaRegmapRead(pRegmap, frameNum, writeAttrib) == newState); - - // Update some stats for optimization - pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFrames, 1, - oldState, newState); - - if (pRegmap->bProtected) + // Entire state is in one NvU64, so exit immediately after + if (initialIdx == finalIdx) { - pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFramesProtected, 1, - oldState, newState); + _pmaRegmapDoSingleStateChange(pRegmap, initialIdx, newState, writeMask, initialMask & finalMask, &delta2m, &delta64k); + goto set_regs; } - // - // If we are freeing a frame, we should check if we need to update the 2MB - // page tracking - // - if (bUpdate2mbTracking || - (((oldState & STATE_MASK) != STATE_FREE) && _pmaRegmapAllFree2mb(pRegmap, frameNum))) + // Checks for 64-aligned start/end so we don't have to deal with partial coverage in the main loop + if (initialOffs != 0) { - pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPages, 1, - oldState, newState); - - if (pRegmap->bProtected) - { - pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPagesProtected, 1, - oldState, newState); - } + // Do first state update with partial NvU64 coverage + _pmaRegmapDoSingleStateChange(pRegmap, initialIdx, newState, writeMask, initialMask, &delta2m, &delta64k); + initialIdx++; + } + if (finalOffs != FRAME_TO_U64_MASK) + { + // Update last partial NvU64 + _pmaRegmapDoSingleStateChange(pRegmap, finalIdx, newState, writeMask, finalMask, &delta2m, &delta64k); + finalIdx--; } -} -void -pmaRegmapChangeState(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState) -{ - NV_ASSERT(newState <= STATE_PIN); - // Write state bits, but not attrib bits - pmaRegmapChangeStateAttrib((PMA_REGMAP *)pMap, frameNum, newState, NV_FALSE); -} + // Update all full-size + for (i = initialIdx; i <= finalIdx; i++) + { + _pmaRegmapDoSingleStateChange(pRegmap, i, newState, writeMask, NV_U64_MAX, &delta2m, &delta64k); + } -void -pmaRegmapChangePageStateAttrib -( - void * pMap, - NvU64 startFrame, - NvU64 pageSize, - PMA_PAGESTATUS newState, - NvBool writeAttrib -) -{ - NvU32 framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); - NvU64 frame; - for (frame = startFrame; frame < startFrame + framesPerPage; frame++) +set_regs: + if ((newState & writeMask & STATE_MASK) != 0) + { + pRegmap->pPmaStats->numFreeFrames -= delta64k; + pRegmap->pPmaStats->numFree2mbPages -= delta2m; + } + else { - pmaRegmapChangeStateAttrib((PMA_REGMAP *)pMap, frame, newState, writeAttrib); + pRegmap->pPmaStats->numFreeFrames += delta64k; + pRegmap->pPmaStats->numFree2mbPages += delta2m; } + if (!pRegmap->bProtected) + { + return; + } + if ((writeMask & newState & STATE_MASK) != 0) + { + pRegmap->pPmaStats->numFreeFramesProtected -= delta64k; + pRegmap->pPmaStats->numFree2mbPagesProtected -= delta2m; + } + else + { + pRegmap->pPmaStats->numFreeFramesProtected += delta64k; + pRegmap->pPmaStats->numFree2mbPagesProtected += delta2m; + } + return; } + PMA_PAGESTATUS pmaRegmapRead(void *pMap, NvU64 frameNum, NvBool readAttrib) { @@ -811,148 +679,504 @@ static NvS64 _scanContiguousSearchLoop NvBool bSearchEvictable ) { - NvU64 freeStart; - PMA_PAGESTATUS startStatus, endStatus, state; - NvS64 checkDiff; - NvS64 (*useFunc)(PMA_REGMAP *, NvU64, NvU64); + NvU64 frameBaseIdx = alignUpToMod(localStart, frameAlignment, frameAlignmentPadding); + // + // latestFree stores the highest '0' seen in the given map array in the current run + // ie we have the needed pages if frameBaseIdx + numPages == latestFree. Initialize to first aligned frame + // + NvU64 latestFree[PMA_BITS_PER_PAGE]; + NvU64 i; + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + latestFree[i] = frameBaseIdx; + } - if (!bSearchEvictable) +loop_begin: + // + // Always start a loop iteration with an updated frameBaseIdx by ensuring that latestFree is always >= frameBaseIdx + // frameBaseIdx == latestFree[i] means that there are no observed 0s so far in the current run + // + for (i = 0; i < PMA_BITS_PER_PAGE; i++) { - // Look for available frames - state = STATE_FREE; - checkDiff = ALL_FREE; - useFunc = _pmaRegmapAvailable; + if (latestFree[i] < frameBaseIdx) + { + latestFree[i] = frameBaseIdx; + } } - else + // At the end of memory, pages not available + if ((frameBaseIdx + numFrames - 1llu) > localEnd) { - // Look for evictable frames - state = STATE_UNPIN; - checkDiff = EVICTABLE; - useFunc = _pmaRegmapEvictable; + return -1; } - - freeStart = localStart; - while ((freeStart + numFrames - 1) <= localEnd) + for (i = 0; i < PMA_BITS_PER_PAGE; i++) { - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); - endStatus = pmaRegmapRead(pRegmap, (freeStart + numFrames - 1), NV_TRUE); - - if (endStatus == STATE_FREE || endStatus == state) + // TODO, merge logic so we don't need multiple calls for unpin + if (i == MAP_IDX_ALLOC_UNPIN && bSearchEvictable) + { + continue; + } + while (latestFree[i] < (frameBaseIdx + numFrames)) { - if (startStatus == STATE_FREE || startStatus == state) + // + // All this logic looks complicated, but essentially all it is doing is getting the NvU64 from + // the correct index in the array and shifting and masking so that the first bit is latestFree[i]. + // endOffs is set then to the length of the run of zeros at the beginning + // + NvU64 curMapIdx = PAGE_MAPIDX(latestFree[i]); + NvU64 beginOffs = PAGE_BITIDX(latestFree[i]); + NvU64 mask = beginOffs == 0 ? 0 : NV_U64_MAX << (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] >> beginOffs) | mask; + NvU64 endOffs = portUtilCountTrailingZeros64(curWithOffs); + // + // If no more are free, we have not hit the needed number of pages. Following loop finds + // the next free page + // + if (endOffs == 0) { - NvS64 diff = (*useFunc)(pRegmap, freeStart, (freeStart + numFrames - 1)); - if (diff == checkDiff) + mask = beginOffs == 0 ? 0 : NV_U64_MAX >> (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curMap = pRegmap->map[i][curMapIdx] | mask; + frameBaseIdx = latestFree[i] - beginOffs; + if (curMap != NV_U64_MAX) { - return (NvS64)freeStart; + goto free_found; } - else + curMapIdx++; + frameBaseIdx += FRAME_TO_U64_SIZE; + while (frameBaseIdx <= localEnd) { - // - // Find the next aligned free frame and set it as the start - // frame for next iteration's scan. - // - NV_ASSERT(diff >= 0); - - freeStart = alignUpToMod(diff + 1, frameAlignment, frameAlignmentPadding); - - NV_ASSERT(freeStart != 0); + curMap = pRegmap->map[i][curMapIdx]; + if(curMap != NV_U64_MAX) + { + goto free_found; + } + frameBaseIdx += FRAME_TO_U64_SIZE; + curMapIdx++; } + // No more free pages, exit + return -1; +free_found: + // Found a free page, set frameBaseIdx and go back to the beginning of the loop + frameBaseIdx += portUtilCountTrailingZeros64(~curMap); + frameBaseIdx = alignUpToMod(frameBaseIdx, frameAlignment, frameAlignmentPadding); + goto loop_begin; } - else - { - // Start point isn't free, so bump to check the next aligned frame - freeStart += frameAlignment; - } + latestFree[i] += endOffs; } - else + } + + return frameBaseIdx; +} + +static NvS64 _scanContiguousSearchLoopReverse +( + PMA_REGMAP *pRegmap, + NvU64 numFrames, + NvU64 localStart, + NvU64 localEnd, + NvU64 frameAlignment, + NvU64 frameAlignmentPadding, + NvBool bSearchEvictable +) +{ + NvU64 realAlign = (frameAlignmentPadding + numFrames) & (frameAlignment - 1ll); + NvU64 frameBaseIdx = alignDownToMod(localEnd + 1llu, frameAlignment, realAlign); + // + // latestFree stores the lowest '0' seen in the given map array in the current run + // ie we have the needed pages if frameBaseIdx - numPages == latestFree. Initialize to last aligned frame + // + NvU64 latestFree[PMA_BITS_PER_PAGE]; + NvU64 i; + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + latestFree[i] = frameBaseIdx; + } +loop_begin: + // + // Always start a loop iteration with an updated frameBaseIdx by ensuring that latestFree is always <= frameBaseIdx + // frameBaseIdx == latestFree[i] means that there are no observed 0s so far in the current run + // + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + if (latestFree[i] > frameBaseIdx) + { + latestFree[i] = frameBaseIdx; + } + } + // At the beginning of memory, pages not available + if ((localStart + numFrames) > frameBaseIdx) + { + return -1; + } + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + // TODO, merge logic so we don't need multiple calls for unpin + if (i == MAP_IDX_ALLOC_UNPIN && bSearchEvictable) + { + continue; + } + while (latestFree[i] > (frameBaseIdx - numFrames)) { // - // End point isn't usable, so jump to after the end to check again - // However, align the new start point properly before next iteration. + // All this logic looks complicated, but essentially all it is doing is getting the NvU64 from + // the correct index in the array and shifting and masking so that the last bit is latestFree[i]. + // endOffs is set then to the length of the run of zeros at the end // - freeStart += NV_ALIGN_UP(numFrames, frameAlignment); + NvU64 curId = latestFree[i] - 1llu; + NvU64 curMapIdx = PAGE_MAPIDX(curId); + NvU64 beginOffs = PAGE_BITIDX(curId); + NvU64 mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX >> (1llu + beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] << (FRAME_TO_U64_MASK - beginOffs)) | mask; + NvU64 endOffs = portUtilCountLeadingZeros64(curWithOffs); + // + // If no more are free, we have not hit the needed number of pages. Following loop finds + // the next free page + // + if (endOffs == 0) + { + mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX << (1llu + beginOffs); + NvU64 curMap = (pRegmap->map[i][curMapIdx]) | mask; + frameBaseIdx = latestFree[i] + FRAME_TO_U64_MASK - beginOffs; + if (curMap != NV_U64_MAX) + { + goto free_found; + } + curMapIdx--; + frameBaseIdx -= FRAME_TO_U64_SIZE; + while (frameBaseIdx > localStart) + { + curMap = pRegmap->map[i][curMapIdx]; + if(curMap != NV_U64_MAX) + { + goto free_found; + } + frameBaseIdx -= FRAME_TO_U64_SIZE; + curMapIdx--; + } + // No more free pages, exit + return -1; +free_found: + // Found a free page, set frameBaseIdx and go back to the beginning of the loop + frameBaseIdx -= portUtilCountLeadingZeros64(~curMap); + frameBaseIdx = alignDownToMod(frameBaseIdx, frameAlignment, realAlign); + goto loop_begin; + } + latestFree[i] -= endOffs; } } - return -1; + return frameBaseIdx - numFrames; } -static NvS64 _scanContiguousSearchLoopReverse +static NV_FORCEINLINE +NvU64 +_scanDiscontiguousSearchLoop ( PMA_REGMAP *pRegmap, - NvU64 numFrames, + NvU64 numPages, + NvU64 framesPerPage, NvU64 localStart, NvU64 localEnd, NvU64 frameAlignment, NvU64 frameAlignmentPadding, - NvBool bSearchEvictable + NvU64 *pPages, + NvU64 *pNumEvictablePages ) { - NvU64 freeStart; - PMA_PAGESTATUS startStatus, endStatus, state; - NvS64 checkDiff; - NvS64 (*useFunc)(PMA_REGMAP *, NvU64, NvU64); + NvU64 frameBaseIdx = alignUpToMod(localStart, frameAlignment, frameAlignmentPadding); + + // + // latestFree stores the lowest '0' seen in the given map array in the current run + // ie we have the needed pages if frameBaseIdx - numPages == latestFree. Initialize to last aligned frame + // + NvU64 latestFree[PMA_BITS_PER_PAGE]; + NvU64 totalFound = 0; + + // Evictable pages count down from end of array + NvU64 curEvictPage = numPages; + NvBool bEvictablePage = NV_FALSE; + NvU64 i; - if (!bSearchEvictable) + for (i = 0; i < PMA_BITS_PER_PAGE; i++) { - // Look for available frames - state = STATE_FREE; - checkDiff = ALL_FREE; - useFunc = _pmaRegmapAvailable; + latestFree[i] = frameBaseIdx; } - else +loop_begin: + // + // Always start a loop iteration with an updated frameBaseIdx by ensuring that latestFree is always >= frameBaseIdx + // frameBaseIdx == latestFree[i] means that there are no observed 0s so far in the current run + // + for (i = 0; i < PMA_BITS_PER_PAGE; i++) { - // Look for evictable frames - state = STATE_UNPIN; - checkDiff = EVICTABLE; - useFunc = _pmaRegmapEvictable; + if (latestFree[i] < frameBaseIdx) + { + latestFree[i] = frameBaseIdx; + } } - // First frame from end able to accommodate num_frames allocation. - freeStart = localEnd + 1 - numFrames; - freeStart -= (freeStart - localStart) % frameAlignment; + // Initialize to standard free page state + bEvictablePage = NV_FALSE; - while (freeStart >= localStart && (NvS64)freeStart >= 0) + // At the end of memory, pages not available + if ((frameBaseIdx + framesPerPage - 1llu) > localEnd) { - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); - endStatus = pmaRegmapRead(pRegmap, (freeStart + numFrames - 1), NV_TRUE); + *pNumEvictablePages = numPages - curEvictPage; + return totalFound; + } - if (startStatus == STATE_FREE || startStatus == state) + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + // If array is not already full of evictable and free pages, go to evictable loop + if ((i != MAP_IDX_ALLOC_UNPIN) || (curEvictPage <= totalFound)) { - if (endStatus == STATE_FREE || endStatus == state) + while (latestFree[i] < (frameBaseIdx + framesPerPage)) { - NvS64 diff = (*useFunc)(pRegmap, freeStart, (freeStart + numFrames - 1)); - if (diff == checkDiff) + // + // All this logic looks complicated, but essentially all it is doing is getting the NvU64 from + // the correct index in the array and shifting and masking so that the first bit is latestFree[i]. + // endOffs is set then to the length of the run of zeros at the beginning + // + NvU64 curMapIdx = PAGE_MAPIDX(latestFree[i]); + NvU64 beginOffs = PAGE_BITIDX(latestFree[i]); + NvU64 mask = beginOffs == 0 ? 0 : NV_U64_MAX << (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] >> beginOffs) | mask; + NvU64 endOffs = portUtilCountTrailingZeros64(curWithOffs); + // + // If no more are free, we have not hit the needed number of pages. Following loop finds + // the next free page + // + if (endOffs == 0) { - return (NvS64)freeStart; + mask = beginOffs == 0 ? 0 : NV_U64_MAX >> (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curMap = pRegmap->map[i][curMapIdx] | mask; + frameBaseIdx = latestFree[i] - beginOffs; + if (curMap != NV_U64_MAX) + { + goto free_found; + } + curMapIdx++; + frameBaseIdx += FRAME_TO_U64_SIZE; + while (frameBaseIdx <= localEnd) + { + curMap = pRegmap->map[i][curMapIdx]; + if(curMap != NV_U64_MAX) + { + goto free_found; + } + frameBaseIdx += FRAME_TO_U64_SIZE; + curMapIdx++; + } + // No more free pages, exit + *pNumEvictablePages = numPages - curEvictPage; + return totalFound; +free_found: + // Found a free page, set frameBaseIdx and go back to the beginning of the loop + frameBaseIdx += portUtilCountTrailingZeros64(~curMap); + frameBaseIdx = alignUpToMod(frameBaseIdx, frameAlignment, frameAlignmentPadding); + goto loop_begin; } - else + latestFree[i] += endOffs; + } + } + else + { + // Loop to check if current range has an unpinned page, then it gets stored in the evictable area + while (latestFree[i] < (frameBaseIdx + framesPerPage)) + { + // Basically same as above loop, just not exiting if 0 not found, instead setting bEvictablePage + NvU64 curMapIdx = PAGE_MAPIDX(latestFree[i]); + NvU64 beginOffs = PAGE_BITIDX(latestFree[i]); + NvU64 mask = beginOffs == 0 ? 0 : NV_U64_MAX << (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] >> beginOffs) | mask; + NvU64 endOffs = portUtilCountTrailingZeros64(curWithOffs); + latestFree[i] += endOffs; + if (endOffs == 0) { - NV_ASSERT(diff >= 0); - - // Set end point to one frame before the first unavailable frame found - freeStart = diff - numFrames; - freeStart -= (freeStart - localStart) % frameAlignment; + bEvictablePage = NV_TRUE; + break; } } - else + } + } + + // Store evictable pages at end of array to not interfere with free pages + if (bEvictablePage) + { + curEvictPage--; + pPages[curEvictPage] = frameBaseIdx; + frameBaseIdx += framesPerPage; + goto loop_begin; + } + + pPages[totalFound] = frameBaseIdx; + totalFound++; + frameBaseIdx += framesPerPage; + + // Found all needed pages (all free and not STATE_UNPIN) + if (totalFound == numPages) + { + *pNumEvictablePages = 0; + return numPages; + } + goto loop_begin; +} + +static NV_FORCEINLINE +NvU64 +_scanDiscontiguousSearchLoopReverse +( + PMA_REGMAP *pRegmap, + NvU64 numPages, + NvU64 framesPerPage, + NvU64 localStart, + NvU64 localEnd, + NvU64 frameAlignment, + NvU64 frameAlignmentPadding, + NvU64 *pPages, + NvU64 *pNumEvictablePages +) +{ + NvU64 realAlign = (frameAlignmentPadding + framesPerPage) & (frameAlignment - 1ll); + NvU64 frameBaseIdx = alignDownToMod(localEnd+1llu, frameAlignment, realAlign); + + // + // latestFree stores the lowest '0' seen in the given map array in the current run + // ie we have the needed pages if frameBaseIdx - numPages == latestFree. Initialize to last aligned frame + // + NvU64 latestFree[PMA_BITS_PER_PAGE]; + NvU64 totalFound = 0; + + // Evictable pages count down from end of array + NvU64 curEvictPage = numPages; + NvBool bEvictablePage = NV_FALSE; + NvU64 i; + + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + latestFree[i] = frameBaseIdx; + } +loop_begin: + // + // Always start a loop iteration with an updated frameBaseIdx by ensuring that latestFree is always <= frameBaseIdx + // frameBaseIdx == latestFree[i] means that there are no observed 0s so far in the current run + // + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + if (latestFree[i] > frameBaseIdx) + { + latestFree[i] = frameBaseIdx; + } + } + + // Initialize to standard free page state + bEvictablePage = NV_FALSE; + + // At the beginning of memory, pages not available + if ((localStart + framesPerPage) > frameBaseIdx) + { + *pNumEvictablePages = numPages - curEvictPage; + return totalFound; + } + + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + // If array is not already full of evictable and free pages, go to evictable loop + if ((i != MAP_IDX_ALLOC_UNPIN) || (curEvictPage <= totalFound)) + { + while (latestFree[i] > (frameBaseIdx - framesPerPage)) { - // Start point isn't free, so bump to check the next aligned frame - freeStart -= frameAlignment; + // + // All this logic looks complicated, but essentially all it is doing is getting the NvU64 from + // the correct index in the array and shifting and masking so that the last bit is latestFree[i]. + // endOffs is set then to the length of the run of zeros at the end + // + NvU64 curId = latestFree[i] - 1llu; + NvU64 curMapIdx = PAGE_MAPIDX(curId); + NvU64 beginOffs = PAGE_BITIDX(curId); + NvU64 mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX >> (1llu + beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] << (FRAME_TO_U64_MASK - beginOffs)) | mask; + NvU64 endOffs = portUtilCountLeadingZeros64(curWithOffs); + + // + // If no more are free, we have not hit the needed number of pages. Following loop finds + // the next free page + // + if (endOffs == 0) + { + mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX << (1llu + beginOffs); + NvU64 curMap = pRegmap->map[i][curMapIdx] | mask; + frameBaseIdx = latestFree[i] + FRAME_TO_U64_MASK - beginOffs; + if (curMap != NV_U64_MAX) + { + goto free_found; + } + curMapIdx--; + frameBaseIdx -= 64; + while (frameBaseIdx > localStart) + { + curMap = pRegmap->map[i][curMapIdx]; + if(curMap != NV_U64_MAX) + { + goto free_found; + } + frameBaseIdx -= 64; + curMapIdx--; + } + + // No more free pages, exit + *pNumEvictablePages = numPages - curEvictPage; + return totalFound; +free_found: + // Found a free page, set frameBaseIdx and go back to the beginning of the loop + frameBaseIdx -= portUtilCountLeadingZeros64(~curMap); + frameBaseIdx = alignDownToMod(frameBaseIdx, frameAlignment, realAlign); + goto loop_begin; + } + latestFree[i] -= endOffs; } } else { - // - // End point isn't usable, so jump to after the end to check again - // However, align the new start point properly before next iteration. - // - freeStart -= NV_ALIGN_UP(numFrames, frameAlignment); + // Loop to check if current range has an unpinned page, then it gets stored in the evictable area + while (latestFree[i] > (frameBaseIdx - framesPerPage)) + { + // Basically same as above loop, just not exiting if 0 not found, instead setting bEvictablePage + NvU64 curId = latestFree[i] - 1llu; + NvU64 curMapIdx = PAGE_MAPIDX(curId); + NvU64 beginOffs = PAGE_BITIDX(curId); + NvU64 mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX >> (1llu + beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] << (FRAME_TO_U64_MASK - beginOffs)) | mask; + NvU64 endOffs = portUtilCountLeadingZeros64(curWithOffs); + latestFree[i] -= endOffs; + if (endOffs == 0) + { + bEvictablePage = NV_TRUE; + break; + } + } } } - return -1; + frameBaseIdx -= framesPerPage; + + // Store evictable pages at end of array to not interfere with free pages + if (bEvictablePage) + { + curEvictPage--; + pPages[curEvictPage] = frameBaseIdx; + goto loop_begin; + } + + pPages[totalFound] = frameBaseIdx; + totalFound++; + + // Found all needed pages (all free and not STATE_UNPIN) + if (totalFound == numPages) + { + *pNumEvictablePages = 0; + return numPages; + } + + goto loop_begin; } // @@ -1004,10 +1228,6 @@ pmaRegmapScanContiguous } localStart = alignUpToMod(localStart, frameAlignment, frameAlignmentPadding); - NV_PRINTF(LEVEL_INFO, - "Scanning with addrBase 0x%llx in frame range 0x%llx..0x%llx, pages to allocate 0x%llx\n", - addrBase, localStart, localEnd, numPages); - if (!bReverseAlloc) { frameFound = _scanContiguousSearchLoop(pRegmap, numFrames, localStart, localEnd, @@ -1069,10 +1289,12 @@ pmaRegmapScanDiscontiguous NvBool bReverseAlloc ) { - NvU64 freeStart, found, framesPerPage, localStart, localEnd; - NvU64 alignedAddrBase, frameAlignmentPadding; - PMA_PAGESTATUS startStatus, endStatus; - PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap; + PMA_REGMAP *pRegmap = (PMA_REGMAP*) pMap; + NvU64 localStart, localEnd, framesPerPage, alignedAddrBase, frameAlignmentPadding; + NvU64 freeFound = 0, evictFound = 0; + NvU64 totalFound = 0; + NV_STATUS status = NV_OK; + NvU64 i; framesPerPage = pageSize >> PMA_PAGE_SHIFT; @@ -1098,101 +1320,69 @@ pmaRegmapScanDiscontiguous else { localStart = 0; - localEnd = pRegmap->totalFrames-1; + localEnd = pRegmap->totalFrames - 1; } - localStart = alignUpToMod(localStart, framesPerPage, frameAlignmentPadding); - found = 0; + // + // Do the actual scanning here. The scanning functions return free pages at the beginning of + // the array, and evictable pages in reverse order at the end of the array + // if (!bReverseAlloc) { - freeStart = localStart; + freeFound = _scanDiscontiguousSearchLoop(pRegmap, numPages, framesPerPage, + localStart, localEnd, alignment >> PMA_PAGE_SHIFT, + frameAlignmentPadding, freeList, &evictFound); } else { - // First frame from end able to accommodate page allocation. - freeStart = localEnd + 1 - framesPerPage; - freeStart -= (freeStart - localStart) % framesPerPage; + freeFound = _scanDiscontiguousSearchLoopReverse(pRegmap, numPages, framesPerPage, + localStart, localEnd, alignment >> PMA_PAGE_SHIFT, + frameAlignmentPadding, freeList, &evictFound); } - NV_PRINTF(LEVEL_INFO, - "Scanning with addrBase 0x%llx in frame range 0x%llx..0x%llx, pages to allocate 0x%llx\n", - addrBase, localStart, localEnd, numPages); - - // scan for allocatable pages - // two-pass algorithm - while (found != numPages) - { - if (!bReverseAlloc) - { - if ((freeStart + framesPerPage - 1) > localEnd) break; - } - else - { - if (freeStart < localStart || (NvS64)freeStart < 0) break; - } + *numPagesAlloc = freeFound; - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); - endStatus = pmaRegmapRead(pRegmap, (freeStart + framesPerPage - 1), NV_TRUE); + // Scanning implementations don't actually decrement evictFound, so adjust appropriately here + evictFound = freeFound + evictFound > numPages ? numPages - freeFound : evictFound; - if (startStatus == STATE_FREE) - { - if(endStatus == STATE_FREE) - { - NvS64 diff = _pmaRegmapAvailable(pRegmap, freeStart, (freeStart + framesPerPage - 1)); - if (diff == ALL_FREE) - { - freeList[found++] = addrBase + (freeStart << PMA_PAGE_SHIFT); - } - } - } - freeStart = !bReverseAlloc ? (freeStart + framesPerPage) : (freeStart - framesPerPage); - } - - *numPagesAlloc = found; - if(found == numPages) return NV_OK; - if(bSkipEvict) return NV_ERR_NO_MEMORY; - - if (!bReverseAlloc) + // Not enough pages + if (((freeFound + evictFound) != numPages) || + (bSkipEvict && (freeFound != numPages))) { - freeStart = localStart; + status = NV_ERR_NO_MEMORY; } - else + else if (evictFound != 0) { - // First frame from end able to accommodate page allocation. - freeStart = localEnd + 1 - framesPerPage; - freeStart -= (freeStart - localStart) % framesPerPage; + status = NV_ERR_IN_USE; } - while (found != numPages) - { - if (!bReverseAlloc) - { - if ((freeStart + framesPerPage - 1) > localEnd) return NV_ERR_NO_MEMORY; - } - else - { - if (freeStart < localStart || (NvS64)freeStart < 0) return NV_ERR_NO_MEMORY; - } - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); - endStatus = pmaRegmapRead(pRegmap, (freeStart + framesPerPage - 1), NV_TRUE); + // Set totalFound appropriately to shift pages at the end of the function + totalFound = freeFound + evictFound; + if (bSkipEvict) + { + totalFound = freeFound; + goto alignAndReturn; + } - if (startStatus == STATE_FREE || startStatus == STATE_UNPIN) - { - if(endStatus == STATE_FREE || endStatus == STATE_UNPIN) - { - NvS64 diff = _pmaRegmapEvictable(pRegmap, freeStart, (freeStart + framesPerPage - 1)); - if (diff == EVICTABLE) - { - freeList[found++] = addrBase + (freeStart << PMA_PAGE_SHIFT); - } - } - } - freeStart = !bReverseAlloc ? (freeStart + framesPerPage) : (freeStart - framesPerPage); + // End of list contains the evictable pages, swap elements from beginning of range to end + for (i = (numPages - freeFound) >> 1; i != 0; i--) + { + NvU64 temp = freeList[freeFound + i - 1llu]; + freeList[freeFound + i - 1llu] = freeList[numPages - i]; + freeList[numPages - i] = temp; } - return NV_ERR_IN_USE; +alignAndReturn: + while (totalFound != 0) + { + totalFound--; + freeList[totalFound] <<= PMA_PAGE_SHIFT; + freeList[totalFound] += addrBase; + } + return status; } + void pmaRegmapGetSize ( @@ -1230,9 +1420,9 @@ pmaRegmapGetLargestFree bitmap |= (~0ULL) << PAGE_BITIDX(pRegmap->totalFrames); } - if (maxZerosGet(bitmap) == _UINT_SIZE) + if (maxZerosGet(bitmap) == FRAME_TO_U64_SIZE) { - mapTrailZeros += _UINT_SIZE; + mapTrailZeros += FRAME_TO_U64_SIZE; } else { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c index a84a866b3..9841ae451 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c @@ -287,8 +287,8 @@ sec2utilsDestruct_IMPL { OBJCHANNEL *pChannel = pSec2Utils->pChannel; OBJGPU *pGpu = pSec2Utils->pGpu; - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + MemoryManager *pMemoryManager = NULL; + RM_API *pRmApi = NULL; // Sanity checks if ((pGpu == NULL) || (pChannel == NULL)) @@ -302,6 +302,9 @@ sec2utilsDestruct_IMPL return; } + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + ccslContextClear(pSec2Utils->pCcslCtx); if ((pChannel->bClientUserd) && (pChannel->pControlGPFifo != NULL)) @@ -591,7 +594,7 @@ sec2utilsMemset_IMPL do { NvU64 maxContigSize = bContiguous ? memsetLength : (pageGranularity - offset % pageGranularity); - NvU32 memsetSizeContig = (NvU32)NV_MIN(NV_MIN(memsetLength, maxContigSize), NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES); + NvU32 memsetSizeContig = (NvU32)NV_MIN(NV_MIN(memsetLength, maxContigSize), NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES); channelPbInfo.dstAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, offset); diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c index f0564549b..2eec6fa2d 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c @@ -30,6 +30,7 @@ #include "gpu/mem_mgr/mem_desc.h" #include "published/ampere/ga100/dev_fb.h" +#include "published/ampere/ga100/hwproject.h" /*! * @brief Write the sysmemFlushBuffer val into the NV_PFB_NISO_FLUSH_SYSMEM_ADDR register @@ -440,3 +441,13 @@ kmemsysIsPagePLCable_GA100 return NV_TRUE; } } + +NvU32 +kmemsysGetMaxFbpas_GA100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_SCAL_LITTER_NUM_FBPAS; +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c index ce11a8fa7..9ad1e6a06 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,15 +23,23 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "nvtypes.h" #include "os/os.h" #include "kernel/gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/mem_desc.h" #include "gpu/bus/kern_bus.h" +#include "kernel/gpu/intr/intr.h" +#include "nverror.h" #include "published/hopper/gh100/dev_fb.h" +#include "published/hopper/gh100/dev_fbpa.h" #include "published/hopper/gh100/dev_vm.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" #include "published/hopper/gh100/dev_nv_xal_addendum.h" +#include "published/hopper/gh100/dev_nv_xpl.h" +#include "published/hopper/gh100/dev_xtl_ep_pri.h" +#include "published/hopper/gh100/hwproject.h" +#include "published/ampere/ga100/dev_fb.h" NV_STATUS kmemsysDoCacheOp_GH100 @@ -566,3 +574,24 @@ kmemsysSwizzIdToVmmuSegmentsRange_GH100 return NV_OK; } +NvU32 +kmemsysGetEccDedCountSize_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; +} + +NvU32 +kmemsysGetEccDedCountRegAddr_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 fbpa, + NvU32 subp +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT(fbpa) + (subp * NV_FBPA_PRI_STRIDE); +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c index ad3938bfa..f4d4cfaf1 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,9 @@ #include "gpu/mem_sys/kern_mem_sys.h" #include "published/turing/tu102/dev_vm.h" +#include "published/turing/tu102/hwproject.h" +#include "published/turing/tu102/dev_fbpa.h" +#include "published/turing/tu102/dev_ltc.h" void kmemsysWriteL2SysmemInvalidateReg_TU102 @@ -68,3 +71,114 @@ kmemsysReadL2PeermemInvalidateReg_TU102 { return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_L2_PEERMEM_INVALIDATE); } + +NvU32 +kmemsysGetMaxFbpas_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_SCAL_LITTER_NUM_FBPAS; +} + +NvU32 kmemsysGetEccDedCountSize_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; +} + +NvU32 kmemsysGetEccDedCountRegAddr_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 fbpa, + NvU32 subp +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT(fbpa) + (subp * NV_FBPA_PRI_STRIDE); +} + +/*! + * Utility function used to read registers and ignore PRI errors + */ +static NvU32 +_kmemsysReadRegAndMaskPriError +( + OBJGPU *pGpu, + NvU32 regAddr +) +{ + NvU32 regVal; + + regVal = osGpuReadReg032(pGpu, regAddr); + if ((regVal & GPU_READ_PRI_ERROR_MASK) == GPU_READ_PRI_ERROR_CODE) + { + return 0; + } + + return regVal; +} + +void +kmemsysGetEccCounts_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 *dramCount, + NvU32 *ltcCount +) +{ + NvU32 maxFbpas = kmemsysGetMaxFbpas_HAL(pGpu, pKernelMemorySystem); + NvU32 dedCountSize = kmemsysGetEccDedCountSize_HAL(pGpu, pKernelMemorySystem); + NvU32 fbpaDedCountRegAddr = 0; + NvU32 regVal; + + if (dramCount == NULL || ltcCount == NULL) + { + return; + } + + *dramCount = 0; + *ltcCount = 0; + + for (NvU32 i = 0; i < maxFbpas; i++) + { + for (NvU32 j = 0; j < dedCountSize; j++) + { + // DRAM count read + fbpaDedCountRegAddr = kmemsysGetEccDedCountRegAddr_HAL(pGpu, pKernelMemorySystem, i, j); + *dramCount += _kmemsysReadRegAndMaskPriError(pGpu, fbpaDedCountRegAddr); + + // LTC count read + regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + + (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE)); + *ltcCount += DRF_VAL(_PLTCG_LTC0_LTS0, _L2_CACHE_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + } + } +} + +void +kmemsysClearEccCounts_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + NvU32 maxFbpas = kmemsysGetMaxFbpas_HAL(pGpu, pKernelMemorySystem); + NvU32 dedCountSize = kmemsysGetEccDedCountSize_HAL(pGpu, pKernelMemorySystem); + NvU32 fbpaDedCountRegAddr = 0; + + for (NvU32 i = 0; i < maxFbpas; i++) + { + for (NvU32 j = 0; j < dedCountSize; j++) + { + fbpaDedCountRegAddr = kmemsysGetEccDedCountRegAddr_HAL(pGpu, pKernelMemorySystem, i, j); + osGpuWriteReg032(pGpu, fbpaDedCountRegAddr, 0); + osGpuWriteReg032(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE), 0); + } + } +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c index f964bb383..e3fc0e255 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c @@ -531,6 +531,7 @@ kmemsysGetMIGGPUInstanceMemInfo_IMPL NvU64 vmmuSegmentSize; NvU64 startAddr; NvU64 endAddr; + NvU64 partitionSize; NV_ASSERT_OR_RETURN(pAddrRange != NULL, NV_ERR_INVALID_ARGUMENT); *pAddrRange = NV_RANGE_EMPTY; @@ -556,12 +557,75 @@ kmemsysGetMIGGPUInstanceMemInfo_IMPL NV_ASSERT_OR_RETURN((vmmuSegmentSize != 0), NV_ERR_INVALID_STATE); startAddr = pKernelMemorySystem->gpuInstanceMemConfig[swizzId].startingVmmuSegment * vmmuSegmentSize; - endAddr = startAddr + (pKernelMemorySystem->gpuInstanceMemConfig[swizzId].memSizeInVmmuSegment * vmmuSegmentSize) - 1; + partitionSize = pKernelMemorySystem->gpuInstanceMemConfig[swizzId].memSizeInVmmuSegment * vmmuSegmentSize; + + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + NvU64 memblockSize; + NvU64 alignedStartAddr; + + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + + // + // Align the partition start address and size to memblock size + // Some FB memory is wasted here if it is not already aligned. + // + alignedStartAddr = NV_ALIGN_UP64(startAddr, memblockSize); + + if(pKernelMemorySystem->bNumaMigPartitionSizeEnumerated) + { + partitionSize = pKernelMemorySystem->numaMigPartitionSize[swizzId]; + } + else + { + partitionSize -= (alignedStartAddr - startAddr); + } + + partitionSize = NV_ALIGN_DOWN64(partitionSize, memblockSize); + startAddr = alignedStartAddr; + } + + endAddr = startAddr + partitionSize - 1; + *pAddrRange = rangeMake(startAddr, endAddr); return NV_OK; } +/** + * @brief Modifies numaMigPartitionSize array such that memory size of + all the mig partitions with swizzId between startSwizzId and + endSwizzId is assigned the minimum value among all partition's + memory size. + * + * @param[IN] pKernelMemorySystem + * @param[IN] startSwizzId + * @param[IN] endSwizzId + * + */ +static void +_kmemsysSetNumaMigPartitionSizeSubArrayToMinimumValue +( + KernelMemorySystem *pKernelMemorySystem, + NvU64 startSwizzId, + NvU64 endSwizzId +) +{ + NvU64 minPartitionSize = pKernelMemorySystem->numaMigPartitionSize[startSwizzId]; + NvU64 index; + + for (index = startSwizzId; index <= endSwizzId; index++) + { + if(pKernelMemorySystem->numaMigPartitionSize[index] < minPartitionSize) + minPartitionSize = pKernelMemorySystem->numaMigPartitionSize[index]; + } + + for (index = startSwizzId; index <= endSwizzId; index++) + { + pKernelMemorySystem->numaMigPartitionSize[index] = minPartitionSize; + } +} + /*! * @brief Function to populate static GPU instance memory config which will be * utilized for GPU instance memory query and memory allocation @@ -615,6 +679,30 @@ kmemsysPopulateMIGGPUInstanceMemConfig_KERNEL kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments)); } + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + NV_RANGE addrRange = NV_RANGE_EMPTY; + NvU32 memSize; + + for(swizzId = 0; swizzId < KMIGMGR_MAX_GPU_SWIZZID; swizzId++) + { + kmemsysGetMIGGPUInstanceMemInfo(pGpu, pKernelMemorySystem, swizzId, &addrRange); + pKernelMemorySystem->numaMigPartitionSize[swizzId] = addrRange.hi - addrRange.lo + 1; + } + + // + // In GH180 for all the swizzId's for a given memory profile (FULL, HALF, QUARTER + // and EIGHTH partitions) might not be same. Modify numaMigPartitionSize array + // for the partition size to be constant for a given profile. BUG 4284299. + // + for (memSize = NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL; memSize < NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE; memSize++) + { + NV_RANGE swizzRange = kmigmgrMemSizeFlagToSwizzIdRange(pGpu, pKernelMIGManager, + DRF_NUM(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, memSize)); + _kmemsysSetNumaMigPartitionSizeSubArrayToMinimumValue(pKernelMemorySystem, swizzRange.lo, swizzRange.hi); + } + pKernelMemorySystem->bNumaMigPartitionSizeEnumerated = NV_TRUE; + } return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c index d4a28cabb..df9a0ce50 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -5800,6 +5800,7 @@ kmigmgrInitGPUInstanceBufPools_IMPL { Heap *pHeap; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU32 pmaConfig = PMA_QUERY_NUMA_ONLINED; NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_ARGUMENT); pHeap = pKernelMIGGpuInstance->pMemoryPartitionHeap; NV_ASSERT_OR_RETURN(pHeap != NULL, NV_ERR_INVALID_STATE); @@ -5815,7 +5816,12 @@ kmigmgrInitGPUInstanceBufPools_IMPL // This is just a sanity check to make sure this assumption is correct and // allocation from PMA cannot trigger UVM evictions. // - if (memmgrIsPmaInitialized(pMemoryManager)) + // When FB memory is onlined as NUMA node, kernel can directly alloc FB memory + // and hence free memory can not be expected to be same as total memory. + // + if (memmgrIsPmaInitialized(pMemoryManager) && + (pmaQueryConfigs(&pHeap->pmaObject, &pmaConfig) == NV_OK) && + !(pmaConfig & PMA_QUERY_NUMA_ONLINED)) { NvU64 freeSpace, totalSpace; pmaGetFreeMemory(&pHeap->pmaObject, &freeSpace); diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c index baa40ff38..332711b4f 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c @@ -447,3 +447,40 @@ kgmmuClearReplayableFaultIntr_TU102 Intr *pIntr = GPU_GET_INTR(pGpu); intrClearLeafVector_HAL(pGpu, pIntr, NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE, pThreadState); } + +NvU32 +kgmmuGetEccCounts_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NvU32 mmuCount = 0; + NvU32 regVal; + + // L2TLB + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _L2TLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // HUBTLB + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _HUBTLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // FILLUNIT + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _FILLUNIT_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + return mmuCount; +} + +void +kgmmuClearEccCounts_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + GPU_REG_WR32(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT, 0); + GPU_REG_WR32(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT, 0); + GPU_REG_WR32(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT, 0); +} diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c index 9a316a44c..d48d2fec4 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c @@ -52,7 +52,6 @@ #include "deprecated/rmapi_deprecated.h" #include "nvRmReg.h" - // // Watchdog object ids // @@ -107,7 +106,6 @@ #define SUBDEVICE_MASK_ALL DRF_MASK(NV906F_DMA_SET_SUBDEVICE_MASK_VALUE) - NV_STATUS krcWatchdogChangeState_IMPL ( @@ -402,7 +400,7 @@ krcWatchdogShutdown_IMPL // // Make sure to clear any old watchdog data this also clears - // WATCHDOG_FLAGS_INITIALIZED + // WATCHDOG_FLAGS_INITIALIZED, bHandleValid, and hClient // portMemSet(&pKernelRc->watchdog, 0, sizeof pKernelRc->watchdog); portMemSet(&pKernelRc->watchdogChannelInfo, 0, @@ -519,6 +517,8 @@ krcWatchdogInit_IMPL status = NV_ERR_NO_MEMORY; goto error; } + pKernelRc->watchdog.hClient = hClient; + pKernelRc->watchdog.bHandleValid = NV_TRUE; } if (bAcquireLock) @@ -1178,6 +1178,7 @@ error: if (status != NV_OK) { pRmApi->Free(pRmApi, hClient, hClient); + pKernelRc->watchdog.bHandleValid = NV_FALSE; } portMemFree(pParams); @@ -1417,4 +1418,11 @@ krcWatchdogWriteNotifierToGpfifo_IMPL SLI_LOOP_END; } +NV_STATUS krcWatchdogGetClientHandle(KernelRc *pKernelRc, NvHandle *phClient) +{ + if (!pKernelRc->watchdog.bHandleValid) + return NV_ERR_INVALID_STATE; + *phClient = pKernelRc->watchdog.hClient; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c b/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c index 733732e05..c18692063 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c +++ b/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c @@ -29,6 +29,7 @@ #include "rmapi/client.h" #include <class/cl90e6.h> +#include <class/cl90e7.h> NV_STATUS @@ -82,6 +83,15 @@ genapiControl_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { + if (RES_GET_EXT_CLASS_ID(pGenericEngineApi) == GF100_SUBDEVICE_INFOROM) + { + OBJGPU *pGpu = GPU_RES_GET_GPU(pGenericEngineApi); + OBJINFOROM *pInforom = GPU_GET_INFOROM(pGpu); + if (!IS_GSP_CLIENT(pGpu) && pInforom == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + } return gpuresControl_IMPL(staticCast(pGenericEngineApi, GpuResource), pCallContext, pParams); diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index e79503886..54d4bf93a 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -3893,3 +3893,41 @@ NvBool gpumgrIsSafeToReadGpuInfo(void) // return rmapiLockIsOwner() || (rmGpuLocksGetOwnedMask() != 0); } + +// +// Workaround for Bug 3809777. This is a HW bug happening in Ampere and +// Ada GPU's. For these GPU's, after device reset, CRS (Configuration Request +// Retry Status) is being released without waiting for GFW boot completion. +// MSI-X capability in the config space may be inconsistent when GFW boot +// is in progress, so this function checks if MSI-X is allowed. +// For Hopper and above, the CRS will be released after +// GFW boot completion, so the WAR is not needed. +// The bug will be exposed only when GPU is running inside guest in +// pass-through mode. +// +NvBool gpumgrIsDeviceMsixAllowed +( + RmPhysAddr bar0BaseAddr, + NvU32 pmcBoot1, + NvU32 pmcBoot42 +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + NvU32 chipArch; + + if ((hypervisorGetHypervisorType(pHypervisor) == OS_HYPERVISOR_UNKNOWN) || + !FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _REAL, pmcBoot1)) + { + return NV_TRUE; + } + + chipArch = DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42); + if ((chipArch != NV_PMC_BOOT_42_ARCHITECTURE_AD100) && + (chipArch != NV_PMC_BOOT_42_ARCHITECTURE_GA100)) + { + return NV_TRUE; + } + + return gpuIsMsixAllowed_TU102(bar0BaseAddr); +} diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c index 7ed5c2cfc..e8d71808e 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c @@ -93,6 +93,7 @@ _memoryfabricValidatePhysMem MEMORY_DESCRIPTOR *pPhysMemDesc; NvU64 physPageSize; NV_STATUS status; + Memory *pMemory; if (hPhysMem == 0) { @@ -110,7 +111,19 @@ _memoryfabricValidatePhysMem return status; } - pPhysMemDesc = (dynamicCast(pPhysmemRef->pResource, Memory))->pMemDesc; + pMemory = dynamicCast(pPhysmemRef->pResource, Memory); + if (pMemory == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); + return NV_ERR_INVALID_OBJECT_HANDLE; + } + + pPhysMemDesc = pMemory->pMemDesc; + if (pPhysMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); + return NV_ERR_INVALID_OBJECT_HANDLE; + } if ((pOwnerGpu != pPhysMemDesc->pGpu) || !memmgrIsApertureSupportedByFla_HAL(pOwnerGpu, pMemoryManager, @@ -748,7 +761,7 @@ memoryfabricConstruct_IMPL NV0041_CTRL_GET_SURFACE_INFO_PARAMS surfaceInfoParam = {0}; surfaceInfo[0].index = NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE; - surfaceInfo[1].index = NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE; + surfaceInfo[1].index = NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS; surfaceInfoParam.surfaceInfoListSize = 2; surfaceInfoParam.surfaceInfoList = NvP64_VALUE(&surfaceInfo); @@ -765,7 +778,14 @@ memoryfabricConstruct_IMPL } pMemdescData->physAttrs.addressSpace = surfaceInfo[0].data; - pMemdescData->physAttrs.compressionCoverage = surfaceInfo[1].data; + // + // TODO: Bug 4322867: use NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR + // instead of NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE. + // NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE is buggy and + // will be removed soon. + // + pMemdescData->physAttrs.compressionCoverage = + (surfaceInfo[1].data & NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR) ? 0x1 : 0x0; mapFlags |= bReadOnly ? FABRIC_VASPACE_MAP_FLAGS_READ_ONLY : 0; diff --git a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c index cf1308f07..e9969c37a 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c @@ -218,7 +218,7 @@ _memMulticastFabricDescriptorDequeueWaitUnderLock } } -NV_STATUS +static NV_STATUS _memMulticastFabricGpuInfoAddUnderLock ( MemoryMulticastFabric *pMemoryMulticastFabric, @@ -1027,8 +1027,8 @@ memorymulticastfabricConstruct_IMPL return status; } -NV_STATUS -memorymulticastfabricCtrlAttachGpu_IMPL +static NV_STATUS +_memorymulticastfabricCtrlAttachGpu ( MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams @@ -1041,14 +1041,13 @@ memorymulticastfabricCtrlAttachGpu_IMPL OBJGPU *pGpu; FABRIC_VASPACE *pFabricVAS; NvU64 gpuProbeHandle; - MEM_MULTICAST_FABRIC_GPU_INFO *pNode = \ - listTail(&pMulticastFabricDesc->gpuInfoList); + MEM_MULTICAST_FABRIC_GPU_INFO *pNode = NULL; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); if (pParams->flags != 0) { NV_PRINTF(LEVEL_ERROR, "flags passed for attach mem must be zero\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; + return NV_ERR_INVALID_ARGUMENT; } // Check if the Multicast FLA object has any additional slots for GPUs @@ -1070,10 +1069,19 @@ memorymulticastfabricCtrlAttachGpu_IMPL { NV_PRINTF(LEVEL_ERROR, "Multicast attach not supported on Windows/CC/vGPU modes\n"); - status = NV_ERR_NOT_SUPPORTED; - goto fail; + return NV_ERR_NOT_SUPPORTED; + } + + status = _memMulticastFabricGpuInfoAddUnderLock(pMemoryMulticastFabric, + pCallContext->pControlParams); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to populate GPU info\n"); + return status; } + pNode = listTail(&pMulticastFabricDesc->gpuInfoList); + status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfoKernel, &gpuProbeHandle); if (status != NV_OK) @@ -1119,6 +1127,26 @@ fail: return status; } +NV_STATUS +memorymulticastfabricCtrlAttachGpu_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlAttachGpu(pMemoryMulticastFabric, + pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} + static MEM_MULTICAST_FABRIC_GPU_INFO* _memorymulticastfabricGetAttchedGpuInfo ( @@ -1148,8 +1176,8 @@ _memorymulticastfabricGetAttchedGpuInfo return NULL; } -NV_STATUS -memorymulticastfabricCtrlDetachMem_IMPL +static NV_STATUS +_memorymulticastfabricCtrlDetachMem ( MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_DETACH_MEM_PARAMS *pParams @@ -1189,6 +1217,26 @@ memorymulticastfabricCtrlDetachMem_IMPL return NV_OK; } +NV_STATUS +memorymulticastfabricCtrlDetachMem_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_DETACH_MEM_PARAMS *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlDetachMem(pMemoryMulticastFabric, + pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} + static NV_STATUS _memorymulticastfabricValidatePhysMem ( @@ -1202,6 +1250,7 @@ _memorymulticastfabricValidatePhysMem MEMORY_DESCRIPTOR *pPhysMemDesc; NvU64 physPageSize; NV_STATUS status; + Memory *pMemory; status = serverutilGetResourceRef(RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), hPhysMem, &pPhysmemRef); @@ -1213,7 +1262,19 @@ _memorymulticastfabricValidatePhysMem return status; } - pPhysMemDesc = (dynamicCast(pPhysmemRef->pResource, Memory))->pMemDesc; + pMemory = dynamicCast(pPhysmemRef->pResource, Memory); + if (pMemory == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); + return NV_ERR_INVALID_OBJECT_HANDLE; + } + + pPhysMemDesc = pMemory->pMemDesc; + if (pPhysMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); + return NV_ERR_INVALID_OBJECT_HANDLE; + } if (memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM || (pAttachedGpu != pPhysMemDesc->pGpu)) @@ -1237,8 +1298,8 @@ _memorymulticastfabricValidatePhysMem return NV_OK; } -NV_STATUS -memorymulticastfabricCtrlAttachMem_IMPL +static NV_STATUS +_memorymulticastfabricCtrlAttachMem ( MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams @@ -1342,6 +1403,26 @@ freeDupedMem: return status; } +NV_STATUS +memorymulticastfabricCtrlAttachMem_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlAttachMem(pMemoryMulticastFabric, + pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} + void memorymulticastfabricDestruct_IMPL ( @@ -1393,8 +1474,8 @@ memorymulticastfabricCopyConstruct_IMPL return NV_OK; } -NV_STATUS -memorymulticastfabricCtrlGetInfo_IMPL +static NV_STATUS +_memorymulticastfabricCtrlGetInfo ( MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_GET_INFO_PARAMS *pParams @@ -1414,6 +1495,26 @@ memorymulticastfabricCtrlGetInfo_IMPL } NV_STATUS +memorymulticastfabricCtrlGetInfo_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_GET_INFO_PARAMS *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlGetInfo(pMemoryMulticastFabric, + pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} + +NV_STATUS memorymulticastfabricIsReady_IMPL ( MemoryMulticastFabric *pMemoryMulticastFabric, @@ -1451,8 +1552,8 @@ memorymulticastfabricIsReady_IMPL return mcTeamStatus; } -NV_STATUS -memorymulticastfabricCtrlRegisterEvent_IMPL +static NV_STATUS +_memorymulticastfabricCtrlRegisterEvent ( MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams @@ -1467,20 +1568,23 @@ memorymulticastfabricCtrlRegisterEvent_IMPL } NV_STATUS -memorymulticastfabricControl_Prologue_IMPL +memorymulticastfabricCtrlRegisterEvent_IMPL ( - MemoryMulticastFabric *pMemoryMulticastFabric, - CALL_CONTEXT *pCallContext, - RS_RES_CONTROL_PARAMS_INTERNAL *pParams + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams ) { - RmResource *pResource = staticCast(pMemoryMulticastFabric, RmResource); + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; - // Other control calls, nothing to be validated. - if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_GPU) - return rmresControl_Prologue_IMPL(pResource, pCallContext, pParams); + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlRegisterEvent(pMemoryMulticastFabric, + pParams); - return _memMulticastFabricGpuInfoAddUnderLock(pMemoryMulticastFabric, pParams); + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; } NV_STATUS @@ -1491,7 +1595,6 @@ memorymulticastfabricControl_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV_STATUS status = NV_OK; if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_GPU) @@ -1522,14 +1625,13 @@ memorymulticastfabricControl_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); } - fabricMulticastFabricOpsMutexAcquire(pFabric); - - status = resControl_IMPL(staticCast(pMemoryMulticastFabric, RsResource), - pCallContext, pParams); - - fabricMulticastFabricOpsMutexRelease(pFabric); - - return status; + // + // Note: GPU lock(s) is required for some control calls. Thus, it is + // incorrect to take the leaf lock here. resControl_IMPL() attempts to + // acquire the GPU locks before it calls the control call body. + // + return resControl_IMPL(staticCast(pMemoryMulticastFabric, RsResource), + pCallContext, pParams); } NvBool diff --git a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c index d622daad6..e72a38222 100644 --- a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c +++ b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c @@ -209,17 +209,14 @@ allocUpstreamTopPool { PMA_ALLOCATION_OPTIONS allocOptions = {0}; RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo; - NvU64 i; - NvU64 *pPageStore = portMemAllocNonPaged(sizeof(NvU64) * numPages); - NV_STATUS status = NV_OK; + NvU64 i, pageBegin; + NV_STATUS status; NV_ASSERT_OR_RETURN(NULL != pCtx, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(NULL != pPage, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(NULL != pPageStore, NV_ERR_NO_MEMORY); pMemReserveInfo = (RM_POOL_ALLOC_MEM_RESERVE_INFO *)pCtx; - allocOptions.flags = PMA_ALLOCATE_PINNED | PMA_ALLOCATE_PERSISTENT | PMA_ALLOCATE_FORCE_ALIGNMENT; - allocOptions.alignment = PMA_CHUNK_SIZE_64K; + allocOptions.flags = PMA_ALLOCATE_PINNED | PMA_ALLOCATE_PERSISTENT; if (pMemReserveInfo->bSkipScrub) { @@ -230,24 +227,56 @@ allocUpstreamTopPool { allocOptions.flags |= PMA_ALLOCATE_PROTECTED_REGION; } - - NV_ASSERT_OK_OR_GOTO(status, - pmaAllocatePages(pMemReserveInfo->pPma, - numPages, - pageSize, - &allocOptions, - pPageStore), - free_mem); + + // + // Some tests fail page table and directory allocation when close to all FB is allocated if we allocate contiguously. + // For now, we're special-casing this supported pageSize and allocating the 64K pages discontigously. + // TODO: Unify the codepaths so that all pages allocated discontiguously (not currently supported by PMA) + // + if (pageSize == PMA_CHUNK_SIZE_64K) + { + NvU64 *pPageStore = portMemAllocNonPaged(sizeof(NvU64) * numPages); + NV_STATUS status = NV_OK; + NV_ASSERT_OK_OR_GOTO(status, + pmaAllocatePages(pMemReserveInfo->pPma, + numPages, + pageSize, + &allocOptions, + pPageStore), + free_mem); + + for (i = 0; i < numPages; i++) + { + pPage[i].address = pPageStore[i]; + pPage[i].pMetadata = NULL; + } +free_mem: + portMemFree(pPageStore); + return status; + } + + allocOptions.flags |= PMA_ALLOCATE_CONTIGUOUS; for (i = 0; i < numPages; i++) { - pPage[i].address = pPageStore[i]; + NV_ASSERT_OK_OR_GOTO(status, pmaAllocatePages(pMemReserveInfo->pPma, + pageSize / PMA_CHUNK_SIZE_64K, + PMA_CHUNK_SIZE_64K, + &allocOptions, + &pageBegin), err); + pPage[i].address = pageBegin; pPage[i].pMetadata = NULL; } -free_mem: - portMemFree(pPageStore); - return status; + return NV_OK; +err: + for (;i > 0; i--) + { + NvU32 flags = pMemReserveInfo->bSkipScrub ? PMA_FREE_SKIP_SCRUB : 0; + pmaFreePages(pMemReserveInfo->pPma, &pPage[i - 1].address, 1, + pageSize, flags); + } + return status; } /*! diff --git a/src/nvidia/src/kernel/mem_mgr/video_mem.c b/src/nvidia/src/kernel/mem_mgr/video_mem.c index c0e3327c1..a894c76de 100644 --- a/src/nvidia/src/kernel/mem_mgr/video_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/video_mem.c @@ -562,6 +562,14 @@ vidmemConstruct_IMPL goto done; } + if (FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, _DEFAULT, pAllocData->attr)) + { + pAllocData->attr = + FLD_SET_DRF_NUM(OS32, _ATTR, _PHYSICALITY, + pDevice->defaultVidmemPhysicalityOverride, + pAllocData->attr); + } + NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, stdmemValidateParams(pGpu, hClient, pAllocData)); NV_CHECK_OR_RETURN(LEVEL_WARNING, DRF_VAL(OS32, _ATTR, _LOCATION, pAllocData->attr) == NVOS32_ATTR_LOCATION_VIDMEM && diff --git a/src/nvidia/src/kernel/platform/chipset/chipset.c b/src/nvidia/src/kernel/platform/chipset/chipset.c index 315aedb1b..3c7da8cd7 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -82,6 +82,12 @@ clInitPropertiesFromRegistry_IMPL(OBJGPU *pGpu, OBJCL *pCl) } } + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC, &data32) == NV_OK) + && (data32 == NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES)) + { + pCl->setProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC, NV_TRUE); + } + pOS->osQADbgRegistryInit(pOS); } diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_info.c b/src/nvidia/src/kernel/platform/chipset/chipset_info.c index 6a1105920..31e5601b5 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_info.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_info.c @@ -1301,6 +1301,18 @@ Arm_NeoverseN1_setupFunc return NV_OK; } +// Ampere AmpereOne Setup Function +static NV_STATUS +Ampere_AmpereOne_setupFunc +( + OBJCL *pCl +) +{ + // TODO Need to check if any more PDB properties should be set + pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); + return NV_OK; +} + void csGetInfoStrings ( diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index 267ba0789..f51bb8451 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -186,6 +186,7 @@ void RmInitCpuInfo(void) break; case AARCH64_VENDOR_PART(ARM, NEOVERSE_N2): case AARCH64_VENDOR_PART(ARM, NEOVERSE_V2): + case AARCH64_VENDOR_PART(AMPERE_2, AMPEREONE): pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC; break; default: diff --git a/src/nvidia/src/kernel/platform/cpu_arm_def.h b/src/nvidia/src/kernel/platform/cpu_arm_def.h index 185777505..3f658e771 100644 --- a/src/nvidia/src/kernel/platform/cpu_arm_def.h +++ b/src/nvidia/src/kernel/platform/cpu_arm_def.h @@ -57,6 +57,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_IMPLEMENTER_FUJITSU 0x46 #define CP_MIDR_IMPLEMENTER_PHYTIUM 0x70 #define CP_MIDR_IMPLEMENTER_AMPERE 0x81 +#define CP_MIDR_IMPLEMENTER_AMPERE_2 0XC0 #define CP_CSSELR_DATA_CACHE 0 #define CP_CSSELR_INSTRUCTION_CACHE 1 @@ -91,6 +92,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1 #define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49 +#define CP_MIDR_PRIMARY_PART_NUM_AMPEREONE 0xac3 // Cache Size Identification Register #define CP_CCSIDR "ccsidr_el1" diff --git a/src/nvidia/src/kernel/rmapi/alloc_free.c b/src/nvidia/src/kernel/rmapi/alloc_free.c index 0dd98174f..b6981987f 100644 --- a/src/nvidia/src/kernel/rmapi/alloc_free.c +++ b/src/nvidia/src/kernel/rmapi/alloc_free.c @@ -913,7 +913,8 @@ serverAllocResourceUnderLock callContext.pLockInfo = pRmAllocParams->pLockInfo; callContext.secInfo = *pRmAllocParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); NV_RM_RPC_ALLOC_OBJECT(pGpu, pRmAllocParams->hClient, pRmAllocParams->hParent, @@ -922,7 +923,7 @@ serverAllocResourceUnderLock pRmAllocParams->pAllocParams, pRmAllocParams->paramsSize, status); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; diff --git a/src/nvidia/src/kernel/rmapi/client.c b/src/nvidia/src/kernel/rmapi/client.c index d4f5cf86d..c253a54fe 100644 --- a/src/nvidia/src/kernel/rmapi/client.c +++ b/src/nvidia/src/kernel/rmapi/client.c @@ -82,6 +82,8 @@ rmclientConstruct_IMPL pClient->pSecurityToken = NULL; pClient->pOSInfo = pSecInfo->clientOSInfo; + pClient->cachedPrivilege = pSecInfo->privLevel; + // TODO: Revisit in M2, see GPUSWSEC-1176 if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) { @@ -96,10 +98,10 @@ rmclientConstruct_IMPL else { pClient->ProcID = osGetCurrentProcess(); + if (pClient->cachedPrivilege <= RS_PRIV_LEVEL_USER_ROOT) + pClient->pOsPidInfo = osGetPidInfo(); } - pClient->cachedPrivilege = pSecInfo->privLevel; - // Set user-friendly client name from current process osGetCurrentProcessName(pClient->name, NV_PROC_NAME_MAX_LENGTH); @@ -128,7 +130,7 @@ rmclientConstruct_IMPL { NV_PRINTF(LEVEL_WARNING, "NVRM_RPC: Failed to set host client resource handle range %x\n", status); - return status; + goto out; } } @@ -139,7 +141,7 @@ rmclientConstruct_IMPL { NV_PRINTF(LEVEL_WARNING, "Failed to set host client restricted resource handle range. Status=%x\n", status); - return status; + goto out; } if (!rmGpuLockIsOwner()) @@ -148,7 +150,7 @@ rmclientConstruct_IMPL if ((status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_CLIENT)) != NV_OK) { NV_ASSERT(0); - return status; + goto out; } bReleaseLock = NV_TRUE; } @@ -206,6 +208,13 @@ rmclientConstruct_IMPL if (status == NV_OK && pParams->pAllocParams != NULL) *(NvHandle*)(pParams->pAllocParams) = pParams->hClient; +out: + if (status != NV_OK) + { + osPutPidInfo(pClient->pOsPidInfo); + pClient->pOsPidInfo = NULL; + } + return status; } @@ -230,6 +239,8 @@ rmclientDestruct_IMPL // Free any association of the client with existing third-party p2p object CliUnregisterFromThirdPartyP2P(pClient); + osPutPidInfo(pClient->pOsPidInfo); + // // Free all of the devices of the client (do it in reverse order to // facilitate tear down of things like ctxdmas, etc) diff --git a/src/nvidia/src/kernel/rmapi/client_resource.c b/src/nvidia/src/kernel/rmapi/client_resource.c index 2c443a2d7..af8768ac4 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource.c +++ b/src/nvidia/src/kernel/rmapi/client_resource.c @@ -4148,9 +4148,10 @@ cliresCtrlCmdClientShareObject_IMPL callContext.pResourceRef = pObjectRef; callContext.secInfo = pCallContext->secInfo; - resservSwapTlsCallContext(&pOldCallContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldCallContext, &callContext)); + status = clientShareResource(pClient, pObjectRef, pSharePolicy, &callContext); - resservRestoreTlsCallContext(pOldCallContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldCallContext)); if (status != NV_OK) return status; diff --git a/src/nvidia/src/kernel/rmapi/control.c b/src/nvidia/src/kernel/rmapi/control.c index 48c7ddc17..c202ebec7 100644 --- a/src/nvidia/src/kernel/rmapi/control.c +++ b/src/nvidia/src/kernel/rmapi/control.c @@ -274,7 +274,9 @@ serverControlApiCopyIn rmStatus = embeddedParamCopyIn(pEmbeddedParamCopies, pRmCtrlParams); if (rmStatus != NV_OK) + { return rmStatus; + } pCookie->bFreeEmbeddedCopy = NV_TRUE; return NV_OK; @@ -487,8 +489,9 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams } // error check parameters - if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) || - ((paramsSize == 0) && (pUserParams != (NvP64) 0))) + if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) || + ((paramsSize == 0) && (pUserParams != (NvP64) 0)) + ) { NV_PRINTF(LEVEL_WARNING, "bad params: ptr " NvP64_fmt " size: 0x%x\n", pUserParams, paramsSize); @@ -519,6 +522,7 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams } getCtrlInfoStatus = rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight); + if (getCtrlInfoStatus == NV_OK) { // @@ -1013,7 +1017,7 @@ _rmapiControlWithSecInfoTlsIRQL NV_STATUS status; THREAD_STATE_NODE threadState; - NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; + NvU8 stackAllocator[2*TLS_ISR_ALLOCATOR_SIZE]; PORT_MEM_ALLOCATOR* pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); tlsIsrInit(pIsrAllocator); diff --git a/src/nvidia/src/kernel/rmapi/event.c b/src/nvidia/src/kernel/rmapi/event.c index 5ebc0854b..0592fbe4e 100644 --- a/src/nvidia/src/kernel/rmapi/event.c +++ b/src/nvidia/src/kernel/rmapi/event.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -285,9 +285,11 @@ NV_STATUS notifyUnregisterEvent_IMPL // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), // do an RPC to the host to do the hardware update. // - if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + if ( + !(IS_GSP_CLIENT(pGpu) && (pNotifierRef->internalClassId == classId(KernelHostVgpuDeviceApi))) && + (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || (IS_GSP_CLIENT(pGpu) && pNotifierRef->internalClassId != classId(ContextDma)) || - (IS_VIRTUAL_WITH_SRIOV(pGpu) && !((*ppEventNotification)->bNonStallIntrEvent))) + (IS_VIRTUAL_WITH_SRIOV(pGpu) && !((*ppEventNotification)->bNonStallIntrEvent)))) { // // In SR-IOV enabled systems, nonstall events are registered diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c index 60211a929..4060ca829 100644 --- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c +++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c @@ -3446,8 +3446,6 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_MC) || (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_V2)) { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); - isPeerSupported = NV_TRUE; pPeerGpu = pAdjustedMemDesc->pGpu; peerId = BUS_INVALID_PEER; @@ -3462,10 +3460,21 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, if (pPeerGpu != NULL) { - if ((pKernelNvlink != NULL) && - knvlinkIsNvlinkP2pSupported(pMappingGpu, pKernelNvlink, pPeerGpu)) + if (IS_VIRTUAL_WITH_SRIOV(pMappingGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pMappingGpu)) + { + peerId = kbusGetNvlinkPeerId_HAL(pMappingGpu, + GPU_GET_KERNEL_BUS(pMappingGpu), + pPeerGpu); + } + else { - peerId = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); + if ((pKernelNvlink != NULL) && + knvlinkIsNvlinkP2pSupported(pMappingGpu, pKernelNvlink, pPeerGpu)) + { + peerId = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); + } } } else diff --git a/src/nvidia/src/kernel/rmapi/resource_list.h b/src/nvidia/src/kernel/rmapi/resource_list.h index b4809d5c1..0e0d4e6a1 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list.h +++ b/src/nvidia/src/kernel/rmapi/resource_list.h @@ -624,6 +624,16 @@ RS_ENTRY( /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( + /* External Class */ GF100_SUBDEVICE_INFOROM, + /* Internal Class */ GenericEngineApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( /* External Class */ NV01_TIMER, /* Internal Class */ TimerApi, /* Multi-Instance */ NV_FALSE, diff --git a/src/nvidia/src/kernel/rmapi/rmapi_cache.c b/src/nvidia/src/kernel/rmapi/rmapi_cache.c index 6746e8743..4507bd78b 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_cache.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_cache.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/rmapi/rmapi_utils.c b/src/nvidia/src/kernel/rmapi/rmapi_utils.c index 8eda73e61..61d0e3921 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_utils.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_utils.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/libraries/crashcat/crashcat_engine.c b/src/nvidia/src/libraries/crashcat/crashcat_engine.c index 480f4c371..573b60935 100644 --- a/src/nvidia/src/libraries/crashcat/crashcat_engine.c +++ b/src/nvidia/src/libraries/crashcat/crashcat_engine.c @@ -142,6 +142,7 @@ static CrashCatBufferDescriptor *_crashcatEngineCreateBufferDescriptor portMemSet(pBufDesc, 0, sizeof(*pBufDesc)); + pBufDesc->bRegistered = NV_FALSE; pBufDesc->aperture = aperture; pBufDesc->physOffset = offset; pBufDesc->size = size; @@ -315,6 +316,8 @@ void *crashcatEngineMapCrashBuffer_IMPL // if (!pBufDesc->bRegistered) _crashcatEngineDestroyBufferDescriptor(pCrashCatEng, pBufDesc); + + return NULL; } return pBufDesc->pMapping; diff --git a/src/nvidia/src/libraries/crashcat/crashcat_report.c b/src/nvidia/src/libraries/crashcat/crashcat_report.c index 12ee09835..3d55aadad 100644 --- a/src/nvidia/src/libraries/crashcat/crashcat_report.c +++ b/src/nvidia/src/libraries/crashcat/crashcat_report.c @@ -72,7 +72,7 @@ void crashcatReportLog_IMPL(CrashCatReport *pReport) crashcatReportLogRiscv64GprState_HAL(pReport); break; case NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE: - crashcatReportLogRiscv64Trace_HAL(pReport); + crashcatReportLogRiscv64Traces_HAL(pReport); break; case NV_CRASHCAT_PACKET_TYPE_IO32_STATE: crashcatReportLogIo32State_HAL(pReport); diff --git a/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c b/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c index 0401faa68..818afb698 100644 --- a/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c +++ b/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c @@ -45,7 +45,8 @@ static NV_INLINE NvCrashCatPacketHeader_V1 crashcatReadPacketHeader(void *pHdr) void crashcatReportDestruct_V1(CrashCatReport *pReport) { - portMemFree(pReport->v1.pRiscv64Trace); + portMemFree(pReport->v1.pRiscv64StackTrace); + portMemFree(pReport->v1.pRiscv64PcTrace); portMemFree(pReport->v1.pIo32State); } @@ -242,20 +243,54 @@ void *crashcatReportExtractRiscv64Trace_V1 if (!crashcatPacketHeaderValid(hdr) || (crashcatPacketHeaderFormatVersion(hdr) != NV_CRASHCAT_PACKET_FORMAT_VERSION_1)) { - NV_PRINTF(LEVEL_WARNING, "Invalid V1 stack trace header 0x%" NvU64_fmtx "\n", hdr); + NV_PRINTF(LEVEL_WARNING, "Invalid V1 trace packet header 0x%" NvU64_fmtx "\n", hdr); return pReportBytes; } - // Allocate the buffer for the stack trace + // Allocate the buffer for the trace const NvU32 payloadSize = crashcatPacketHeaderPayloadSize(hdr); const NvLength sizeBytes = sizeof(NvCrashCatRiscv64Trace_V1) + payloadSize; NV_CHECK_OR_RETURN(LEVEL_ERROR, payloadSize > 0, pReportBytes); - pReport->v1.pRiscv64Trace = portMemAllocNonPaged(sizeBytes); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pReport->v1.pRiscv64Trace != NULL, pReportBytes); + NvCrashCatRiscv64Trace_V1 *pRiscv64Trace = portMemAllocNonPaged(sizeBytes); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pRiscv64Trace != NULL, pReportBytes); - portMemCopy(pReport->v1.pRiscv64Trace, sizeBytes, pReportBytes, sizeBytes); - pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE); + portMemCopy(pRiscv64Trace, sizeBytes, pReportBytes, sizeBytes); + + // + // We support both stack and PC traces in one report. They share a tag bit (will be set if + // either are present). + // + switch (crashcatRiscv64TraceV1Type(pRiscv64Trace)) + { + case NV_CRASHCAT_TRACE_TYPE_STACK: + if (pReport->v1.pRiscv64StackTrace != NULL) + { + NV_PRINTF(LEVEL_WARNING, + "Only one stack trace packet is supported, discarding the old one\n"); + portMemFree(pReport->v1.pRiscv64StackTrace); + } + + pReport->v1.pRiscv64StackTrace = pRiscv64Trace; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE); + break; + case NV_CRASHCAT_TRACE_TYPE_NVRVTB: + if (pReport->v1.pRiscv64PcTrace != NULL) + { + NV_PRINTF(LEVEL_WARNING, + "Only one PC trace packet is supported, discarding the old one\n"); + portMemFree(pReport->v1.pRiscv64PcTrace); + } + + pReport->v1.pRiscv64PcTrace = pRiscv64Trace; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE); + break; + default: + NV_PRINTF(LEVEL_WARNING, "Unknown CrashCat trace type (0x%x), discarding\n", + crashcatRiscv64TraceV1Type(pRiscv64Trace)); + portMemFree(pRiscv64Trace); + break; + } return (void *)((NvUPtr)pReportBytes + sizeBytes); } @@ -392,9 +427,12 @@ static NV_INLINE const char *crashcatRiscv64TraceTypeToString_V1(NV_CRASHCAT_TRA } } -void crashcatReportLogRiscv64Trace_V1(CrashCatReport *pReport) +static void crashcatReportLogRiscv64Trace_V1 +( + CrashCatReport *pReport, + NvCrashCatRiscv64Trace_V1 *pTraceV1 +) { - NvCrashCatRiscv64Trace_V1 *pTraceV1 = pReport->v1.pRiscv64Trace; NvU16 entries = crashcatPacketHeaderPayloadSize(pTraceV1->header) >> 3; NV_CRASHCAT_TRACE_TYPE traceType = crashcatRiscv64TraceV1Type(pTraceV1); @@ -402,8 +440,59 @@ void crashcatReportLogRiscv64Trace_V1(CrashCatReport *pReport) CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "%s Trace:", crashcatRiscv64TraceTypeToString_V1(traceType)); - for (NvU16 i = 0; i < entries; i++) - CRASHCAT_REPORT_LOG_DATA(pReport, "0x%" NvU64_fmtx, pTraceV1->addr[i]); + if (traceType == NV_CRASHCAT_TRACE_TYPE_NVRVTB) + { + // PC traces are too long with each entry on its own line + const NvU8 ENTRIES_PER_LINE = 5; + NvU16 idx; + for (idx = 0; idx < (entries / ENTRIES_PER_LINE) * ENTRIES_PER_LINE; + idx += ENTRIES_PER_LINE) + { + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " " + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2], + pTraceV1->addr[idx + 3], pTraceV1->addr[idx + 4]); + } + + switch (entries - idx) + { + case 4: + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " " + "0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2], + pTraceV1->addr[idx + 3]); + break; + case 3: + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2]); + break; + case 2: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1]); + break; + case 1: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx, pTraceV1->addr[idx + 0]); + break; + default: + break; + } + } + else + { + for (NvU16 idx = 0; idx < entries; idx++) + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx, pTraceV1->addr[idx]); + } +} + +void crashcatReportLogRiscv64Traces_V1(CrashCatReport *pReport) +{ + if (pReport->v1.pRiscv64StackTrace != NULL) + crashcatReportLogRiscv64Trace_V1(pReport, pReport->v1.pRiscv64StackTrace); + if (pReport->v1.pRiscv64PcTrace != NULL) + crashcatReportLogRiscv64Trace_V1(pReport, pReport->v1.pRiscv64PcTrace); } static NV_INLINE const char *crashcatIo32ApertureToString_V1(NV_CRASHCAT_IO_APERTURE aperture) diff --git a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c index aa9c3d6e0..be64974ec 100644 --- a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c +++ b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c @@ -69,7 +69,11 @@ void crashcatReportLogReporter_V1_GENERIC(CrashCatReport *pReport) NvCrashCatNvriscvUcodeId ucodeId = crashcatReportV1ReporterUcodeId(pReportV1); NV_CRASHCAT_RISCV_MODE riscvMode = crashcatReportV1ReporterMode(pReportV1); - crashcatEnginePrintf(pReport->pEngine, NV_FALSE, + // + // Though this is technically not a separate packet, we use the CRASHCAT_REPORT_LOG_PACKET_TYPE + // macro to get the correct prefix/indentation for the reporter information. + // + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by partition:%u ucode:%u [%c-mode] version:%u @ %u", partition, ucodeId, crashcatReportModeToChar_GENERIC(riscvMode), crashcatReportV1ReporterVersion(pReportV1), diff --git a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c index 0720c92ae..51c038a6d 100644 --- a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c +++ b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c @@ -114,10 +114,13 @@ void crashcatReportLogReporter_V1_LIBOS2(CrashCatReport *pReport) NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; NvU8 taskId = crashcatReportV1ReporterLibos2TaskId(pReportV1); + // + // Though this is technically not a separate packet, we use the CRASHCAT_REPORT_LOG_PACKET_TYPE + // macro to get the correct prefix/indentation for the reporter information. + // if (taskId == NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS2_TASK_ID_UNSPECIFIED) { - crashcatEnginePrintf(pReport->pEngine, NV_FALSE, - "Reported by libos kernel v%u.%u [%u] @ %u", + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by libos kernel v%u.%u [%u] @ %u", crashcatReportV1ReporterVersionLibos2Major(pReportV1), crashcatReportV1ReporterVersionLibos2Minor(pReportV1), crashcatReportV1ReporterVersionLibos2Cl(pReportV1), @@ -125,8 +128,7 @@ void crashcatReportLogReporter_V1_LIBOS2(CrashCatReport *pReport) } else { - crashcatEnginePrintf(pReport->pEngine, NV_FALSE, - "Reported by libos task:%u v%u.%u [%u] @ ts:%u", + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by libos task:%u v%u.%u [%u] @ ts:%u", taskId, crashcatReportV1ReporterVersionLibos2Major(pReportV1), crashcatReportV1ReporterVersionLibos2Minor(pReportV1), crashcatReportV1ReporterVersionLibos2Cl(pReportV1), diff --git a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c new file mode 100644 index 000000000..d19b21caf --- /dev/null +++ b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c @@ -0,0 +1,149 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_report.h" +#include "crashcat/crashcat_engine.h" +#include "libos_v3_crashcat.h" +#include "utils/nvprintf.h" +#include "nv-crashcat-decoder.h" + +static inline const char *crashcatReportModeToString_LIBOS3(NV_CRASHCAT_RISCV_MODE mode) +{ + switch (mode) + { + case NV_CRASHCAT_RISCV_MODE_M: + return MAKE_NV_PRINTF_STR("monitor"); + case NV_CRASHCAT_RISCV_MODE_S: + return MAKE_NV_PRINTF_STR("kernel"); + case NV_CRASHCAT_RISCV_MODE_U: + return MAKE_NV_PRINTF_STR("task"); + default: + return MAKE_NV_PRINTF_STR("unspecified"); + } +} + +static inline const char *crashcatReportPanicReasonToString_LIBOS3(LibosPanicReason reason) +{ +#define LIBOS_PANIC_REASON_CASE(reason, str) \ + case LibosPanicReason ## reason: return MAKE_NV_PRINTF_STR(str) + + switch (reason) + { + LIBOS_PANIC_REASON_CASE(UnhandledState, "unhandled state"); + LIBOS_PANIC_REASON_CASE(InvalidConfiguration, "invalid configuration"); + LIBOS_PANIC_REASON_CASE(FatalHardwareError, "fatal hardware error"); + LIBOS_PANIC_REASON_CASE(InsufficientResources, "insufficient resources"); + LIBOS_PANIC_REASON_CASE(Timeout, "timeout"); + LIBOS_PANIC_REASON_CASE(EnvCallFailed, "environment call failed"); + LIBOS_PANIC_REASON_CASE(AsanMemoryError, "asan memory error detected"); + LIBOS_PANIC_REASON_CASE(ProgrammingError, "programming error"); + LIBOS_PANIC_REASON_CASE(AssertionFailed, "condition failed"); + LIBOS_PANIC_REASON_CASE(TrapKernelPanic, "unhandled trap"); + LIBOS_PANIC_REASON_CASE(TrapInstruction, "instruction access fault"); + default: return MAKE_NV_PRINTF_STR("unknown error"); + } +} + +void crashcatReportLogSource_V1_LIBOS3(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + + NvU8 taskId = crashcatReportV1SourceLibos3TaskId(pReportV1); + NvCrashCatNvriscvPartition sourcePartition = crashcatReportV1ReporterPartition(pReportV1); + NvCrashCatNvriscvUcodeId sourceUcodeId = crashcatReportV1ReporterUcodeId(pReportV1); + +#define CRASHCAT_LOG_LIBOS3_SOURCE(fmt, ...) \ + if (taskId == NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID_UNSPECIFIED) \ + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, fmt ", partition:%u#%u", \ + __VA_ARGS__, sourcePartition, sourceUcodeId); \ + else \ + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, fmt ", partition:%u#%u, task:%u", \ + __VA_ARGS__, sourcePartition, sourceUcodeId, taskId) + + const char *pModeStr = crashcatReportModeToString_LIBOS3(crashcatReportV1SourceMode(pReportV1)); + switch (crashcatReportV1SourceCauseType(pReportV1)) + { + case NV_CRASHCAT_CAUSE_TYPE_EXCEPTION: + { + // Kernel or task unhandled exception - the sourceData is the xcause value + NvU64 xcause = pReportV1->sourceData; + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s exception: %s (cause:0x%" NvU64_fmtx ") @ pc:0x%" NvU64_fmtx, + pModeStr, crashcatReportRiscvCauseToString(xcause), + xcause, pReportV1->sourcePc); + break; + } + case NV_CRASHCAT_CAUSE_TYPE_TIMEOUT: + { + // Task timeout (no way for libos3 to self-report kernel timeouts) + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s timeout @ pc:0x%" NvU64_fmtx, + pModeStr, pReportV1->sourcePc); + break; + } + case NV_CRASHCAT_CAUSE_TYPE_PANIC: + { + // Kernel or task panic + LibosPanicReason reason = crashcatReportV1SourceCauseLibos3Reason(pReportV1); + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s panic: %s (%u) @ pc:0x%" NvU64_fmtx ", aux:0x%" NvU64_fmtx, + pModeStr, crashcatReportPanicReasonToString_LIBOS3(reason), reason, + pReportV1->sourcePc, pReportV1->sourceData); + break; + } + } +} + +void crashcatReportLogReporter_V1_LIBOS3(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + NvU8 taskId = crashcatReportV1ReporterLibos3TaskId(pReportV1); + + // + // Though this is technically not a separate packet, we use the CRASHCAT_REPORT_LOG_PACKET_TYPE + // macro to get the correct prefix/indentation for the reporter information. + // + if (taskId == NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID_UNSPECIFIED) + { + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, + "Reported by libos partition:%u#%u kernel v%u.%u [%u] @ ts:%u", + crashcatReportV1ReporterPartition(pReportV1), + crashcatReportV1ReporterUcodeId(pReportV1), + crashcatReportV1ReporterVersionLibos3Major(pReportV1), + crashcatReportV1ReporterVersionLibos3Minor(pReportV1), + crashcatReportV1ReporterVersionLibos3Cl(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); + } + else + { + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, + "Reported by libos partition:%u#%u task:%u v%u.%u [%u] @ ts:%u", + crashcatReportV1ReporterPartition(pReportV1), + crashcatReportV1ReporterUcodeId(pReportV1), + taskId, crashcatReportV1ReporterVersionLibos3Major(pReportV1), + crashcatReportV1ReporterVersionLibos3Minor(pReportV1), + crashcatReportV1ReporterVersionLibos3Cl(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); + } +} diff --git a/src/nvidia/src/libraries/mmu/mmu_walk.c b/src/nvidia/src/libraries/mmu/mmu_walk.c index 946990b32..b9d8dfcb8 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk.c +++ b/src/nvidia/src/libraries/mmu/mmu_walk.c @@ -177,6 +177,7 @@ mmuWalkSetUserCtx MMU_WALK_USER_CTX *pUserCtx ) { + NV_ASSERT_OR_RETURN(NULL != pWalk, NV_ERR_INVALID_STATE); pWalk->pUserCtx = pUserCtx; return NV_OK; @@ -223,9 +224,12 @@ mmuWalkFindLevel ) { const MMU_WALK_LEVEL *pLevel = &pWalk->root; - while (pLevel->pFmt != pLevelFmt) + while (pLevel != NULL && pLevel->pFmt != pLevelFmt) { NvU32 subLevel; + + NV_ASSERT_OR_RETURN(pLevel->pFmt != NULL, NULL); + // Single sub-level always continues. if (1 == pLevel->pFmt->numSubLevels) { diff --git a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c index 4ff892230..d30f321c4 100644 --- a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c +++ b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c @@ -1444,6 +1444,14 @@ _portMemAllocatorCreateOnExistingBlock pAllocator->pTracking = NULL; // No tracking for this allocator pAllocator->pImpl = (PORT_MEM_ALLOCATOR_IMPL*)(pAllocator + 1); + + // + // PORT_MEM_BITVECTOR (pAllocator->pImpl) and PORT_MEM_ALLOCATOR_TRACKING (pAllocator->pImpl->tracking) + // are mutually exclusively used. + // When pAllocator->pTracking = NULL the data in pAllocator->pImpl->tracking is not used and instead + // pBitVector uses the same meory location. + // When pAllocator->pImpl->tracking there is no usage of PORT_MEM_BITVECTOR + // pBitVector = (PORT_MEM_BITVECTOR*)(pAllocator->pImpl); pBitVector->pSpinlock = pSpinlock; @@ -1544,6 +1552,10 @@ _portMemAllocatorAllocExistingWrapper { portSyncSpinlockRelease(pSpinlock); } + if (pMem == NULL) + { + PORT_MEM_PRINT_ERROR("Memory allocation failed.\n"); + } return pMem; } diff --git a/src/nvidia/src/libraries/resserv/src/rs_client.c b/src/nvidia/src/libraries/resserv/src/rs_client.c index 358061c16..6b2f34382 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_client.c +++ b/src/nvidia/src/libraries/resserv/src/rs_client.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -523,7 +523,7 @@ clientCopyResource_IMPL callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldContext, &callContext)); // // Kernel clients are allowed to dup anything, unless they request otherwise. @@ -560,7 +560,7 @@ clientCopyResource_IMPL } } - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) return status; @@ -668,9 +668,11 @@ _clientAllocResourceHelper } callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), fail); + status = resservResourceFactory(pServer->pAllocator, &callContext, pParams, &pResource); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto fail; @@ -724,6 +726,8 @@ _clientAllocResourceHelper fail: if (pResource != NULL) { + NV_STATUS callContextStatus; + RS_RES_FREE_PARAMS_INTERNAL params; pOldContext = NULL; @@ -738,11 +742,20 @@ fail: callContext.pResourceRef = pResourceRef; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); - resSetFreeParams(pResource, &callContext, ¶ms); + callContextStatus = resservSwapTlsCallContext(&pOldContext, &callContext); + if (callContextStatus == NV_OK) + { + resSetFreeParams(pResource, &callContext, ¶ms); + + objDelete(pResource); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Failed to set call context! Error: 0x%x\n", + callContextStatus); + } - objDelete(pResource); - resservRestoreTlsCallContext(pOldContext); } if (pResourceRef != NULL) @@ -798,7 +811,9 @@ clientFreeResource_IMPL if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + resSetFreeParams(pResource, &callContext, pParams); resPreDestruct(pResource); @@ -825,7 +840,7 @@ clientFreeResource_IMPL pResourceRef->pResource = NULL; - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); done: if (!pParams->bInvalidateOnly) @@ -872,9 +887,10 @@ clientUnmapMemory_IMPL if (pSecInfo != NULL) callContext.secInfo = *pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldContext, &callContext)); + status = resUnmap(pResourceRef->pResource, &callContext, pCpuMapping); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) { diff --git a/src/nvidia/src/libraries/resserv/src/rs_server.c b/src/nvidia/src/libraries/resserv/src/rs_server.c index 7e51ea063..99e7bc7e1 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_server.c +++ b/src/nvidia/src/libraries/resserv/src/rs_server.c @@ -1344,9 +1344,11 @@ serverControl } pLockInfo->pContextRef = pResourceRef->pParentRef; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = resControl(pResourceRef->pResource, &callContext, pParams); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); done: @@ -1521,7 +1523,8 @@ _serverShareResourceAccessClient callContext.pResourceRef = pResourceRef; callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); if (hClientOwner == hClientTarget) { @@ -1544,7 +1547,7 @@ _serverShareResourceAccessClient goto restore_context; restore_context: - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); // NV_PRINTF(LEVEL_INFO, "hClientOwner %x: Shared hResource: %x with hClientTarget: %x\n", // hClientOwner, pParams->hResource, hClientTarget); @@ -1631,9 +1634,11 @@ serverShareResourceAccess callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = clientShareResource(pClient, pResourceRef, pParams->pSharePolicy, &callContext); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; @@ -1735,9 +1740,11 @@ serverMap if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = resMap(pResource, &callContext, pParams, pCpuMapping); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; @@ -1910,7 +1917,9 @@ serverInterMap if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + bRestoreCallContext = NV_TRUE; status = refAddInterMapping(pMapperRef, pMappableRef, pContextRef, &pMapping); @@ -1934,7 +1943,7 @@ done: serverInterMap_Epilogue(pServer, pParams, &releaseFlags); if (bRestoreCallContext) - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) { @@ -2024,7 +2033,9 @@ serverInterUnmap if (pLockInfo->pContextRef == NULL) pLockInfo->pContextRef = pContextRef; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + bRestoreCallContext = NV_TRUE; status = serverResLock_Prologue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); @@ -2045,7 +2056,7 @@ done: serverResLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); if (bRestoreCallContext) - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); _serverUnlockClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, pParams->hClient, pLockInfo, &releaseFlags); serverTopLock_Epilogue(pServer, topLockAccess, pLockInfo, &releaseFlags); diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index f8604e09a..52751fcec 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -755,6 +755,7 @@ SRCS += src/libraries/crashcat/v1/crashcat_report_v1.c SRCS += src/libraries/crashcat/v1/crashcat_wayfinder_v1.c SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c +SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c SRCS += src/libraries/eventbuffer/eventbufferproducer.c SRCS += src/libraries/fnv_hash/fnv_hash.c SRCS += src/libraries/ioaccess/ioaccess.c diff --git a/version.mk b/version.mk index c24c6c536..249fcb0f9 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 535.43.23 +NVIDIA_VERSION = 535.43.24 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST)) |