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authorDavid Boddie <david@boddie.org.uk>2020-07-18 16:33:54 +0200
committerDavid Boddie <david@boddie.org.uk>2020-07-18 16:33:54 +0200
commit83beab8bbcbec5a219996d2118aa15bebc108e91 (patch)
treef804918a63beefa04de33e2a72030ddcae224c2d
parent012b00b7e47ed291b1f2ab07745f5a53db357c91 (diff)
Fixed case 60 which used an ARMv4 instruction regardless of version.
Fixed case 22 to avoid using the pre/post-indexing flag with non-load instructions.
-rw-r--r--utils/5l/asm.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/utils/5l/asm.c b/utils/5l/asm.c
index 53d51c45..d693eea6 100644
--- a/utils/5l/asm.c
+++ b/utils/5l/asm.c
@@ -902,13 +902,15 @@ PP = p;
r = o->param;
o1 = olr(instoffset, r, p->to.reg, p->scond);
- o2 = oprrr(ASLL, p->scond);
- o3 = oprrr(ASRA, p->scond);
r = p->to.reg;
if(p->as == AMOVB) {
+ o2 = oprrr(ASLL, p->scond & ~C_PBIT);
+ o3 = oprrr(ASRA, p->scond & ~C_PBIT);
o2 |= (24<<7)|(r)|(r<<12);
o3 |= (24<<7)|(r)|(r<<12);
} else {
+ o2 = oprrr(ASLL, p->scond);
+ o3 = oprrr(ASRA, p->scond);
o2 |= (16<<7)|(r)|(r<<12);
if(p->as == AMOVHU)
o3 = oprrr(ASRL, p->scond);
@@ -1195,15 +1197,18 @@ PP = p;
o1 |= 1<<22;
break;
- case 60: /* movb R(R),R -> ldrsb indexed */
+ case 60: /* movb R(R),R -> ldrb indexed */
if(p->from.reg == NREG) {
diag("byte MOV from shifter operand");
goto mov;
}
if(p->from.offset&(~0xf))
- diag("bad shift in LDRSB");
- o1 = olhrr(p->from.offset, p->from.reg, p->to.reg, p->scond);
- o1 ^= (1<<5)|(1<<6);
+ diag("bad shift in LDRB");
+ o1 = olr(p->from.offset, p->from.reg, p->to.reg, p->scond);
+ if(p->as == AMOVB) {
+ o1 |= 1<<22; /* B */
+ o1 ^= 1<<25; /* instruction with Rm */
+ }
break;
case 61: /* movw/b/bu R,R<<[IR](R) -> str indexed */