diff options
| author | Damien Zammit <damien@zamaudio.com> | 2024-01-30 08:04:15 +0000 |
|---|---|---|
| committer | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2024-01-30 19:25:30 +0100 |
| commit | 366954d50be00d085d44a8c461a80f2d0b663224 (patch) | |
| tree | bf1d49c5956030035aba79347493b439b0c26626 /i386 | |
| parent | 6bca5c2873ef4cfccd8d2ebeedad29c9d5a6ec7f (diff) | |
apic: Set up LAPICs in xAPIC mode
Clear flag in msr for xAPIC mode.
Message-ID: <20240130080405.1304381-1-damien@zamaudio.com>
Diffstat (limited to 'i386')
| -rw-r--r-- | i386/i386/apic.h | 3 | ||||
| -rw-r--r-- | i386/i386/cpuboot.S | 4 | ||||
| -rw-r--r-- | i386/i386at/boothdr.S | 3 |
3 files changed, 6 insertions, 4 deletions
diff --git a/i386/i386/apic.h b/i386/i386/apic.h index b8fff2af..e410e9c6 100644 --- a/i386/i386/apic.h +++ b/i386/i386/apic.h @@ -302,7 +302,8 @@ extern int cpu_id_lut[]; #define APIC_MSR 0x1b #define APIC_MSR_BSP 0x100 /* Processor is a BSP */ -#define APIC_MSR_ENABLE 0x800 +#define APIC_MSR_X2APIC 0x400 /* LAPIC is in x2APIC mode */ +#define APIC_MSR_ENABLE 0x800 /* LAPIC is enabled */ /* Set or clear a bit in a 255-bit APIC mask register. These registers are spread through eight 32-bit registers. */ diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S index c85c4ddb..13d9160e 100644 --- a/i386/i386/cpuboot.S +++ b/i386/i386/cpuboot.S @@ -175,13 +175,13 @@ _apboot: mov apboot_idt_ptr, %ebx lidt (%ebx) - /* Enable local apic */ + /* Enable local apic in xAPIC mode */ xorl %eax, %eax xorl %edx, %edx movl $APIC_MSR, %ecx rdmsr orl $APIC_MSR_ENABLE, %eax - andl $(~APIC_MSR_BSP), %eax + andl $(~(APIC_MSR_BSP | APIC_MSR_X2APIC)), %eax movl $APIC_MSR, %ecx wrmsr diff --git a/i386/i386at/boothdr.S b/i386/i386at/boothdr.S index 6696d966..daaf57db 100644 --- a/i386/i386at/boothdr.S +++ b/i386/i386at/boothdr.S @@ -67,13 +67,14 @@ boot_entry: movl $solid_intstack+INTSTACK_SIZE-4, %esp andl $0xfffffff0,%esp - /* Enable local apic */ + /* Enable local apic in xAPIC mode */ xorl %eax, %eax xorl %edx, %edx movl $APIC_MSR, %ecx rdmsr orl $APIC_MSR_ENABLE, %eax orl $APIC_MSR_BSP, %eax + andl $(~APIC_MSR_X2APIC), %eax movl $APIC_MSR, %ecx wrmsr |