diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 75 |
1 files changed, 58 insertions, 17 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index fdfbc6566a5..64049a6e521 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -835,8 +835,8 @@ ;; complex forms. Basic data transfer is done later. (define_insn "zero_extendqi<mode>2" - [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wa,^v") - (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,v")))] + [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,wa,^v") + (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,?Z,v")))] "" "@ lbz%U1%X1 %0,%1 @@ -889,8 +889,8 @@ (define_insn "zero_extendhi<mode>2" - [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wa,^v") - (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))] + [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,wa,^v") + (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,?Z,v")))] "" "@ lhz%U1%X1 %0,%1 @@ -944,7 +944,7 @@ (define_insn "zero_extendsi<mode>2" [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa") - (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))] + (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,?Z,?Z,r,wa,wa")))] "" "@ lwz%U1%X1 %0,%1 @@ -7496,7 +7496,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=r, r, r, d, v, - m, Z, Z, + m, ?Z, ?Z, r, r, r, r, wa, wa, wa, v, wa, v, v, @@ -7504,7 +7504,7 @@ r, *h, *h") (match_operand:SI 1 "input_operand" "r, U, - m, Z, Z, + m, ?Z, ?Z, r, d, v, I, L, eI, n, wa, O, wM, wB, @@ -7785,11 +7785,11 @@ ;; MTVSRWZ MF%1 MT%1 NOP (define_insn "*mov<mode>_internal" [(set (match_operand:QHI 0 "nonimmediate_operand" - "=r, r, wa, m, Z, r, + "=r, r, wa, m, ?Z, r, wa, wa, wa, v, ?v, r, wa, r, *c*l, *h") (match_operand:QHI 1 "input_operand" - "r, m, Z, r, wa, i, + "r, m, ?Z, r, wa, i, wa, O, wM, wB, wS, wa, r, *h, r, 0"))] "gpc_reg_operand (operands[0], <MODE>mode) @@ -7973,10 +7973,10 @@ ;; FMR MR MT%0 MF%1 NOP (define_insn "movsd_hardfloat" [(set (match_operand:SD 0 "nonimmediate_operand" - "=!r, d, m, Z, ?d, ?r, + "=!r, d, m, ?Z, ?d, ?r, f, !r, *c*l, !r, *h") (match_operand:SD 1 "input_operand" - "m, Z, r, wx, r, d, + "m, ?Z, r, wx, r, d, f, r, r, *h, 0"))] "(register_operand (operands[0], SDmode) || register_operand (operands[1], SDmode)) @@ -14580,10 +14580,10 @@ [(set_attr "type" "fp,fpstore,mtvsr,mfvsr,store")]) (define_insn_and_split "unpack<mode>_nodm" - [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m") + [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,m") (unspec:<FP128_64> - [(match_operand:FMOVE128 1 "register_operand" "d,d") - (match_operand:QI 2 "const_0_to_1_operand" "i,i")] + [(match_operand:FMOVE128 1 "register_operand" "d,d,r") + (match_operand:QI 2 "const_0_to_1_operand" "i,i,i")] UNSPEC_UNPACK_128BIT))] "(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (<MODE>mode)" "#" @@ -14600,15 +14600,28 @@ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno); } - [(set_attr "type" "fp,fpstore")]) + [(set_attr "type" "fp,fpstore,store")]) -(define_insn_and_split "pack<mode>" +(define_expand "pack<mode>" + [(use (match_operand:FMOVE128 0 "register_operand")) + (use (match_operand:<FP128_64> 1 "register_operand")) + (use (match_operand:<FP128_64> 2 "register_operand"))] + "FLOAT128_2REG_P (<MODE>mode)" +{ + if (TARGET_HARD_FLOAT) + emit_insn (gen_pack<mode>_hard (operands[0], operands[1], operands[2])); + else + emit_insn (gen_pack<mode>_soft (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_insn_and_split "pack<mode>_hard" [(set (match_operand:FMOVE128 0 "register_operand" "=&d") (unspec:FMOVE128 [(match_operand:<FP128_64> 1 "register_operand" "d") (match_operand:<FP128_64> 2 "register_operand" "d")] UNSPEC_PACK_128BIT))] - "FLOAT128_2REG_P (<MODE>mode)" + "FLOAT128_2REG_P (<MODE>mode) && TARGET_HARD_FLOAT" "#" "&& reload_completed" [(set (match_dup 3) (match_dup 1)) @@ -14626,6 +14639,34 @@ [(set_attr "type" "fp") (set_attr "length" "8")]) +(define_insn_and_split "pack<mode>_soft" + [(set (match_operand:FMOVE128 0 "register_operand" "=&r") + (unspec:FMOVE128 + [(match_operand:<FP128_64> 1 "register_operand" "r") + (match_operand:<FP128_64> 2 "register_operand" "r")] + UNSPEC_PACK_128BIT))] + "FLOAT128_2REG_P (<MODE>mode) && TARGET_SOFT_FLOAT" + "#" + "&& reload_completed" + [(set (match_dup 3) (match_dup 1)) + (set (match_dup 4) (match_dup 2))] +{ + unsigned dest_hi = REGNO (operands[0]); + unsigned dest_lo = dest_hi + (TARGET_POWERPC64 ? 1 : 2); + + gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo)); + gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo)); + + operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi); + operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo); +} + [(set_attr "type" "integer") + (set (attr "length") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16")))]) + (define_insn "unpack<mode>" [(set (match_operand:DI 0 "register_operand" "=wa,wa") (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa") |