From 07527728ff3afe44109f7c5a9e40979ef856266e Mon Sep 17 00:00:00 2001
From: AlmuHS <almuhs@github.com>
Date: Sat, 18 May 2019 17:51:11 +0200
Subject: undone experiment

---
 i386/i386/cpuboot.S | 48 +++++++++++++++++++++++++++++++++++++++++++++---
 i386/i386/mp_desc.c | 36 ------------------------------------
 i386/i386/mp_desc.h |  1 -
 3 files changed, 45 insertions(+), 40 deletions(-)

diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S
index b15640c7..7ebd76f2 100644
--- a/i386/i386/cpuboot.S
+++ b/i386/i386/cpuboot.S
@@ -88,6 +88,50 @@ _apboot:
 	movw	%ax,%es
 	movw	%ax,%ss
 
+#if PAE
+    //set_cr3((unsigned)_kvtophys(kernel_pmap->pdpbase));
+	movl %cr3, %eax
+	movl %eax, _kvtophys(kernel_pmap->pdpbase)
+	movl %eax, %cr3
+
+#ifndef	MACH_HYP
+    if (!CPU_HAS_FEATURE(CPU_FEATURE_PAE))
+        panic("CPU doesn't have support for PAE.");
+    //set_cr4(get_cr4() | CR4_PAE);
+	movl %cr4, %eax
+	orl CR4_PAE, %eax
+	movl %eax, %cr4
+
+#endif	/* MACH_HYP */
+#else
+    set_cr3((unsigned)_kvtophys(kernel_page_dir));
+#endif	/* PAE */
+#ifndef	MACH_HYP
+    /* Turn paging on.
+     * Also set the WP bit so that on 486 or better processors
+     * page-level write protection works in kernel mode.
+     */
+    //set_cr0(get_cr0() | CR0_PG | CR0_WP);
+	movl %cr0, %eax
+	orl CR0_PG, %eax
+	orl CR0_WP, %eax
+	movl %eax, %cr0	
+
+    //set_cr0(get_cr0() & ~(CR0_CD | CR0_NW));
+	movl %cr0, %eax
+	andl ~(CR0_CD | CR0_NW), %eax 
+	movl %eax, %cr0
+
+
+    if (CPU_HAS_FEATURE(CPU_FEATURE_PGE))
+        //set_cr4(get_cr4() | CR4_PGE);
+		movl %cr4, %eax
+		orl CR4_PGE, %eax
+		mov %eax, %cr4
+
+#endif	/* MACH_HYP */
+
+
 	movl stack_ptr, %esp
 	addl $STACK_SIZE, %esp
 
@@ -97,7 +141,6 @@ _apboot:
 
 	pushl stack_ptr
 
-	call pmap_conf
 	call cpu_ap_main
 	cli
 
@@ -132,5 +175,4 @@ apbootend:
 
     .globl dummyf
 dummyf:
-ret
-
+ret
\ No newline at end of file
diff --git a/i386/i386/mp_desc.c b/i386/i386/mp_desc.c
index 5e3899b7..fb06536c 100644
--- a/i386/i386/mp_desc.c
+++ b/i386/i386/mp_desc.c
@@ -293,42 +293,6 @@ void startup_cpu(uint32_t apic_id)
 
 }
 
-void pmap_conf()
-{
-#ifdef	MACH_PV_PAGETABLES
-    for (i = 0; i < PDPNUM; i++)
-        pmap_set_page_readonly_init((void*) kernel_page_dir + i * INTEL_PGBYTES);
-#if PAE
-    pmap_set_page_readonly_init(kernel_pmap->pdpbase);
-#endif	/* PAE */
-#endif	/* MACH_PV_PAGETABLES */
-#if PAE
-    set_cr3((unsigned)_kvtophys(kernel_pmap->pdpbase));
-#ifndef	MACH_HYP
-    if (!CPU_HAS_FEATURE(CPU_FEATURE_PAE))
-        panic("CPU doesn't have support for PAE.");
-    set_cr4(get_cr4() | CR4_PAE);
-#endif	/* MACH_HYP */
-#else
-    set_cr3((unsigned)_kvtophys(kernel_page_dir));
-#endif	/* PAE */
-#ifndef	MACH_HYP
-    /* Turn paging on.
-     * Also set the WP bit so that on 486 or better processors
-     * page-level write protection works in kernel mode.
-     */
-    set_cr0(get_cr0() | CR0_PG | CR0_WP);
-    set_cr0(get_cr0() & ~(CR0_CD | CR0_NW));
-    if (CPU_HAS_FEATURE(CPU_FEATURE_PGE))
-        set_cr4(get_cr4() | CR4_PGE);
-#endif	/* MACH_HYP */
-    flush_instr_queue();
-#ifdef	MACH_PV_PAGETABLES
-    pmap_clear_bootstrap_pagetable((void *)boot_info.pt_base);
-#endif	/* MACH_PV_PAGETABLES */
-
-}
-
 int
 cpu_setup()
 {
diff --git a/i386/i386/mp_desc.h b/i386/i386/mp_desc.h
index 55f9c08f..549738fc 100644
--- a/i386/i386/mp_desc.h
+++ b/i386/i386/mp_desc.h
@@ -82,7 +82,6 @@ extern kern_return_t intel_startCPU(int slot_num);
 
 extern void interrupt_processor(int cpu);
 extern void startup_cpu(uint32_t apic_id);
-extern void pmap_conf();
 extern int cpu_ap_main();
 extern int cpu_setup();
 
-- 
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