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authorAlmuHS <almuhs@github.com>2019-07-09 01:20:02 +0200
committerAlmuHS <almuhs@github.com>2019-07-09 01:20:02 +0200
commitf60ef1dc556b5c3daf1ba0a6159ce298ba07dc9c (patch)
treec95a6109b4de5ceb77c50e4b3a3e937e8d9babea
parent5d615388d734264701d036ae70396abbd258bbc1 (diff)
docs: update paging section
-rw-r--r--README.md7
1 files changed, 4 insertions, 3 deletions
diff --git a/README.md b/README.md
index 722e75f9..2571cccb 100644
--- a/README.md
+++ b/README.md
@@ -169,6 +169,7 @@ More info in: <https://www.gnu.org/software/hurd/microkernel/mach/gnumach/buildi
- Added paging configuration in [`cpuboot.S`](https://github.com/AlmuHS/GNUMach_SMP/blob/smp/i386/i386/cpuboot.S )
- Added calls to `gdt_init()` and `idt_init()` before call to `slave_main()`, to load final GDT and IDT.
- Enabled call to `slave_main()`, to add AP processors to the kernel
+- Moved paging configuration to `paging_setup()` function
### Recover old *gnumach* APIC headers
@@ -303,11 +304,11 @@ We have split this task in some steps:
Before add the cpus to the kernel, we need to configure paging in them, to allow fully access to the memory.
-To enable paging, we need to initialize CR0, CR3 and CR4 registers. as similar for to [this](https://github.com/AlmuHS/GNUMach_SMP/blob/smp/i386/i386at/model_dep.c#L477-L500).
+To enable paging, we need to initialize CR0, CR3 and CR4 registers. in a similar way to [this](https://github.com/AlmuHS/GNUMach_SMP/blob/smp/i386/i386at/model_dep.c#L477-L500).
-This code, translated to assembly, has been added to [`cpuboot.S`](https://github.com/AlmuHS/GNUMach_SMP/blob/wip/i386/i386/cpuboot.S) assembly routine.
+This code has been copied in `paging_setup()` function, in `mp_desc.c`. The processor, at starts, isn't capable to read the content from a pointer, so we copied the memory address of `kernel_page_dir` and `pdpbase` in two temporary integer variables: `kernel_page_dir_addr`, and `pdpbase_addr`.
-The paging initialization requires a temporary mapping in some low memory address.
+The paging initialization also requires a temporary mapping in some low memory address.
We keep the temporary mapping done in BSP processor until all AP will be enabled.
## Add AP processors to the kernel