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authorAlmuHS <almuhs@github.com>2019-07-08 21:14:52 +0200
committerAlmuHS <almuhs@github.com>2019-07-08 21:14:52 +0200
commit1b05999a3d13b1c7ad9a57bfb85b8e69ec9a6c96 (patch)
treed56da0a123ea6efc8021b8206693f5eb7e5d22ce
parente4df7e2dc4d1d97900d3189a76a8116934b5467a (diff)
experiment: move paging enabling to C
-rw-r--r--i386/i386/cpuboot.S133
-rw-r--r--i386/i386/mp_desc.c28
-rw-r--r--i386/i386/mp_desc.h1
3 files changed, 96 insertions, 66 deletions
diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S
index f0af9cf9..e1e3635a 100644
--- a/i386/i386/cpuboot.S
+++ b/i386/i386/cpuboot.S
@@ -85,72 +85,72 @@ _apboot:
movw %ax,%es
movw %ax,%ss
-#if PAE
- //set_cr3((unsigned)_kvtophys(kernel_pmap->pdpbase));
- movl (pdpbase_addr), %eax
- movl %eax, %cr3
-
-#ifndef MACH_HYP
- //if (!CPU_HAS_FEATURE(CPU_FEATURE_PAE))
- movl (cpu_features), %eax
- test $(1<<CPU_FEATURE_PAE), %eax
- jnz setpae
- jz nopae
-
-setpae:
- //set_cr4(get_cr4() | CR4_PAE);
- movl %cr4, %eax
- orl $CR4_PAE, %eax
- movl %eax, %cr4
-nopae:
- nop
-
-#endif /* MACH_HYP */
-#else
- //set_cr3((unsigned)_kvtophys(kernel_page_dir));
- movl (kernel_page_dir_addr), %eax
- movl %eax, %cr3
-
-#endif /* PAE */
-#ifndef MACH_HYP
- /* Turn paging on.
- * Also set the WP bit so that on 486 or better processors
- * page-level write protection works in kernel mode.
- */
- //set_cr0(get_cr0() | CR0_PG | CR0_WP);
- //movl %cr0, %eax
- //orl $(CR0_PG | CR0_WP), %eax
- movl $0x8001003b, %eax
- movl %eax, %cr0
-
- //set_cr0(get_cr0() & ~(CR0_CD | CR0_NW));
- movl %cr0, %eax
- andl $(~(CR0_CD | CR0_NW)), %eax
- movl %eax, %cr0
-
-
- //if (CPU_HAS_FEATURE(CPU_FEATURE_PGE))
- movl (cpu_features), %eax
- test $(1<<CPU_FEATURE_PGE), %eax
- jnz setpge
- jz nopge
-
- setpge:
- //set_cr4(get_cr4() | CR4_PGE);
- movl %cr4, %eax
- orl $CR4_PGE, %eax
- movl %eax, %cr4
- nopge:
- nop
-
-#endif /* MACH_HYP */
-
- //flush_instr_queue();
- jmp 0f
-0:
- //flush_tlb();
- movl %cr3, %eax
- movl %eax, %cr3
+/*#if PAE*/
+/* //set_cr3((unsigned)_kvtophys(kernel_pmap->pdpbase));*/
+/* movl (pdpbase_addr), %eax*/
+/* movl %eax, %cr3*/
+
+/*#ifndef MACH_HYP*/
+/* //if (!CPU_HAS_FEATURE(CPU_FEATURE_PAE))*/
+/* movl (cpu_features), %eax*/
+/* test $(1<<CPU_FEATURE_PAE), %eax*/
+/* jnz setpae*/
+/* jz nopae*/
+
+/*setpae:*/
+/* //set_cr4(get_cr4() | CR4_PAE);*/
+/* movl %cr4, %eax*/
+/* orl $CR4_PAE, %eax*/
+/* movl %eax, %cr4*/
+/*nopae:*/
+/* nop*/
+
+/*#endif /* MACH_HYP */
+/*#else*/
+/* //set_cr3((unsigned)_kvtophys(kernel_page_dir));*/
+/* movl (kernel_page_dir_addr), %eax*/
+/* movl %eax, %cr3*/
+
+/*#endif PAE */
+/*#ifndef MACH_HYP*/
+/* /* Turn paging on.*/
+/* * Also set the WP bit so that on 486 or better processors*/
+/* * page-level write protection works in kernel mode.*/
+/* */
+/* //set_cr0(get_cr0() | CR0_PG | CR0_WP);*/
+/* //movl %cr0, %eax*/
+/* //orl $(CR0_PG | CR0_WP), %eax*/
+/* movl $0x8001003b, %eax*/
+/* movl %eax, %cr0*/
+
+/* //set_cr0(get_cr0() & ~(CR0_CD | CR0_NW));*/
+/* movl %cr0, %eax*/
+/* andl $(~(CR0_CD | CR0_NW)), %eax*/
+/* movl %eax, %cr0*/
+
+
+/* //if (CPU_HAS_FEATURE(CPU_FEATURE_PGE))*/
+/* movl (cpu_features), %eax*/
+/* test $(1<<CPU_FEATURE_PGE), %eax*/
+/* jnz setpge*/
+/* jz nopge*/
+
+/* setpge:*/
+/* //set_cr4(get_cr4() | CR4_PGE);*/
+/* movl %cr4, %eax*/
+/* orl $CR4_PGE, %eax*/
+/* movl %eax, %cr4*/
+/* nopge:*/
+/* nop*/
+
+/*#endif /* MACH_HYP */
+
+/* //flush_instr_queue();*/
+/* jmp 0f*/
+/*0:*/
+/* //flush_tlb();*/
+/* movl %cr3, %eax*/
+/* movl %eax, %cr3*/
movl stack_ptr, %esp
@@ -162,6 +162,7 @@ nopae:
pushl stack_ptr
+ call paging_setup
call cpu_ap_main
cli
diff --git a/i386/i386/mp_desc.c b/i386/i386/mp_desc.c
index 3bb207b1..e9834111 100644
--- a/i386/i386/mp_desc.c
+++ b/i386/i386/mp_desc.c
@@ -367,6 +367,34 @@ cpu_setup()
return 0;
}
+void paging_setup(){
+
+#if PAE
+ set_cr3(pdpbase_addr);
+#ifndef MACH_HYP
+ if (!CPU_HAS_FEATURE(CPU_FEATURE_PAE))
+ set_cr4(get_cr4() | CR4_PAE);
+#endif /* MACH_HYP */
+#else
+ set_cr3(kernel_page_dir_addr);
+#endif /* PAE */
+#ifndef MACH_HYP
+ /* Turn paging on.
+ * Also set the WP bit so that on 486 or better processors
+ * page-level write protection works in kernel mode.
+ */
+ set_cr0(get_cr0() | CR0_PG | CR0_WP);
+ set_cr0(get_cr0() & ~(CR0_CD | CR0_NW));
+
+ if (CPU_HAS_FEATURE(CPU_FEATURE_PGE))
+ set_cr4(get_cr4() | CR4_PGE);
+
+#endif /* MACH_HYP */
+
+ flush_instr_queue();
+ flush_tlb();
+
+}
int
cpu_ap_main()
diff --git a/i386/i386/mp_desc.h b/i386/i386/mp_desc.h
index 549738fc..556f36bc 100644
--- a/i386/i386/mp_desc.h
+++ b/i386/i386/mp_desc.h
@@ -89,5 +89,6 @@ extern int cpu_setup();
#endif /* MULTIPROCESSOR */
extern void start_other_cpus(void);
+extern void paging_setup();
#endif /* _I386_MP_DESC_H_ */