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| author | Tamar Christina <tamar.christina@arm.com> | 2022-12-13 18:01:15 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2022-12-13 18:01:15 +0000 |
| commit | 69ec1e2065ac43eea44fdfa703cf027ce72a62da (patch) | |
| tree | 50c8cc2ae7f6efc20b89dcc5a30dea3b7b37e58a | |
| parent | 33be3ee36a7e2c0be383ec01b5fbc9aef39568fd (diff) | |
AArch64: Fix ILP32 tbranch
the baremetal builds are currently broken because the shift ends up in the wrong
representation if the mode is SImode and the shift amount if 31. To fix this
create the rtx constant with an explicit mode so the backend passes know which
representation it needs to take.
gcc/ChangeLog:
* config/aarch64/aarch64.md (tbranch_<code><mode>3): Use gen_int_mode.
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d749c98eef6..6c27fb89e66 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -957,7 +957,7 @@ { rtx bitvalue = gen_reg_rtx (<ZEROM>mode); rtx reg = gen_lowpart (<ZEROM>mode, operands[0]); - rtx val = GEN_INT (1UL << UINTVAL (operands[1])); + rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), <MODE>mode); emit_insn (gen_and<zerom>3 (bitvalue, reg, val)); operands[1] = const0_rtx; operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue, |